counter: stm32-lptimer-cnt: Provide defines for clock polarities
The STM32 low-power timer permits configuration of the clock polarity via the LPTIMX_CFGR register CKPOL bits. This patch provides preprocessor defines for the supported clock polarities. Cc: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/a111c8905c467805ca530728f88189b59430f27e.1630031207.git.vilhelm.gray@gmail.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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@ -140,9 +140,9 @@ static const enum counter_function stm32_lptim_cnt_functions[] = {
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};
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enum stm32_lptim_synapse_action {
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STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE,
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STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE,
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STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES,
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STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE = STM32_LPTIM_CKPOL_RISING_EDGE,
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STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE = STM32_LPTIM_CKPOL_FALLING_EDGE,
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STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES = STM32_LPTIM_CKPOL_BOTH_EDGES,
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STM32_LPTIM_SYNAPSE_ACTION_NONE,
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};
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@ -45,6 +45,11 @@
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#define STM32_LPTIM_PRESC GENMASK(11, 9)
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#define STM32_LPTIM_CKPOL GENMASK(2, 1)
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/* STM32_LPTIM_CKPOL */
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#define STM32_LPTIM_CKPOL_RISING_EDGE 0
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#define STM32_LPTIM_CKPOL_FALLING_EDGE 1
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#define STM32_LPTIM_CKPOL_BOTH_EDGES 2
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/* STM32_LPTIM_ARR */
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#define STM32_LPTIM_MAX_ARR 0xFFFF
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