forked from Minki/linux
gpu/drm/radeon: Fix typo in comments
Remove the repeated word 'the' from comments Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2802,8 +2802,8 @@ ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of t
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ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
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usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
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usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
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usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
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usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
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*/
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@ -353,7 +353,7 @@
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# define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0
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# define R300_PVS_CNTL_1_POS_END_SHIFT 10
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# define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20
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/* Addresses are relative the the vertex program parameters area. */
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/* Addresses are relative the vertex program parameters area. */
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#define R300_VAP_PVS_CNTL_2 0x22D4
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# define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0
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# define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16
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@ -406,7 +406,7 @@ void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
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/*
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* radeon_wb_*()
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* Writeback is the the method by which the the GPU updates special pages
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* Writeback is the method by which the GPU updates special pages
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* in memory with the status of certain GPU events (fences, ring pointers,
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* etc.).
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*/
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@ -50,7 +50,7 @@
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* for GPU/CPU synchronization. When the fence is written,
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* it is expected that all buffers associated with that fence
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* are no longer in use by the associated ring on the GPU and
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* that the the relevant GPU caches have been flushed. Whether
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* that the relevant GPU caches have been flushed. Whether
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* we use a scratch register or memory location depends on the asic
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* and whether writeback is enabled.
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*/
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@ -41,7 +41,7 @@
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* (uncached system pages).
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* Each VM has an ID associated with it and there is a page table
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* associated with each VMID. When execting a command buffer,
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* the kernel tells the the ring what VMID to use for that command
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* the kernel tells the ring what VMID to use for that command
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* buffer. VMIDs are allocated dynamically as commands are submitted.
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* The userspace drivers maintain their own address space and the kernel
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* sets up their pages tables accordingly when they submit their
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