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ARM: dts: r9a06g032: Add the watchdog nodes

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This SoC includes 2 watchdog controllers (one per A7 core).

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
Link: https://lore.kernel.org/r/20220221095032.95054-4-jjhiblot@traphandler.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Jean-Jacques Hiblot 2022-02-21 10:50:29 +01:00 committed by Geert Uytterhoeven
parent a3a59919ab
commit 045d0625d3
1 changed files with 16 additions and 0 deletions
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16
arch/arm/boot/dts/r9a06g032.dtsi
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@ -66,6 +66,22 @@
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
ranges; ranges;
wdt0: watchdog@40008000 {
compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
reg = <0x40008000 0x1000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
status = "disabled";
};
wdt1: watchdog@40009000 {
compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
reg = <0x40009000 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
status = "disabled";
};
sysctrl: system-controller@4000c000 { sysctrl: system-controller@4000c000 {
compatible = "renesas,r9a06g032-sysctrl"; compatible = "renesas,r9a06g032-sysctrl";
reg = <0x4000c000 0x1000>; reg = <0x4000c000 0x1000>;