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drm/i915: Setup EMR first on all gen2-4

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Unify the appaerance of the gen2-4 irq postinstall hooks a little
bit by doing the EMR setup first on all the platforms.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170818183705.27850-7-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä 2017-08-18 21:36:55 +03:00
parent e9e9848a6b
commit 045cebd2e4
1 changed files with 19 additions and 18 deletions
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37
drivers/gpu/drm/i915/i915_irq.c
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@ -3616,8 +3616,8 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
u16 enable_mask; u16 enable_mask;
I915_WRITE16(EMR, I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE |
~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); I915_ERROR_MEMORY_REFRESH));
/* Unmask the interrupts that we always want on. */ /* Unmask the interrupts that we always want on. */
dev_priv->irq_mask = dev_priv->irq_mask =
@ -3745,7 +3745,8 @@ static int i915_irq_postinstall(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
u32 enable_mask; u32 enable_mask;
I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
I915_ERROR_MEMORY_REFRESH));
/* Unmask the interrupts that we always want on. */ /* Unmask the interrupts that we always want on. */
dev_priv->irq_mask = dev_priv->irq_mask =
@ -3921,6 +3922,21 @@ static int i965_irq_postinstall(struct drm_device *dev)
u32 enable_mask; u32 enable_mask;
u32 error_mask; u32 error_mask;
/*
* Enable some error detection, note the instruction error mask
* bit is reserved, so we leave it masked.
*/
if (IS_G4X(dev_priv)) {
error_mask = ~(GM45_ERROR_PAGE_TABLE |
GM45_ERROR_MEM_PRIV |
GM45_ERROR_CP_PRIV |
I915_ERROR_MEMORY_REFRESH);
} else {
error_mask = ~(I915_ERROR_PAGE_TABLE |
I915_ERROR_MEMORY_REFRESH);
}
I915_WRITE(EMR, error_mask);
/* Unmask the interrupts that we always want on. */ /* Unmask the interrupts that we always want on. */
dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
I915_DISPLAY_PORT_INTERRUPT | I915_DISPLAY_PORT_INTERRUPT |
@ -3942,21 +3958,6 @@ static int i965_irq_postinstall(struct drm_device *dev)
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
spin_unlock_irq(&dev_priv->irq_lock); spin_unlock_irq(&dev_priv->irq_lock);
/*
* Enable some error detection, note the instruction error mask
* bit is reserved, so we leave it masked.
*/
if (IS_G4X(dev_priv)) {
error_mask = ~(GM45_ERROR_PAGE_TABLE |
GM45_ERROR_MEM_PRIV |
GM45_ERROR_CP_PRIV |
I915_ERROR_MEMORY_REFRESH);
} else {
error_mask = ~(I915_ERROR_PAGE_TABLE |
I915_ERROR_MEMORY_REFRESH);
}
I915_WRITE(EMR, error_mask);
GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask); GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);