forked from Minki/linux
ath10k: define structures for CE ctrl/misc register
Define structures for the copy engine ctrl/misc registers, that includes CE CMD halt, watermark source, watermark destination, host IE ring, source, destination and dmax ring. This adds support to avoid the conditional compilation, code optimization and dynamic configuration of the copy engine register map for respective hardware bus interface. Signed-off-by: Sarada Prasanna Garnayak <c_sgarna@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
This commit is contained in:
Sarada Prasanna Garnayak
Kalle Valo
parent
9a993cc1ea
commit
03a016f894
@ -59,205 +59,243 @@
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* the buffer is sent/received.
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*/
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static inline unsigned int
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ath10k_set_ring_byte(unsigned int offset,
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struct ath10k_hw_ce_regs_addr_map *addr_map)
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{
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return ((offset << addr_map->lsb) & addr_map->mask);
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}
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static inline unsigned int
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ath10k_get_ring_byte(unsigned int offset,
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struct ath10k_hw_ce_regs_addr_map *addr_map)
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{
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return ((offset & addr_map->mask) >> (addr_map->lsb));
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}
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static inline void ath10k_ce_dest_ring_write_index_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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ath10k_pci_write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n);
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ath10k_pci_write32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->dst_wr_index_addr, n);
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}
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static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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return ath10k_pci_read32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS);
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return ath10k_pci_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->dst_wr_index_addr);
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}
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static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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ath10k_pci_write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n);
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ath10k_pci_write32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->sr_wr_index_addr, n);
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}
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static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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return ath10k_pci_read32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS);
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return ath10k_pci_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->sr_wr_index_addr);
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}
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static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_SRRI_ADDRESS);
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return ath10k_pci_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->current_srri_addr);
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}
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static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int addr)
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{
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ath10k_pci_write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr);
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ath10k_pci_write32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->sr_base_addr, addr);
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}
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static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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ath10k_pci_write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n);
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ath10k_pci_write32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->sr_size_addr, n);
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}
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static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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u32 ctrl1_addr = ath10k_pci_read32((ar),
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(ce_ctrl_addr) + CE_CTRL1_ADDRESS);
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struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
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u32 ctrl1_addr = ath10k_pci_read32(ar,
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ce_ctrl_addr + ctrl_regs->addr);
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ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
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(ctrl1_addr & ~CE_CTRL1_DMAX_LENGTH_MASK) |
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CE_CTRL1_DMAX_LENGTH_SET(n));
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ath10k_pci_write32(ar, ce_ctrl_addr + ctrl_regs->addr,
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(ctrl1_addr & ~(ctrl_regs->dmax->mask)) |
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ath10k_set_ring_byte(n, ctrl_regs->dmax));
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}
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static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);
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struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
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u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + ctrl_regs->addr);
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ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
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(ctrl1_addr & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) |
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CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n));
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ath10k_pci_write32(ar, ce_ctrl_addr + ctrl_regs->addr,
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(ctrl1_addr & ~(ctrl_regs->src_ring->mask)) |
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ath10k_set_ring_byte(n, ctrl_regs->src_ring));
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}
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static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);
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struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
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u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + ctrl_regs->addr);
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ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
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(ctrl1_addr & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) |
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CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n));
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ath10k_pci_write32(ar, ce_ctrl_addr + ctrl_regs->addr,
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(ctrl1_addr & ~(ctrl_regs->dst_ring->mask)) |
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ath10k_set_ring_byte(n, ctrl_regs->dst_ring));
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}
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static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_DRRI_ADDRESS);
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return ath10k_pci_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->current_drri_addr);
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}
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static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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u32 addr)
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{
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ath10k_pci_write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr);
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ath10k_pci_write32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->dr_base_addr, addr);
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}
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static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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ath10k_pci_write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n);
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ath10k_pci_write32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->dr_size_addr, n);
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}
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static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);
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struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;
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u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + srcr_wm->addr);
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ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,
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(addr & ~SRC_WATERMARK_HIGH_MASK) |
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SRC_WATERMARK_HIGH_SET(n));
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ath10k_pci_write32(ar, ce_ctrl_addr + srcr_wm->addr,
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(addr & ~(srcr_wm->wm_high->mask)) |
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(ath10k_set_ring_byte(n, srcr_wm->wm_high)));
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}
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static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);
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struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;
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u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + srcr_wm->addr);
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ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,
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(addr & ~SRC_WATERMARK_LOW_MASK) |
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SRC_WATERMARK_LOW_SET(n));
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ath10k_pci_write32(ar, ce_ctrl_addr + srcr_wm->addr,
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(addr & ~(srcr_wm->wm_low->mask)) |
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(ath10k_set_ring_byte(n, srcr_wm->wm_low)));
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}
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static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);
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struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;
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u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + dstr_wm->addr);
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ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,
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(addr & ~DST_WATERMARK_HIGH_MASK) |
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DST_WATERMARK_HIGH_SET(n));
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ath10k_pci_write32(ar, ce_ctrl_addr + dstr_wm->addr,
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(addr & ~(dstr_wm->wm_high->mask)) |
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(ath10k_set_ring_byte(n, dstr_wm->wm_high)));
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}
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static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);
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struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;
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u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + dstr_wm->addr);
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ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,
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(addr & ~DST_WATERMARK_LOW_MASK) |
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DST_WATERMARK_LOW_SET(n));
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ath10k_pci_write32(ar, ce_ctrl_addr + dstr_wm->addr,
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(addr & ~(dstr_wm->wm_low->mask)) |
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(ath10k_set_ring_byte(n, dstr_wm->wm_low)));
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}
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static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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u32 host_ie_addr = ath10k_pci_read32(ar,
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ce_ctrl_addr + HOST_IE_ADDRESS);
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struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;
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u32 host_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->host_ie_addr);
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ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
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host_ie_addr | HOST_IE_COPY_COMPLETE_MASK);
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ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,
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host_ie_addr | host_ie->copy_complete->mask);
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}
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static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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u32 host_ie_addr = ath10k_pci_read32(ar,
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ce_ctrl_addr + HOST_IE_ADDRESS);
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struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;
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u32 host_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->host_ie_addr);
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ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
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host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK);
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ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,
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host_ie_addr & ~(host_ie->copy_complete->mask));
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}
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static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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u32 host_ie_addr = ath10k_pci_read32(ar,
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ce_ctrl_addr + HOST_IE_ADDRESS);
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struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
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u32 host_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->host_ie_addr);
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ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
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host_ie_addr & ~CE_WATERMARK_MASK);
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ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,
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host_ie_addr & ~(wm_regs->wm_mask));
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}
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static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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u32 misc_ie_addr = ath10k_pci_read32(ar,
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ce_ctrl_addr + MISC_IE_ADDRESS);
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struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;
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u32 misc_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->misc_ie_addr);
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ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,
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misc_ie_addr | CE_ERROR_MASK);
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ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,
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misc_ie_addr | misc_regs->err_mask);
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}
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static inline void ath10k_ce_error_intr_disable(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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u32 misc_ie_addr = ath10k_pci_read32(ar,
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ce_ctrl_addr + MISC_IE_ADDRESS);
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struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;
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u32 misc_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->misc_ie_addr);
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ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,
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misc_ie_addr & ~CE_ERROR_MASK);
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ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,
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misc_ie_addr & ~(misc_regs->err_mask));
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}
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static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int mask)
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{
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ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask);
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struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
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ath10k_pci_write32(ar, ce_ctrl_addr + wm_regs->addr, mask);
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}
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/*
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@ -719,13 +757,13 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
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struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
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u32 ctrl_addr = ce_state->ctrl_addr;
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spin_lock_bh(&ar_pci->ce_lock);
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/* Clear the copy-complete interrupts that will be handled here. */
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ath10k_ce_engine_int_status_clear(ar, ctrl_addr,
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HOST_IS_COPY_COMPLETE_MASK);
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ath10k_ce_engine_int_status_clear(ar, ctrl_addr, wm_regs->cc_mask);
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spin_unlock_bh(&ar_pci->ce_lock);
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@ -741,7 +779,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
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* Misc CE interrupts are not being handled, but still need
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* to be cleared.
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*/
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ath10k_ce_engine_int_status_clear(ar, ctrl_addr, CE_WATERMARK_MASK);
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ath10k_ce_engine_int_status_clear(ar, ctrl_addr, wm_regs->wm_mask);
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spin_unlock_bh(&ar_pci->ce_lock);
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}
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@ -263,143 +263,11 @@ struct ce_attr {
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void (*recv_cb)(struct ath10k_ce_pipe *);
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};
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#define SR_BA_ADDRESS 0x0000
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#define SR_SIZE_ADDRESS 0x0004
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#define DR_BA_ADDRESS 0x0008
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#define DR_SIZE_ADDRESS 0x000c
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#define CE_CMD_ADDRESS 0x0018
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#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB 17
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#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
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#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
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#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \
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(((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
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CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB 16
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \
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(((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \
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CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \
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(((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
|
||||
CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
|
||||
|
||||
#define CE_CTRL1_DMAX_LENGTH_MSB 15
|
||||
#define CE_CTRL1_DMAX_LENGTH_LSB 0
|
||||
#define CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
|
||||
#define CE_CTRL1_DMAX_LENGTH_GET(x) \
|
||||
(((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB)
|
||||
#define CE_CTRL1_DMAX_LENGTH_SET(x) \
|
||||
(((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
|
||||
|
||||
#define CE_CTRL1_ADDRESS 0x0010
|
||||
#define CE_CTRL1_HW_MASK 0x0007ffff
|
||||
#define CE_CTRL1_SW_MASK 0x0007ffff
|
||||
#define CE_CTRL1_HW_WRITE_MASK 0x00000000
|
||||
#define CE_CTRL1_SW_WRITE_MASK 0x0007ffff
|
||||
#define CE_CTRL1_RSTMASK 0xffffffff
|
||||
#define CE_CTRL1_RESET 0x00000080
|
||||
|
||||
#define CE_CMD_HALT_STATUS_MSB 3
|
||||
#define CE_CMD_HALT_STATUS_LSB 3
|
||||
#define CE_CMD_HALT_STATUS_MASK 0x00000008
|
||||
#define CE_CMD_HALT_STATUS_GET(x) \
|
||||
(((x) & CE_CMD_HALT_STATUS_MASK) >> CE_CMD_HALT_STATUS_LSB)
|
||||
#define CE_CMD_HALT_STATUS_SET(x) \
|
||||
(((0 | (x)) << CE_CMD_HALT_STATUS_LSB) & CE_CMD_HALT_STATUS_MASK)
|
||||
#define CE_CMD_HALT_STATUS_RESET 0
|
||||
#define CE_CMD_HALT_MSB 0
|
||||
#define CE_CMD_HALT_MASK 0x00000001
|
||||
|
||||
#define HOST_IE_COPY_COMPLETE_MSB 0
|
||||
#define HOST_IE_COPY_COMPLETE_LSB 0
|
||||
#define HOST_IE_COPY_COMPLETE_MASK 0x00000001
|
||||
#define HOST_IE_COPY_COMPLETE_GET(x) \
|
||||
(((x) & HOST_IE_COPY_COMPLETE_MASK) >> HOST_IE_COPY_COMPLETE_LSB)
|
||||
#define HOST_IE_COPY_COMPLETE_SET(x) \
|
||||
(((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK)
|
||||
#define HOST_IE_COPY_COMPLETE_RESET 0
|
||||
#define HOST_IE_ADDRESS 0x002c
|
||||
|
||||
#define HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
|
||||
#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008
|
||||
#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004
|
||||
#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002
|
||||
#define HOST_IS_COPY_COMPLETE_MASK 0x00000001
|
||||
#define HOST_IS_ADDRESS 0x0030
|
||||
|
||||
#define MISC_IE_ADDRESS 0x0034
|
||||
|
||||
#define MISC_IS_AXI_ERR_MASK 0x00000400
|
||||
|
||||
#define MISC_IS_DST_ADDR_ERR_MASK 0x00000200
|
||||
#define MISC_IS_SRC_LEN_ERR_MASK 0x00000100
|
||||
#define MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080
|
||||
#define MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040
|
||||
#define MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020
|
||||
|
||||
#define MISC_IS_ADDRESS 0x0038
|
||||
|
||||
#define SR_WR_INDEX_ADDRESS 0x003c
|
||||
|
||||
#define DST_WR_INDEX_ADDRESS 0x0040
|
||||
|
||||
#define CURRENT_SRRI_ADDRESS 0x0044
|
||||
|
||||
#define CURRENT_DRRI_ADDRESS 0x0048
|
||||
|
||||
#define SRC_WATERMARK_LOW_MSB 31
|
||||
#define SRC_WATERMARK_LOW_LSB 16
|
||||
#define SRC_WATERMARK_LOW_MASK 0xffff0000
|
||||
#define SRC_WATERMARK_LOW_GET(x) \
|
||||
(((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB)
|
||||
#define SRC_WATERMARK_LOW_SET(x) \
|
||||
(((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
|
||||
#define SRC_WATERMARK_LOW_RESET 0
|
||||
#define SRC_WATERMARK_HIGH_MSB 15
|
||||
#define SRC_WATERMARK_HIGH_LSB 0
|
||||
#define SRC_WATERMARK_HIGH_MASK 0x0000ffff
|
||||
#define SRC_WATERMARK_HIGH_GET(x) \
|
||||
(((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB)
|
||||
#define SRC_WATERMARK_HIGH_SET(x) \
|
||||
(((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
|
||||
#define SRC_WATERMARK_HIGH_RESET 0
|
||||
#define SRC_WATERMARK_ADDRESS 0x004c
|
||||
|
||||
#define DST_WATERMARK_LOW_LSB 16
|
||||
#define DST_WATERMARK_LOW_MASK 0xffff0000
|
||||
#define DST_WATERMARK_LOW_SET(x) \
|
||||
(((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
|
||||
#define DST_WATERMARK_LOW_RESET 0
|
||||
#define DST_WATERMARK_HIGH_MSB 15
|
||||
#define DST_WATERMARK_HIGH_LSB 0
|
||||
#define DST_WATERMARK_HIGH_MASK 0x0000ffff
|
||||
#define DST_WATERMARK_HIGH_GET(x) \
|
||||
(((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB)
|
||||
#define DST_WATERMARK_HIGH_SET(x) \
|
||||
(((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
|
||||
#define DST_WATERMARK_HIGH_RESET 0
|
||||
#define DST_WATERMARK_ADDRESS 0x0050
|
||||
|
||||
static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
|
||||
{
|
||||
return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
|
||||
}
|
||||
|
||||
#define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \
|
||||
HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \
|
||||
HOST_IS_DST_RING_LOW_WATERMARK_MASK | \
|
||||
HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
|
||||
|
||||
#define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \
|
||||
MISC_IS_DST_ADDR_ERR_MASK | \
|
||||
MISC_IS_SRC_LEN_ERR_MASK | \
|
||||
MISC_IS_DST_MAX_LEN_VIO_MASK | \
|
||||
MISC_IS_DST_RING_OVERFLOW_MASK | \
|
||||
MISC_IS_SRC_RING_OVERFLOW_MASK)
|
||||
|
||||
#define CE_SRC_RING_TO_DESC(baddr, idx) \
|
||||
(&(((struct ce_desc *)baddr)[idx]))
|
||||
|
||||
|
||||
@ -2459,24 +2459,29 @@ struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
|
||||
case ATH10K_HW_QCA988X:
|
||||
case ATH10K_HW_QCA9887:
|
||||
ar->regs = &qca988x_regs;
|
||||
ar->hw_ce_regs = &qcax_ce_regs;
|
||||
ar->hw_values = &qca988x_values;
|
||||
break;
|
||||
case ATH10K_HW_QCA6174:
|
||||
case ATH10K_HW_QCA9377:
|
||||
ar->regs = &qca6174_regs;
|
||||
ar->hw_ce_regs = &qcax_ce_regs;
|
||||
ar->hw_values = &qca6174_values;
|
||||
break;
|
||||
case ATH10K_HW_QCA99X0:
|
||||
case ATH10K_HW_QCA9984:
|
||||
ar->regs = &qca99x0_regs;
|
||||
ar->hw_ce_regs = &qcax_ce_regs;
|
||||
ar->hw_values = &qca99x0_values;
|
||||
break;
|
||||
case ATH10K_HW_QCA9888:
|
||||
ar->regs = &qca99x0_regs;
|
||||
ar->hw_ce_regs = &qcax_ce_regs;
|
||||
ar->hw_values = &qca9888_values;
|
||||
break;
|
||||
case ATH10K_HW_QCA4019:
|
||||
ar->regs = &qca4019_regs;
|
||||
ar->hw_ce_regs = &qcax_ce_regs;
|
||||
ar->hw_values = &qca4019_values;
|
||||
break;
|
||||
default:
|
||||
|
||||
@ -794,6 +794,7 @@ struct ath10k {
|
||||
struct completion target_suspend;
|
||||
|
||||
const struct ath10k_hw_regs *regs;
|
||||
const struct ath10k_hw_ce_regs *hw_ce_regs;
|
||||
const struct ath10k_hw_values *hw_values;
|
||||
struct ath10k_bmi bmi;
|
||||
struct ath10k_wmi wmi;
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/bitops.h>
|
||||
#include "core.h"
|
||||
#include "hw.h"
|
||||
#include "hif.h"
|
||||
@ -191,6 +192,142 @@ const struct ath10k_hw_values qca4019_values = {
|
||||
.ce_desc_meta_data_lsb = 4,
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_regs_addr_map qcax_src_ring = {
|
||||
.msb = 0x00000010,
|
||||
.lsb = 0x00000010,
|
||||
.mask = GENMASK(16, 16),
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_regs_addr_map qcax_dst_ring = {
|
||||
.msb = 0x00000011,
|
||||
.lsb = 0x00000011,
|
||||
.mask = GENMASK(17, 17),
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_regs_addr_map qcax_dmax = {
|
||||
.msb = 0x0000000f,
|
||||
.lsb = 0x00000000,
|
||||
.mask = GENMASK(15, 0),
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_ctrl1 qcax_ctrl1 = {
|
||||
.addr = 0x00000010,
|
||||
.hw_mask = 0x0007ffff,
|
||||
.sw_mask = 0x0007ffff,
|
||||
.hw_wr_mask = 0x00000000,
|
||||
.sw_wr_mask = 0x0007ffff,
|
||||
.reset_mask = 0xffffffff,
|
||||
.reset = 0x00000080,
|
||||
.src_ring = &qcax_src_ring,
|
||||
.dst_ring = &qcax_dst_ring,
|
||||
.dmax = &qcax_dmax,
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_regs_addr_map qcax_cmd_halt_status = {
|
||||
.msb = 0x00000003,
|
||||
.lsb = 0x00000003,
|
||||
.mask = GENMASK(3, 3),
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_cmd_halt qcax_cmd_halt = {
|
||||
.msb = 0x00000000,
|
||||
.mask = GENMASK(0, 0),
|
||||
.status_reset = 0x00000000,
|
||||
.status = &qcax_cmd_halt_status,
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_regs_addr_map qcax_host_ie_cc = {
|
||||
.msb = 0x00000000,
|
||||
.lsb = 0x00000000,
|
||||
.mask = GENMASK(0, 0),
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_host_ie qcax_host_ie = {
|
||||
.copy_complete_reset = 0x00000000,
|
||||
.copy_complete = &qcax_host_ie_cc,
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_host_wm_regs qcax_wm_reg = {
|
||||
.dstr_lmask = 0x00000010,
|
||||
.dstr_hmask = 0x00000008,
|
||||
.srcr_lmask = 0x00000004,
|
||||
.srcr_hmask = 0x00000002,
|
||||
.cc_mask = 0x00000001,
|
||||
.wm_mask = 0x0000001E,
|
||||
.addr = 0x00000030,
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_misc_regs qcax_misc_reg = {
|
||||
.axi_err = 0x00000400,
|
||||
.dstr_add_err = 0x00000200,
|
||||
.srcr_len_err = 0x00000100,
|
||||
.dstr_mlen_vio = 0x00000080,
|
||||
.dstr_overflow = 0x00000040,
|
||||
.srcr_overflow = 0x00000020,
|
||||
.err_mask = 0x000007E0,
|
||||
.addr = 0x00000038,
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_low = {
|
||||
.msb = 0x0000001f,
|
||||
.lsb = 0x00000010,
|
||||
.mask = GENMASK(31, 16),
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_high = {
|
||||
.msb = 0x0000000f,
|
||||
.lsb = 0x00000000,
|
||||
.mask = GENMASK(15, 0),
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_src_ring = {
|
||||
.addr = 0x0000004c,
|
||||
.low_rst = 0x00000000,
|
||||
.high_rst = 0x00000000,
|
||||
.wm_low = &qcax_src_wm_low,
|
||||
.wm_high = &qcax_src_wm_high,
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_low = {
|
||||
.lsb = 0x00000010,
|
||||
.mask = GENMASK(31, 16),
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_high = {
|
||||
.msb = 0x0000000f,
|
||||
.lsb = 0x00000000,
|
||||
.mask = GENMASK(15, 0),
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_dst_ring = {
|
||||
.addr = 0x00000050,
|
||||
.low_rst = 0x00000000,
|
||||
.high_rst = 0x00000000,
|
||||
.wm_low = &qcax_dst_wm_low,
|
||||
.wm_high = &qcax_dst_wm_high,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs qcax_ce_regs = {
|
||||
.sr_base_addr = 0x00000000,
|
||||
.sr_size_addr = 0x00000004,
|
||||
.dr_base_addr = 0x00000008,
|
||||
.dr_size_addr = 0x0000000c,
|
||||
.ce_cmd_addr = 0x00000018,
|
||||
.misc_ie_addr = 0x00000034,
|
||||
.sr_wr_index_addr = 0x0000003c,
|
||||
.dst_wr_index_addr = 0x00000040,
|
||||
.current_srri_addr = 0x00000044,
|
||||
.current_drri_addr = 0x00000048,
|
||||
.host_ie_addr = 0x0000002c,
|
||||
.ctrl1_regs = &qcax_ctrl1,
|
||||
.cmd_halt = &qcax_cmd_halt,
|
||||
.host_ie = &qcax_host_ie,
|
||||
.wm_regs = &qcax_wm_reg,
|
||||
.misc_regs = &qcax_misc_reg,
|
||||
.wm_srcr = &qcax_wm_src_ring,
|
||||
.wm_dstr = &qcax_wm_dst_ring,
|
||||
};
|
||||
|
||||
const struct ath10k_hw_clk_params qca6174_clk[ATH10K_HW_REFCLK_COUNT] = {
|
||||
{
|
||||
.refclk = 48000000,
|
||||
|
||||
@ -268,6 +268,86 @@ extern const struct ath10k_hw_regs qca6174_regs;
|
||||
extern const struct ath10k_hw_regs qca99x0_regs;
|
||||
extern const struct ath10k_hw_regs qca4019_regs;
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map {
|
||||
u32 msb;
|
||||
u32 lsb;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_ctrl1 {
|
||||
u32 addr;
|
||||
u32 hw_mask;
|
||||
u32 sw_mask;
|
||||
u32 hw_wr_mask;
|
||||
u32 sw_wr_mask;
|
||||
u32 reset_mask;
|
||||
u32 reset;
|
||||
struct ath10k_hw_ce_regs_addr_map *src_ring;
|
||||
struct ath10k_hw_ce_regs_addr_map *dst_ring;
|
||||
struct ath10k_hw_ce_regs_addr_map *dmax; };
|
||||
|
||||
struct ath10k_hw_ce_cmd_halt {
|
||||
u32 status_reset;
|
||||
u32 msb;
|
||||
u32 mask;
|
||||
struct ath10k_hw_ce_regs_addr_map *status; };
|
||||
|
||||
struct ath10k_hw_ce_host_ie {
|
||||
u32 copy_complete_reset;
|
||||
struct ath10k_hw_ce_regs_addr_map *copy_complete; };
|
||||
|
||||
struct ath10k_hw_ce_host_wm_regs {
|
||||
u32 dstr_lmask;
|
||||
u32 dstr_hmask;
|
||||
u32 srcr_lmask;
|
||||
u32 srcr_hmask;
|
||||
u32 cc_mask;
|
||||
u32 wm_mask;
|
||||
u32 addr;
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_misc_regs {
|
||||
u32 axi_err;
|
||||
u32 dstr_add_err;
|
||||
u32 srcr_len_err;
|
||||
u32 dstr_mlen_vio;
|
||||
u32 dstr_overflow;
|
||||
u32 srcr_overflow;
|
||||
u32 err_mask;
|
||||
u32 addr;
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_dst_src_wm_regs {
|
||||
u32 addr;
|
||||
u32 low_rst;
|
||||
u32 high_rst;
|
||||
struct ath10k_hw_ce_regs_addr_map *wm_low;
|
||||
struct ath10k_hw_ce_regs_addr_map *wm_high; };
|
||||
|
||||
struct ath10k_hw_ce_regs {
|
||||
u32 sr_base_addr;
|
||||
u32 sr_size_addr;
|
||||
u32 dr_base_addr;
|
||||
u32 dr_size_addr;
|
||||
u32 ce_cmd_addr;
|
||||
u32 misc_ie_addr;
|
||||
u32 sr_wr_index_addr;
|
||||
u32 dst_wr_index_addr;
|
||||
u32 current_srri_addr;
|
||||
u32 current_drri_addr;
|
||||
u32 ddr_addr_for_rri_low;
|
||||
u32 ddr_addr_for_rri_high;
|
||||
u32 ce_rri_low;
|
||||
u32 ce_rri_high;
|
||||
u32 host_ie_addr;
|
||||
struct ath10k_hw_ce_host_wm_regs *wm_regs;
|
||||
struct ath10k_hw_ce_misc_regs *misc_regs;
|
||||
struct ath10k_hw_ce_ctrl1 *ctrl1_regs;
|
||||
struct ath10k_hw_ce_cmd_halt *cmd_halt;
|
||||
struct ath10k_hw_ce_host_ie *host_ie;
|
||||
struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr;
|
||||
struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr; };
|
||||
|
||||
struct ath10k_hw_values {
|
||||
u32 rtc_state_val_on;
|
||||
u8 ce_count;
|
||||
@ -282,6 +362,7 @@ extern const struct ath10k_hw_values qca6174_values;
|
||||
extern const struct ath10k_hw_values qca99x0_values;
|
||||
extern const struct ath10k_hw_values qca9888_values;
|
||||
extern const struct ath10k_hw_values qca4019_values;
|
||||
extern struct ath10k_hw_ce_regs qcax_ce_regs;
|
||||
|
||||
void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
|
||||
u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
|
||||
|
||||
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Reference in New Issue
Block a user