serial: imx: rename variables to match the register names
Now the variable holding the value of register USR1 is called usr1 instead of sts which is more straight forward. The same is also done for sts2 which is called usr2 now. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -758,27 +758,26 @@ static void imx_mctrl_check(struct imx_port *sport)
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static irqreturn_t imx_int(int irq, void *dev_id)
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static irqreturn_t imx_int(int irq, void *dev_id)
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{
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{
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struct imx_port *sport = dev_id;
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struct imx_port *sport = dev_id;
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unsigned int sts;
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unsigned int usr1, usr2;
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unsigned int sts2;
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irqreturn_t ret = IRQ_NONE;
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irqreturn_t ret = IRQ_NONE;
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sts = readl(sport->port.membase + USR1);
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usr1 = readl(sport->port.membase + USR1);
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sts2 = readl(sport->port.membase + USR2);
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usr2 = readl(sport->port.membase + USR2);
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if (!sport->dma_is_enabled && (sts & (USR1_RRDY | USR1_AGTIM))) {
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if (!sport->dma_is_enabled && (usr1 & (USR1_RRDY | USR1_AGTIM))) {
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imx_rxint(irq, dev_id);
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imx_rxint(irq, dev_id);
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ret = IRQ_HANDLED;
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ret = IRQ_HANDLED;
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}
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}
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if ((sts & USR1_TRDY &&
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if ((usr1 & USR1_TRDY &&
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readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
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readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
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(sts2 & USR2_TXDC &&
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(usr2 & USR2_TXDC &&
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readl(sport->port.membase + UCR4) & UCR4_TCEN)) {
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readl(sport->port.membase + UCR4) & UCR4_TCEN)) {
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imx_txint(irq, dev_id);
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imx_txint(irq, dev_id);
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ret = IRQ_HANDLED;
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ret = IRQ_HANDLED;
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}
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}
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if (sts & USR1_DTRD) {
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if (usr1 & USR1_DTRD) {
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unsigned long flags;
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unsigned long flags;
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writel(USR1_DTRD, sport->port.membase + USR1);
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writel(USR1_DTRD, sport->port.membase + USR1);
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@ -790,17 +789,17 @@ static irqreturn_t imx_int(int irq, void *dev_id)
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ret = IRQ_HANDLED;
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ret = IRQ_HANDLED;
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}
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}
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if (sts & USR1_RTSD) {
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if (usr1 & USR1_RTSD) {
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imx_rtsint(irq, dev_id);
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imx_rtsint(irq, dev_id);
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ret = IRQ_HANDLED;
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ret = IRQ_HANDLED;
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}
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}
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if (sts & USR1_AWAKE) {
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if (usr1 & USR1_AWAKE) {
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writel(USR1_AWAKE, sport->port.membase + USR1);
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writel(USR1_AWAKE, sport->port.membase + USR1);
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ret = IRQ_HANDLED;
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ret = IRQ_HANDLED;
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}
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}
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if (sts2 & USR2_ORE) {
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if (usr2 & USR2_ORE) {
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sport->port.icount.overrun++;
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sport->port.icount.overrun++;
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writel(USR2_ORE, sport->port.membase + USR2);
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writel(USR2_ORE, sport->port.membase + USR2);
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ret = IRQ_HANDLED;
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ret = IRQ_HANDLED;
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