greybus: gpio: add interrupt handling support
Adds gpio interrupt handling support using an irqchip/irqdomain instantiation inside the GB GPIO driver. This implementation works on older kernels such as 3.10 that do not have the gpiolib irqchip helpers. Any line on a Greybus gpiochip may be configured as an interrupt. Once configured, IRQ event messages received from a module fire off the registered interrupt handler. Signed-off-by: Matt Porter <mporter@linaro.org> Signed-off-by: Greg Kroah-Hartman <greg@kroah.com>
This commit is contained in:
Matt Porter
Greg Kroah-Hartman
parent
48d7077c00
commit
036aad9d02
@ -11,6 +11,8 @@
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include "greybus.h"
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struct gb_gpio_line {
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@ -30,9 +32,16 @@ struct gb_gpio_controller {
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struct gb_gpio_line *lines;
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struct gpio_chip chip;
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struct irq_chip irqc;
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struct irq_chip *irqchip;
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struct irq_domain *irqdomain;
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unsigned int irq_base;
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irq_flow_handler_t irq_handler;
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unsigned int irq_default_type;
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};
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#define gpio_chip_to_gb_gpio_controller(chip) \
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container_of(chip, struct gb_gpio_controller, chip)
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#define irq_data_to_gpio_chip(d) (d->domain->host_data)
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/* Version of the Greybus GPIO protocol we support */
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#define GB_GPIO_VERSION_MAJOR 0x00
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@ -50,6 +59,11 @@ struct gb_gpio_controller {
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#define GB_GPIO_TYPE_GET_VALUE 0x08
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#define GB_GPIO_TYPE_SET_VALUE 0x09
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#define GB_GPIO_TYPE_SET_DEBOUNCE 0x0a
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#define GB_GPIO_TYPE_IRQ_TYPE 0x0b
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#define GB_GPIO_TYPE_IRQ_ACK 0x0c
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#define GB_GPIO_TYPE_IRQ_MASK 0x0d
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#define GB_GPIO_TYPE_IRQ_UNMASK 0x0e
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#define GB_GPIO_TYPE_IRQ_EVENT 0x0f
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#define GB_GPIO_TYPE_RESPONSE 0x80 /* OR'd with rest */
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#define GB_GPIO_DEBOUNCE_USEC_DEFAULT 0 /* microseconds */
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@ -106,6 +120,32 @@ struct gb_gpio_set_debounce_request {
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};
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/* debounce response has no payload */
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struct gb_gpio_irq_type_request {
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__u8 which;
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__u8 type;
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};
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/* irq type response has no payload */
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struct gb_gpio_irq_mask_request {
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__u8 which;
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};
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/* irq mask response has no payload */
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struct gb_gpio_irq_unmask_request {
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__u8 which;
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};
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/* irq unmask response has no payload */
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struct gb_gpio_irq_ack_request {
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__u8 which;
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};
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/* irq ack response has no payload */
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/* irq event requests originate on another module and are handled on the AP */
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struct gb_gpio_irq_event_request {
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__u8 which;
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};
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/* irq event response has no payload */
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/* Define get_version() routine */
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define_get_version(gb_gpio_controller, GPIO);
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@ -280,6 +320,120 @@ static int gb_gpio_set_debounce_operation(struct gb_gpio_controller *ggc,
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return ret;
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}
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static void gb_gpio_ack_irq(struct irq_data *d)
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{
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struct gpio_chip *chip = irq_data_to_gpio_chip(d);
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struct gb_gpio_controller *ggc = gpio_chip_to_gb_gpio_controller(chip);
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struct gb_gpio_irq_ack_request request;
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int ret;
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request.which = d->hwirq;
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ret = gb_operation_sync(ggc->connection,
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GB_GPIO_TYPE_IRQ_ACK,
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&request, sizeof(request), NULL, 0);
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if (ret)
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pr_err("irq ack operation failed (%d)\n", ret);
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}
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static void gb_gpio_mask_irq(struct irq_data *d)
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{
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struct gpio_chip *chip = irq_data_to_gpio_chip(d);
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struct gb_gpio_controller *ggc = gpio_chip_to_gb_gpio_controller(chip);
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struct gb_gpio_irq_mask_request request;
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int ret;
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request.which = d->hwirq;
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ret = gb_operation_sync(ggc->connection,
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GB_GPIO_TYPE_IRQ_MASK,
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&request, sizeof(request), NULL, 0);
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if (ret)
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pr_err("irq mask operation failed (%d)\n", ret);
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}
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static void gb_gpio_unmask_irq(struct irq_data *d)
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{
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struct gpio_chip *chip = irq_data_to_gpio_chip(d);
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struct gb_gpio_controller *ggc = gpio_chip_to_gb_gpio_controller(chip);
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struct gb_gpio_irq_unmask_request request;
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int ret;
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request.which = d->hwirq;
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ret = gb_operation_sync(ggc->connection,
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GB_GPIO_TYPE_IRQ_UNMASK,
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&request, sizeof(request), NULL, 0);
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if (ret)
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pr_err("irq unmask operation failed (%d)\n", ret);
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}
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static int gb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *chip = irq_data_to_gpio_chip(d);
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struct gb_gpio_controller *ggc = gpio_chip_to_gb_gpio_controller(chip);
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struct gb_gpio_irq_type_request request;
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int ret = 0;
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request.which = d->hwirq;
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request.type = type;
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switch (type) {
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case IRQ_TYPE_NONE:
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break;
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_EDGE_BOTH:
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case IRQ_TYPE_LEVEL_LOW:
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case IRQ_TYPE_LEVEL_HIGH:
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ret = gb_operation_sync(ggc->connection,
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GB_GPIO_TYPE_IRQ_TYPE,
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&request, sizeof(request), NULL, 0);
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if (ret)
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pr_err("irq type operation failed (%d)\n", ret);
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break;
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default:
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pr_err("No such irq type %d", type);
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ret = -EINVAL;
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}
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return ret;
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}
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static void gb_gpio_request_recv(u8 type, struct gb_operation *op)
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{
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struct gb_gpio_controller *ggc;
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struct gb_connection *connection;
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struct gb_message *request;
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struct gb_gpio_irq_event_request *event;
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int irq;
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struct irq_desc *desc;
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int ret;
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if (type != GB_GPIO_TYPE_IRQ_EVENT) {
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pr_err("unsupported unsolicited request\n");
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return;
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}
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connection = op->connection;
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ggc = connection->private;
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request = op->request;
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event = request->payload;
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if (event->which > ggc->line_max) {
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pr_err("Unsupported hw irq %d\n", event->which);
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return;
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}
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irq = gpio_to_irq(ggc->irq_base + event->which);
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desc = irq_to_desc(irq);
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/* Dispatch interrupt */
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local_irq_disable();
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handle_simple_irq(irq, desc);
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local_irq_enable();
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ret = gb_operation_response_send(op, 0);
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if (ret)
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pr_err("error %d sending response status %d\n", ret, 0);
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}
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static int gb_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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struct gb_gpio_controller *gb_gpio_controller = gpio_chip_to_gb_gpio_controller(chip);
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@ -399,14 +553,6 @@ static int gb_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
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return 0; /* XXX */
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}
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static int gb_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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if (offset >= chip->ngpio)
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return -EINVAL;
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return 0; /* XXX */
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}
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static void gb_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
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{
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return; /* XXX */
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@ -436,10 +582,148 @@ static int gb_gpio_controller_setup(struct gb_gpio_controller *gb_gpio_controlle
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return ret;
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}
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/**
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* gb_gpio_irq_map() - maps an IRQ into a GB gpio irqchip
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* @d: the irqdomain used by this irqchip
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* @irq: the global irq number used by this GB gpio irqchip irq
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* @hwirq: the local IRQ/GPIO line offset on this GB gpio
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*
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* This function will set up the mapping for a certain IRQ line on a
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* GB gpio by assigning the GB gpio as chip data, and using the irqchip
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* stored inside the GB gpio.
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*/
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static int gb_gpio_irq_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct gpio_chip *chip = domain->host_data;
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struct gb_gpio_controller *ggc = gpio_chip_to_gb_gpio_controller(chip);
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irq_set_chip_data(irq, ggc);
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irq_set_chip_and_handler(irq, ggc->irqchip, ggc->irq_handler);
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#ifdef CONFIG_ARM
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set_irq_flags(irq, IRQF_VALID);
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#else
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irq_set_noprobe(irq);
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#endif
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/*
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* No set-up of the hardware will happen if IRQ_TYPE_NONE
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* is passed as default type.
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*/
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if (ggc->irq_default_type != IRQ_TYPE_NONE)
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irq_set_irq_type(irq, ggc->irq_default_type);
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return 0;
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}
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static void gb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
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{
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#ifdef CONFIG_ARM
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set_irq_flags(irq, 0);
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#endif
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irq_set_chip_and_handler(irq, NULL, NULL);
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irq_set_chip_data(irq, NULL);
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}
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static const struct irq_domain_ops gb_gpio_domain_ops = {
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.map = gb_gpio_irq_map,
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.unmap = gb_gpio_irq_unmap,
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};
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/**
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* gb_gpio_irqchip_remove() - removes an irqchip added to a gb_gpio_controller
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* @ggc: the gb_gpio_controller to remove the irqchip from
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*
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* This is called only from gb_gpio_remove()
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*/
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static void gb_gpio_irqchip_remove(struct gb_gpio_controller *ggc)
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{
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unsigned int offset;
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/* Remove all IRQ mappings and delete the domain */
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if (ggc->irqdomain) {
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for (offset = 0; offset < (ggc->line_max + 1); offset++)
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irq_dispose_mapping(irq_find_mapping(ggc->irqdomain, offset));
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irq_domain_remove(ggc->irqdomain);
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}
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if (ggc->irqchip) {
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ggc->irqchip = NULL;
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}
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}
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/**
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* gb_gpio_irqchip_add() - adds an irqchip to a gpio chip
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* @chip: the gpio chip to add the irqchip to
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* @irqchip: the irqchip to add to the adapter
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* @first_irq: if not dynamically assigned, the base (first) IRQ to
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* allocate gpio irqs from
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* @handler: the irq handler to use (often a predefined irq core function)
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* @type: the default type for IRQs on this irqchip, pass IRQ_TYPE_NONE
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* to have the core avoid setting up any default type in the hardware.
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*
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* This function closely associates a certain irqchip with a certain
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* gpio chip, providing an irq domain to translate the local IRQs to
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* global irqs, and making sure that the gpio chip
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* is passed as chip data to all related functions. Driver callbacks
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* need to use container_of() to get their local state containers back
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* from the gpio chip passed as chip data. An irqdomain will be stored
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* in the gpio chip that shall be used by the driver to handle IRQ number
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* translation. The gpio chip will need to be initialized and registered
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* before calling this function.
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*/
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static int gb_gpio_irqchip_add(struct gpio_chip *chip,
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struct irq_chip *irqchip,
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unsigned int first_irq,
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irq_flow_handler_t handler,
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unsigned int type)
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{
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struct gb_gpio_controller *ggc;
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unsigned int offset;
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unsigned irq_base;
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if (!chip || !irqchip)
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return -EINVAL;
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ggc = gpio_chip_to_gb_gpio_controller(chip);
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ggc->irqchip = irqchip;
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ggc->irq_handler = handler;
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ggc->irq_default_type = type;
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ggc->irqdomain = irq_domain_add_simple(NULL,
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ggc->line_max + 1, first_irq,
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&gb_gpio_domain_ops, chip);
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if (!ggc->irqdomain) {
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ggc->irqchip = NULL;
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return -EINVAL;
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}
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/*
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* Prepare the mapping since the irqchip shall be orthogonal to
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* any gpio calls. If the first_irq was zero, this is
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* necessary to allocate descriptors for all IRQs.
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*/
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for (offset = 0; offset < (ggc->line_max + 1); offset++) {
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irq_base = irq_create_mapping(ggc->irqdomain, offset);
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if (offset == 0)
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ggc->irq_base = irq_base;
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}
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return 0;
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}
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static int gb_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct gb_gpio_controller *ggc = gpio_chip_to_gb_gpio_controller(chip);
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return irq_find_mapping(ggc->irqdomain, offset);
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}
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static int gb_gpio_connection_init(struct gb_connection *connection)
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{
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struct gb_gpio_controller *gb_gpio_controller;
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struct gpio_chip *gpio;
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struct irq_chip *irqc;
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int ret;
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gb_gpio_controller = kzalloc(sizeof(*gb_gpio_controller), GFP_KERNEL);
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@ -452,9 +736,17 @@ static int gb_gpio_connection_init(struct gb_connection *connection)
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if (ret)
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goto out_err;
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irqc = &gb_gpio_controller->irqc;
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irqc->irq_ack = gb_gpio_ack_irq;
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irqc->irq_mask = gb_gpio_mask_irq;
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irqc->irq_unmask = gb_gpio_unmask_irq;
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irqc->irq_set_type = gb_gpio_irq_set_type;
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irqc->name = "greybus_gpio";
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gpio = &gb_gpio_controller->chip;
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gpio->label = "greybus_gpio";
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gpio->dev = &connection->dev;
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gpio->owner = THIS_MODULE; /* XXX Module get? */
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gpio->request = gb_gpio_request;
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@ -465,9 +757,8 @@ static int gb_gpio_connection_init(struct gb_connection *connection)
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gpio->get = gb_gpio_get;
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gpio->set = gb_gpio_set;
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gpio->set_debounce = gb_gpio_set_debounce;
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gpio->to_irq = gb_gpio_to_irq;
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gpio->dbg_show = gb_gpio_dbg_show;
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gpio->to_irq = gb_gpio_to_irq;
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gpio->base = -1; /* Allocate base dynamically */
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gpio->ngpio = gb_gpio_controller->line_max + 1;
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gpio->can_sleep = true; /* XXX */
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@ -475,10 +766,20 @@ static int gb_gpio_connection_init(struct gb_connection *connection)
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ret = gpiochip_add(gpio);
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if (ret) {
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pr_err("Failed to register GPIO\n");
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return ret;
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goto out_err;
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}
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ret = gb_gpio_irqchip_add(gpio, irqc, 0,
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handle_simple_irq, IRQ_TYPE_NONE);
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if (ret) {
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pr_err("Couldn't add irqchip to Greybus GPIO controller %d\n", ret);
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goto irqchip_err;
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}
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return 0;
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irqchip_err:
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gb_gpiochip_remove(gpio);
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out_err:
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kfree(gb_gpio_controller);
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return ret;
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@ -491,6 +792,7 @@ static void gb_gpio_connection_exit(struct gb_connection *connection)
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if (!gb_gpio_controller)
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return;
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gb_gpio_irqchip_remove(gb_gpio_controller);
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gb_gpiochip_remove(&gb_gpio_controller->chip);
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/* kref_put(gb_gpio_controller->connection) */
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kfree(gb_gpio_controller);
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@ -503,7 +805,7 @@ static struct gb_protocol gpio_protocol = {
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.minor = 1,
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.connection_init = gb_gpio_connection_init,
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.connection_exit = gb_gpio_connection_exit,
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.request_recv = NULL, /* no incoming requests */
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.request_recv = gb_gpio_request_recv,
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};
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int gb_gpio_protocol_init(void)
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