forked from Minki/linux
drm/amd/powerplay: add power profile support for Polaris
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1613,6 +1613,42 @@ static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
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}
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static void polaris10_save_default_power_profile(struct pp_hwmgr *hwmgr)
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{
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struct polaris10_smumgr *data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
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struct SMU74_Discrete_GraphicsLevel *levels =
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data->smc_state_table.GraphicsLevel;
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unsigned min_level = 1;
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hwmgr->default_gfx_power_profile.activity_threshold =
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be16_to_cpu(levels[0].ActivityLevel);
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hwmgr->default_gfx_power_profile.up_hyst = levels[0].UpHyst;
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hwmgr->default_gfx_power_profile.down_hyst = levels[0].DownHyst;
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hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
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hwmgr->default_compute_power_profile = hwmgr->default_gfx_power_profile;
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hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
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/* Workaround compute SDMA instability: disable lowest SCLK
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* DPM level. Optimize compute power profile: Use only highest
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* 2 power levels (if more than 2 are available), Hysteresis:
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* 0ms up, 5ms down
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*/
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if (data->smc_state_table.GraphicsDpmLevelCount > 2)
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min_level = data->smc_state_table.GraphicsDpmLevelCount - 2;
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else if (data->smc_state_table.GraphicsDpmLevelCount == 2)
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min_level = 1;
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else
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min_level = 0;
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hwmgr->default_compute_power_profile.min_sclk =
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be32_to_cpu(levels[min_level].SclkSetting.SclkFrequency);
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hwmgr->default_compute_power_profile.up_hyst = 0;
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hwmgr->default_compute_power_profile.down_hyst = 5;
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hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
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hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
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}
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/**
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* Initializes the SMC table and uploads it
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*
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@ -1832,6 +1868,9 @@ int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
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result = polaris10_populate_pm_fuses(hwmgr);
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PP_ASSERT_WITH_CODE(0 == result,
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"Failed to populate PM fuses to SMC memory!", return result);
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polaris10_save_default_power_profile(hwmgr);
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return 0;
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}
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@ -2298,3 +2337,28 @@ bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
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CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
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? true : false;
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}
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int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
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struct amd_pp_profile *request)
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{
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struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
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(hwmgr->smumgr->backend);
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struct SMU74_Discrete_GraphicsLevel *levels =
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smu_data->smc_state_table.GraphicsLevel;
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uint32_t array = smu_data->smu7_data.dpm_table_start +
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offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
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uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
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SMU74_MAX_LEVELS_GRAPHICS;
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uint32_t i;
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for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
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levels[i].ActivityLevel =
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cpu_to_be16(request->activity_threshold);
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levels[i].EnabledForActivity = 1;
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levels[i].UpHyst = request->up_hyst;
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levels[i].DownHyst = request->down_hyst;
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}
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return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
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array_size, SMC_RAM_END);
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}
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@ -37,6 +37,8 @@ uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member);
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uint32_t polaris10_get_mac_definition(uint32_t value);
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int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr);
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bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr);
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int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
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struct amd_pp_profile *request);
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#endif
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@ -409,4 +409,5 @@ const struct pp_smumgr_func polaris10_smu_funcs = {
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.populate_all_memory_levels = polaris10_populate_all_memory_levels,
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.get_mac_definition = polaris10_get_mac_definition,
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.is_dpm_running = polaris10_is_dpm_running,
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.populate_requested_graphic_levels = polaris10_populate_requested_graphic_levels,
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};
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