leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

arm64: dts: qcom: msm8996: clean up PCIe PHY node

Browse Source 
Clean up the PCIe PHY node by renaming the wrapper node and grouping the
child node properties.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220705114032.22787-15-johan+linaro@kernel.org
This commit is contained in:
Johan Hovold 2022-07-05 13:40:32 +02:00 committed by Bjorn Andersson
parent 3a5da59af3
commit 02d99d4cfe
1 changed files with 17 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -588,7 +588,7 @@
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
pcie_phy: phy@34000 {
pcie_phy: phy-wrapper@34000 {
compatible = "qcom,msm8996-qmp-pcie-phy";
reg = <0x00034000 0x488>;
#address-cells = <1>;
@ -604,48 +604,55 @@
<&gcc GCC_PCIE_PHY_COM_BCR>,
<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
reset-names = "phy", "common", "cfg";
status = "disabled";
pciephy_0: phy@1000 {
reg = <0x1000 0x130>,
<0x1200 0x200>,
<0x1400 0x1dc>;
#phy-cells = <0>;
#clock-cells = <0>;
clock-output-names = "pcie_0_pipe_clk_src";
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "lane0";
#clock-cells = <0>;
clock-output-names = "pcie_0_pipe_clk_src";
#phy-cells = <0>;
};
pciephy_1: phy@2000 {
reg = <0x2000 0x130>,
<0x2200 0x200>,
<0x2400 0x1dc>;
#phy-cells = <0>;
#clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk_src";
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "pipe1";
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "lane1";
#clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk_src";
#phy-cells = <0>;
};
pciephy_2: phy@3000 {
reg = <0x3000 0x130>,
<0x3200 0x200>,
<0x3400 0x1dc>;
#phy-cells = <0>;
#clock-cells = <0>;
clock-output-names = "pcie_2_pipe_clk_src";
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
clock-names = "pipe2";
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
reset-names = "lane2";
#clock-cells = <0>;
clock-output-names = "pcie_2_pipe_clk_src";
#phy-cells = <0>;
};
};