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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

Browse Source 
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] User stack pointer randomisation
  [MIPS] Remove unused include/asm-mips/gfx.h
  [MIPS] Remove unused include/asm-mips/ds1216.h
  [MIPS] Workaround for RM7000 WAIT instruction aka erratum 38
  [MIPS] Make support for weakly ordered LL/SC a config option.
  [MIPS] Disable UserLocal runtime detection on platforms which never have it.
  [MIPS] Disable MT runtime detection on platforms which never support MT.
This commit is contained in:
Linus Torvalds 2007-07-20 12:01:59 -07:00
commit 02d6112cd7
20 changed files with 125 additions and 134 deletions
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11
arch/mips/Kconfig
View File

@ -1190,8 +1190,19 @@ config SYS_HAS_CPU_RM9000
config SYS_HAS_CPU_SB1
bool
#
# CPU may reorder R->R, R->W, W->R, W->W
# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
#
config WEAK_ORDERING
bool
#
# CPU may reorder reads and writes beyond LL/SC
# CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
#
config WEAK_REORDERING_BEYOND_LLSC
bool
endmenu
#

26
arch/mips/kernel/cpu-probe.c
View File

@ -75,6 +75,27 @@ static void r4k_wait_irqoff(void)
local_irq_enable();
}
/*
* The RM7000 variant has to handle erratum 38. The workaround is to not
* have any pending stores when the WAIT instruction is executed.
*/
static void rm7k_wait_irqoff(void)
{
local_irq_disable();
if (!need_resched())
__asm__(
" .set push \n"
" .set mips3 \n"
" .set noat \n"
" mfc0 $1, $12 \n"
" sync \n"
" mtc0 $1, $12 # stalls until W stage \n"
" wait \n"
" mtc0 $1, $12 # stalls until W stage \n"
" .set pop \n");
local_irq_enable();
}
/* The Au1xxx wait is available only if using 32khz counter or
* external timer source, but specifically not CP0 Counter. */
int allow_au1k_wait;
@ -132,7 +153,6 @@ static inline void check_wait(void)
case CPU_R4700:
case CPU_R5000:
case CPU_NEVADA:
case CPU_RM7000:
case CPU_4KC:
case CPU_4KEC:
case CPU_4KSC:
@ -142,6 +162,10 @@ static inline void check_wait(void)
cpu_wait = r4k_wait;
break;
case CPU_RM7000:
cpu_wait = rm7k_wait_irqoff;
break;
case CPU_24K:
case CPU_34K:
cpu_wait = r4k_wait;

14
arch/mips/kernel/process.c
View File

@ -25,7 +25,9 @@
#include <linux/init.h>
#include <linux/completion.h>
#include <linux/kallsyms.h>
#include <linux/random.h>
#include <asm/asm.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/dsp.h>
@ -460,3 +462,15 @@ unsigned long get_wchan(struct task_struct *task)
out:
return pc;
}
/*
* Don't forget that the stack pointer must be aligned on a 8 bytes
* boundary for 32-bits ABI and 16 bytes for 64-bits ABI.
*/
unsigned long arch_align_stack(unsigned long sp)
{
if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
sp -= get_random_int() & ~PAGE_MASK;
return sp & ALMASK;
}

33
include/asm-mips/atomic.h
View File

@ -138,7 +138,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
{
unsigned long result;
smp_mb();
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
@ -181,7 +181,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
raw_local_irq_restore(flags);
}
smp_mb();
smp_llsc_mb();
return result;
}
@ -190,7 +190,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
{
unsigned long result;
smp_mb();
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
@ -233,7 +233,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
raw_local_irq_restore(flags);
}
smp_mb();
smp_llsc_mb();
return result;
}
@ -250,7 +250,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
{
unsigned long result;
smp_mb();
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
@ -302,7 +302,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
raw_local_irq_restore(flags);
}
smp_mb();
smp_llsc_mb();
return result;
}
@ -519,7 +519,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
{
unsigned long result;
smp_mb();
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
@ -562,7 +562,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
raw_local_irq_restore(flags);
}
smp_mb();
smp_llsc_mb();
return result;
}
@ -571,7 +571,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
{
unsigned long result;
smp_mb();
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
@ -614,7 +614,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
raw_local_irq_restore(flags);
}
smp_mb();
smp_llsc_mb();
return result;
}
@ -631,7 +631,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
{
unsigned long result;
smp_mb();
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
@ -683,7 +683,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
raw_local_irq_restore(flags);
}
smp_mb();
smp_llsc_mb();
return result;
}
@ -791,10 +791,11 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
* atomic*_return operations are serializing but not the non-*_return
* versions.
*/
#define smp_mb__before_atomic_dec() smp_mb()
#define smp_mb__after_atomic_dec() smp_mb()
#define smp_mb__before_atomic_inc() smp_mb()
#define smp_mb__after_atomic_inc() smp_mb()
#define smp_mb__before_atomic_dec() smp_llsc_mb()
#define smp_mb__after_atomic_dec() smp_llsc_mb()
#define smp_mb__before_atomic_inc() smp_llsc_mb()
#define smp_mb__after_atomic_inc() smp_llsc_mb()
#include <asm-generic/atomic.h>
#endif /* _ASM_ATOMIC_H */

9
include/asm-mips/barrier.h
View File

@ -121,6 +121,11 @@
#else
#define __WEAK_ORDERING_MB " \n"
#endif
#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
#define __WEAK_LLSC_MB " sync \n"
#else
#define __WEAK_LLSC_MB " \n"
#endif
#define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
#define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
@ -129,4 +134,8 @@
#define set_mb(var, value) \
do { var = value; smp_mb(); } while (0)
#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
#define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
#define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
#endif /* __ASM_BARRIER_H */

10
include/asm-mips/bitops.h
View File

@ -38,8 +38,8 @@
/*
* clear_bit() doesn't provide any barrier for the compiler.
*/
#define smp_mb__before_clear_bit() smp_mb()
#define smp_mb__after_clear_bit() smp_mb()
#define smp_mb__before_clear_bit() smp_llsc_mb()
#define smp_mb__after_clear_bit() smp_llsc_mb()
/*
* set_bit - Atomically set a bit in memory
@ -289,7 +289,7 @@ static inline int test_and_set_bit(unsigned long nr,
raw_local_irq_restore(flags);
}
smp_mb();
smp_llsc_mb();
return res != 0;
}
@ -377,7 +377,7 @@ static inline int test_and_clear_bit(unsigned long nr,
raw_local_irq_restore(flags);
}
smp_mb();
smp_llsc_mb();
return res != 0;
}
@ -445,7 +445,7 @@ static inline int test_and_change_bit(unsigned long nr,
raw_local_irq_restore(flags);
}
smp_mb();
smp_llsc_mb();
return res != 0;
}

31
include/asm-mips/ds1216.h
View File

@ -1,31 +0,0 @@
#ifndef _DS1216_H
#define _DS1216_H
extern volatile unsigned char *ds1216_base;
unsigned long ds1216_get_cmos_time(void);
int ds1216_set_rtc_mmss(unsigned long nowtime);
#define DS1216_SEC_BYTE 1
#define DS1216_MIN_BYTE 2
#define DS1216_HOUR_BYTE 3
#define DS1216_HOUR_MASK (0x1f)
#define DS1216_AMPM_MASK (1<<5)
#define DS1216_1224_MASK (1<<7)
#define DS1216_DAY_BYTE 4
#define DS1216_DAY_MASK (0x7)
#define DS1216_DATE_BYTE 5
#define DS1216_DATE_MASK (0x3f)
#define DS1216_MONTH_BYTE 6
#define DS1216_MONTH_MASK (0x1f)
#define DS1216_YEAR_BYTE 7
#define DS1216_SEC(buf) (buf[DS1216_SEC_BYTE])
#define DS1216_MIN(buf) (buf[DS1216_MIN_BYTE])
#define DS1216_HOUR(buf) (buf[DS1216_HOUR_BYTE] & DS1216_HOUR_MASK)
#define DS1216_AMPM(buf) (buf[DS1216_HOUR_BYTE] & DS1216_AMPM_MASK)
#define DS1216_1224(buf) (buf[DS1216_HOUR_BYTE] & DS1216_1224_MASK)
#define DS1216_DATE(buf) (buf[DS1216_DATE_BYTE] & DS1216_DATE_MASK)
#define DS1216_MONTH(buf) (buf[DS1216_MONTH_BYTE] & DS1216_MONTH_MASK)
#define DS1216_YEAR(buf) (buf[DS1216_YEAR_BYTE])
#endif

8
include/asm-mips/futex.h
View File

@ -29,7 +29,7 @@
" .set mips3 \n" \
"2: sc $1, %2 \n" \
" beqzl $1, 1b \n" \
__WEAK_ORDERING_MB \
__WEAK_LLSC_MB \
"3: \n" \
" .set pop \n" \
" .set mips0 \n" \
@ -55,7 +55,7 @@
" .set mips3 \n" \
"2: sc $1, %2 \n" \
" beqz $1, 1b \n" \
__WEAK_ORDERING_MB \
__WEAK_LLSC_MB \
"3: \n" \
" .set pop \n" \
" .set mips0 \n" \
@ -152,7 +152,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
" .set mips3 \n"
"2: sc $1, %1 \n"
" beqzl $1, 1b \n"
__WEAK_ORDERING_MB
__WEAK_LLSC_MB
"3: \n"
" .set pop \n"
" .section .fixup,\"ax\" \n"
@ -179,7 +179,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
" .set mips3 \n"
"2: sc $1, %1 \n"
" beqz $1, 1b \n"
__WEAK_ORDERING_MB
__WEAK_LLSC_MB
"3: \n"
" .set pop \n"
" .section .fixup,\"ax\" \n"

55
include/asm-mips/gfx.h
View File

@ -1,55 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* This is the user-visible SGI GFX interface.
*
* This must be used verbatim into the GNU libc. It does not include
* any kernel-only bits on it.
*
* miguel@nuclecu.unam.mx
*/
#ifndef _ASM_GFX_H
#define _ASM_GFX_H
/* The iocls, yes, they do not make sense, but such is life */
#define GFX_BASE 100
#define GFX_GETNUM_BOARDS (GFX_BASE + 1)
#define GFX_GETBOARD_INFO (GFX_BASE + 2)
#define GFX_ATTACH_BOARD (GFX_BASE + 3)
#define GFX_DETACH_BOARD (GFX_BASE + 4)
#define GFX_IS_MANAGED (GFX_BASE + 5)
#define GFX_MAPALL (GFX_BASE + 10)
#define GFX_LABEL (GFX_BASE + 11)
#define GFX_INFO_NAME_SIZE 16
#define GFX_INFO_LABEL_SIZE 16
struct gfx_info {
char name [GFX_INFO_NAME_SIZE]; /* board name */
char label [GFX_INFO_LABEL_SIZE]; /* label name */
unsigned short int xpmax, ypmax; /* screen resolution */
unsigned int lenght; /* size of a complete gfx_info for this board */
};
struct gfx_getboardinfo_args {
unsigned int board; /* board number. starting from zero */
void *buf; /* pointer to gfx_info */
unsigned int len; /* buffer size of buf */
};
struct gfx_attach_board_args {
unsigned int board; /* board number, starting from zero */
void *vaddr; /* address where the board registers should be mapped */
};
#ifdef __KERNEL__
/* umap.c */
extern void remove_mapping (struct vm_area_struct *vma, struct task_struct *, unsigned long, unsigned long);
extern void *vmalloc_uncached (unsigned long size);
extern int vmap_page_range (struct vm_area_struct *vma, unsigned long from, unsigned long size, unsigned long vaddr);
#endif
#endif /* _ASM_GFX_H */

4
include/asm-mips/mach-cobalt/cpu-feature-overrides.h
View File

@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
#define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
@ -46,6 +46,8 @@
#define cpu_has_ic_fills_f_dc 0
#define cpu_icache_snoops_remote_store 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0

3
include/asm-mips/mach-excite/cpu-feature-overrides.h
View File

@ -4,6 +4,7 @@
* for more details.
*
* Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
@ -27,6 +28,8 @@
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_icache_snoops_remote_store 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1

4
include/asm-mips/mach-ip22/cpu-feature-overrides.h
View File

@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 Ralf Baechle
* Copyright (C) 2003, 07 Ralf Baechle
*/
#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
@ -30,6 +30,8 @@
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1

4
include/asm-mips/mach-ip27/cpu-feature-overrides.h
View File

@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 Ralf Baechle
* Copyright (C) 2003, 07 Ralf Baechle
*/
#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
@ -27,6 +27,8 @@
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_icache_snoops_remote_store 1
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1

4
include/asm-mips/mach-ip32/cpu-feature-overrides.h
View File

@ -4,7 +4,7 @@
* for more details.
*
* Copyright (C) 2005 Ilya A. Volynets-Evenbakh
* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2005, 07 Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
@ -38,6 +38,8 @@
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_has_4k_cache 1
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_mips32r1 0

3
include/asm-mips/mach-qemu/cpu-feature-overrides.h
View File

@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 Ralf Baechle
* Copyright (C) 2003, 07 Ralf Baechle
*/
#ifndef __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H
@ -24,6 +24,7 @@
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 0

4
include/asm-mips/mach-rm/cpu-feature-overrides.h
View File

@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
*
* SNI RM200 C apparently was only shipped with R4600 V2.0 and R5000 processors.
*/
@ -32,6 +32,8 @@
#define cpu_has_dsp 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0

4
include/asm-mips/mach-sibyte/cpu-feature-overrides.h
View File

@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
@ -26,6 +26,8 @@
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_icache_snoops_remote_store 0
#define cpu_has_nofpuex 0

4
include/asm-mips/mach-yosemite/cpu-feature-overrides.h
View File

@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
@ -26,6 +26,8 @@
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_icache_snoops_remote_store 0
#define cpu_has_nofpuex 0

18
include/asm-mips/spinlock.h
View File

@ -67,7 +67,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
: "memory");
}
smp_mb();
smp_llsc_mb();
}
static inline void __raw_spin_unlock(raw_spinlock_t *lock)
@ -118,7 +118,7 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
: "memory");
}
smp_mb();
smp_llsc_mb();
return res == 0;
}
@ -183,7 +183,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
: "memory");
}
smp_mb();
smp_llsc_mb();
}
/* Note the use of sub, not subu which will make the kernel die with an
@ -193,7 +193,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
{
unsigned int tmp;
smp_mb();
smp_llsc_mb();
if (R10000_LLSC_WAR) {
__asm__ __volatile__(
@ -262,7 +262,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
: "memory");
}
smp_mb();
smp_llsc_mb();
}
static inline void __raw_write_unlock(raw_rwlock_t *rw)
@ -293,7 +293,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
" .set reorder \n"
" beqzl %1, 1b \n"
" nop \n"
__WEAK_ORDERING_MB
__WEAK_LLSC_MB
" li %2, 1 \n"
"2: \n"
: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
@ -310,7 +310,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
" beqz %1, 1b \n"
" nop \n"
" .set reorder \n"
__WEAK_ORDERING_MB
__WEAK_LLSC_MB
" li %2, 1 \n"
"2: \n"
: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
@ -336,7 +336,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
" sc %1, %0 \n"
" beqzl %1, 1b \n"
" nop \n"
__WEAK_ORDERING_MB
__WEAK_LLSC_MB
" li %2, 1 \n"
" .set reorder \n"
"2: \n"
@ -354,7 +354,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
" beqz %1, 3f \n"
" li %2, 1 \n"
"2: \n"
__WEAK_ORDERING_MB
__WEAK_LLSC_MB
" .subsection 2 \n"
"3: b 1b \n"
" li %2, 0 \n"

10
include/asm-mips/system.h
View File

@ -117,7 +117,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
raw_local_irq_restore(flags); /* implies memory barrier */
}
smp_mb();
smp_llsc_mb();
return retval;
}
@ -165,7 +165,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
raw_local_irq_restore(flags); /* implies memory barrier */
}
smp_mb();
smp_llsc_mb();
return retval;
}
@ -246,7 +246,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
raw_local_irq_restore(flags); /* implies memory barrier */
}
smp_mb();
smp_llsc_mb();
return retval;
}
@ -352,7 +352,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
raw_local_irq_restore(flags); /* implies memory barrier */
}
smp_mb();
smp_llsc_mb();
return retval;
}
@ -470,6 +470,6 @@ extern int stop_a_enabled;
*/
#define __ARCH_WANT_UNLOCKED_CTXSW
#define arch_align_stack(x) (x)
extern unsigned long arch_align_stack(unsigned long sp);
#endif /* _ASM_SYSTEM_H */