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mlxsw: Use one enum for all registers that contain tunnel_port field

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Currently SFN, TNUMT and TNPC registers use separate enums for
tunnel_port.

Create one enum with a neutral name and use it.
Remove the enums that are not currently required.

The next patches add two more registers that contain tunnel_port field,
the new enum can be used for them also.

Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Amit Cohen 2020-12-08 11:22:41 +02:00 committed by David S. Miller
parent a8d5dd192a
commit 02c3b5c5d0
3 changed files with 11 additions and 25 deletions
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32
drivers/net/ethernet/mellanox/mlxsw/reg.h
View File

@ -581,6 +581,13 @@ mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
}
enum mlxsw_reg_tunnel_port {
MLXSW_REG_TUNNEL_PORT_NVE,
MLXSW_REG_TUNNEL_PORT_VPLS,
MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0,
MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1,
};
/* SFN - Switch FDB Notification Register
* -------------------------------------------
* The switch provides notifications on newly learned FDB entries and
@ -738,13 +745,6 @@ MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
enum mlxsw_reg_sfn_tunnel_port {
MLXSW_REG_SFN_TUNNEL_PORT_NVE,
MLXSW_REG_SFN_TUNNEL_PORT_VPLS,
MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0,
MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1,
};
/* reg_sfn_uc_tunnel_port
* Tunnel port.
* Reserved on Spectrum.
@ -10507,13 +10507,6 @@ enum mlxsw_reg_tnumt_record_type {
*/
MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
enum mlxsw_reg_tnumt_tunnel_port {
MLXSW_REG_TNUMT_TUNNEL_PORT_NVE,
MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS,
MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0,
MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1,
};
/* reg_tnumt_tunnel_port
* Tunnel port.
* Access: RW
@ -10561,7 +10554,7 @@ MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
static inline void mlxsw_reg_tnumt_pack(char *payload,
enum mlxsw_reg_tnumt_record_type type,
enum mlxsw_reg_tnumt_tunnel_port tport,
enum mlxsw_reg_tunnel_port tport,
u32 underlay_mc_ptr, bool vnext,
u32 next_underlay_mc_ptr,
u8 record_size)
@ -10725,13 +10718,6 @@ static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
enum mlxsw_reg_tnpc_tunnel_port {
MLXSW_REG_TNPC_TUNNEL_PORT_NVE,
MLXSW_REG_TNPC_TUNNEL_PORT_VPLS,
MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0,
MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1,
};
/* reg_tnpc_tunnel_port
* Tunnel port.
* Access: Index
@ -10751,7 +10737,7 @@ MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
static inline void mlxsw_reg_tnpc_pack(char *payload,
enum mlxsw_reg_tnpc_tunnel_port tport,
enum mlxsw_reg_tunnel_port tport,
bool learn_enable)
{
MLXSW_REG_ZERO(tnpc, payload);

2
drivers/net/ethernet/mellanox/mlxsw/spectrum_nve.c
View File

@ -368,7 +368,7 @@ mlxsw_sp_nve_mc_record_refresh(struct mlxsw_sp_nve_mc_record *mc_record)
next_valid = true;
}
mlxsw_reg_tnumt_pack(tnumt_pl, type, MLXSW_REG_TNUMT_TUNNEL_PORT_NVE,
mlxsw_reg_tnumt_pack(tnumt_pl, type, MLXSW_REG_TUNNEL_PORT_NVE,
mc_record->kvdl_index, next_valid,
next_kvdl_index, mc_record->num_entries);

2
drivers/net/ethernet/mellanox/mlxsw/spectrum_nve_vxlan.c
View File

@ -299,7 +299,7 @@ static bool mlxsw_sp2_nve_vxlan_learning_set(struct mlxsw_sp *mlxsw_sp,
{
char tnpc_pl[MLXSW_REG_TNPC_LEN];
mlxsw_reg_tnpc_pack(tnpc_pl, MLXSW_REG_TNPC_TUNNEL_PORT_NVE,
mlxsw_reg_tnpc_pack(tnpc_pl, MLXSW_REG_TUNNEL_PORT_NVE,
learning_en);
return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(tnpc), tnpc_pl);
}