drm/nouveau/gr/gf100: split gf100_gr_init_ctxctl()
gf100_gr_init_ctxctl() is basically two different functions (one for use of internal firmware, the other for use of external firmware), but its current layout makes it look more complex than it is. Split it to better reflect that fact. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Alexandre Courbot
Ben Skeggs
parent
d2753f40a9
commit
0296b5d985
@ -1455,134 +1455,139 @@ gf100_gr_init_csdata(struct gf100_gr *gr,
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nvkm_wr32(device, falcon + 0x01c4, star + 4);
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}
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int
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gf100_gr_init_ctxctl(struct gf100_gr *gr)
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/* Initialize context from an external (secure or not) firmware */
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static int
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gf100_gr_init_ctxctl_ext(struct gf100_gr *gr)
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{
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_secboot *sb = device->secboot;
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int ret = 0;
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/* load fuc microcode */
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nvkm_mc_unk260(device, 0);
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/* securely-managed falcons must be reset using secure boot */
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
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ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_FECS);
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else
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gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, &gr->fuc409d);
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if (ret)
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return ret;
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
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ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_GPCCS);
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else
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gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, &gr->fuc41ad);
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if (ret)
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return ret;
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nvkm_mc_unk260(device, 1);
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/* start both of them running */
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nvkm_wr32(device, 0x409840, 0xffffffff);
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nvkm_wr32(device, 0x41a10c, 0x00000000);
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nvkm_wr32(device, 0x40910c, 0x00000000);
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
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nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_GPCCS);
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else
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nvkm_wr32(device, 0x41a100, 0x00000002);
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
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nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_FECS);
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else
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nvkm_wr32(device, 0x409100, 0x00000002);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x409800) & 0x00000001)
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break;
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) < 0)
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return -EBUSY;
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nvkm_wr32(device, 0x409840, 0xffffffff);
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nvkm_wr32(device, 0x409500, 0x7fffffff);
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nvkm_wr32(device, 0x409504, 0x00000021);
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nvkm_wr32(device, 0x409840, 0xffffffff);
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nvkm_wr32(device, 0x409500, 0x00000000);
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nvkm_wr32(device, 0x409504, 0x00000010);
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if (nvkm_msec(device, 2000,
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if ((gr->size = nvkm_rd32(device, 0x409800)))
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break;
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) < 0)
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return -EBUSY;
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nvkm_wr32(device, 0x409840, 0xffffffff);
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nvkm_wr32(device, 0x409500, 0x00000000);
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nvkm_wr32(device, 0x409504, 0x00000016);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x409800))
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break;
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) < 0)
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return -EBUSY;
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nvkm_wr32(device, 0x409840, 0xffffffff);
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nvkm_wr32(device, 0x409500, 0x00000000);
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nvkm_wr32(device, 0x409504, 0x00000025);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x409800))
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break;
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) < 0)
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return -EBUSY;
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if (device->chipset >= 0xe0) {
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nvkm_wr32(device, 0x409800, 0x00000000);
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nvkm_wr32(device, 0x409500, 0x00000001);
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nvkm_wr32(device, 0x409504, 0x00000030);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x409800))
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break;
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) < 0)
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return -EBUSY;
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nvkm_wr32(device, 0x409810, 0xb00095c8);
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nvkm_wr32(device, 0x409800, 0x00000000);
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nvkm_wr32(device, 0x409500, 0x00000001);
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nvkm_wr32(device, 0x409504, 0x00000031);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x409800))
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break;
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) < 0)
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return -EBUSY;
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nvkm_wr32(device, 0x409810, 0x00080420);
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nvkm_wr32(device, 0x409800, 0x00000000);
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nvkm_wr32(device, 0x409500, 0x00000001);
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nvkm_wr32(device, 0x409504, 0x00000032);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x409800))
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break;
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) < 0)
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return -EBUSY;
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nvkm_wr32(device, 0x409614, 0x00000070);
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nvkm_wr32(device, 0x409614, 0x00000770);
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nvkm_wr32(device, 0x40802c, 0x00000001);
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}
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if (gr->data == NULL) {
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int ret = gf100_grctx_generate(gr);
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if (ret) {
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nvkm_error(subdev, "failed to construct context\n");
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return ret;
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}
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}
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return 0;
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}
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static int
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gf100_gr_init_ctxctl_int(struct gf100_gr *gr)
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{
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const struct gf100_grctx_func *grctx = gr->func->grctx;
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_secboot *sb = device->secboot;
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int i;
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int ret = 0;
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if (gr->firmware) {
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/* load fuc microcode */
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nvkm_mc_unk260(device, 0);
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/* securely-managed falcons must be reset using secure boot */
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
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ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_FECS);
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else
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gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c,
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&gr->fuc409d);
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if (ret)
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return ret;
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
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ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_GPCCS);
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else
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gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac,
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&gr->fuc41ad);
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if (ret)
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return ret;
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nvkm_mc_unk260(device, 1);
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/* start both of them running */
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nvkm_wr32(device, 0x409840, 0xffffffff);
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nvkm_wr32(device, 0x41a10c, 0x00000000);
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nvkm_wr32(device, 0x40910c, 0x00000000);
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
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nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_GPCCS);
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else
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nvkm_wr32(device, 0x41a100, 0x00000002);
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
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nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_FECS);
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else
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nvkm_wr32(device, 0x409100, 0x00000002);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x409800) & 0x00000001)
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break;
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) < 0)
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return -EBUSY;
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nvkm_wr32(device, 0x409840, 0xffffffff);
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nvkm_wr32(device, 0x409500, 0x7fffffff);
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nvkm_wr32(device, 0x409504, 0x00000021);
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nvkm_wr32(device, 0x409840, 0xffffffff);
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nvkm_wr32(device, 0x409500, 0x00000000);
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nvkm_wr32(device, 0x409504, 0x00000010);
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if (nvkm_msec(device, 2000,
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if ((gr->size = nvkm_rd32(device, 0x409800)))
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break;
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) < 0)
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return -EBUSY;
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nvkm_wr32(device, 0x409840, 0xffffffff);
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nvkm_wr32(device, 0x409500, 0x00000000);
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nvkm_wr32(device, 0x409504, 0x00000016);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x409800))
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break;
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) < 0)
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return -EBUSY;
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nvkm_wr32(device, 0x409840, 0xffffffff);
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nvkm_wr32(device, 0x409500, 0x00000000);
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nvkm_wr32(device, 0x409504, 0x00000025);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x409800))
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break;
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) < 0)
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return -EBUSY;
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if (device->chipset >= 0xe0) {
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nvkm_wr32(device, 0x409800, 0x00000000);
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nvkm_wr32(device, 0x409500, 0x00000001);
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nvkm_wr32(device, 0x409504, 0x00000030);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x409800))
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break;
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) < 0)
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return -EBUSY;
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nvkm_wr32(device, 0x409810, 0xb00095c8);
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nvkm_wr32(device, 0x409800, 0x00000000);
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nvkm_wr32(device, 0x409500, 0x00000001);
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nvkm_wr32(device, 0x409504, 0x00000031);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x409800))
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break;
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) < 0)
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return -EBUSY;
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nvkm_wr32(device, 0x409810, 0x00080420);
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nvkm_wr32(device, 0x409800, 0x00000000);
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nvkm_wr32(device, 0x409500, 0x00000001);
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nvkm_wr32(device, 0x409504, 0x00000032);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x409800))
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break;
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) < 0)
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return -EBUSY;
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nvkm_wr32(device, 0x409614, 0x00000070);
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nvkm_wr32(device, 0x409614, 0x00000770);
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nvkm_wr32(device, 0x40802c, 0x00000001);
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}
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if (gr->data == NULL) {
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int ret = gf100_grctx_generate(gr);
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if (ret) {
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nvkm_error(subdev, "failed to construct context\n");
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return ret;
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}
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}
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return 0;
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} else
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if (!gr->func->fecs.ucode) {
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return -ENOSYS;
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}
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@ -1642,6 +1647,19 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr)
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return 0;
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}
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int
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gf100_gr_init_ctxctl(struct gf100_gr *gr)
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{
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int ret;
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if (gr->firmware)
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ret = gf100_gr_init_ctxctl_ext(gr);
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else
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ret = gf100_gr_init_ctxctl_int(gr);
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return ret;
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}
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static int
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gf100_gr_oneinit(struct nvkm_gr *base)
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{
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