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drm/i915/guc/slpc: Cache platform frequency limits

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Cache rp0, rp1 and rpn platform limits into SLPC structure
for range checking while setting min/max frequencies.

Also add "soft" limits which keep track of frequency changes
made from userland. These are initially set to platform min
and max.

v2: Address review comments (Michal W)
v3: Formatting (Michal W)
v4: Add separate function to parse rp values (Michal W)
v5: Perform range checking for set min/max (Michal W)
v6: checkpatch() and rename static functions (Michal W)
v7: check ret code while setting SLPC limits (Michal W)

Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210730202119.23810-12-vinay.belgaumkar@intel.com
This commit is contained in:
Vinay Belgaumkar 2021-07-30 13:21:16 -07:00 committed by John Harrison
parent 899a0fd73a
commit 025cb07beb
3 changed files with 151 additions and 0 deletions
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139
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
View File

@ -96,6 +96,9 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
return err;
}
slpc->max_freq_softlimit = 0;
slpc->min_freq_softlimit = 0;
return err;
}
@ -126,6 +129,17 @@ static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
return ret > 0 ? -EPROTO : ret;
}
static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
{
u32 request[] = {
GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 2),
id,
};
return intel_guc_send(guc, request, ARRAY_SIZE(request));
}
static bool slpc_is_running(struct intel_guc_slpc *slpc)
{
return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
@ -179,6 +193,16 @@ static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
return ret;
}
static int slpc_unset_param(struct intel_guc_slpc *slpc,
u8 id)
{
struct intel_guc *guc = slpc_to_guc(slpc);
GEM_BUG_ON(id >= SLPC_MAX_PARAM);
return guc_action_slpc_unset_param(guc, id);
}
static const char *slpc_global_state_to_string(enum slpc_global_state state)
{
switch (state) {
@ -300,6 +324,11 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
intel_wakeref_t wakeref;
int ret;
if (val < slpc->min_freq ||
val > slpc->rp0_freq ||
val < slpc->min_freq_softlimit)
return -EINVAL;
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
ret = slpc_set_param(slpc,
SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
@ -310,6 +339,9 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
ret = -EIO;
}
if (!ret)
slpc->max_freq_softlimit = val;
return ret;
}
@ -356,6 +388,11 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
intel_wakeref_t wakeref;
int ret;
if (val < slpc->min_freq ||
val > slpc->rp0_freq ||
val > slpc->max_freq_softlimit)
return -EINVAL;
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
ret = slpc_set_param(slpc,
SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
@ -366,6 +403,9 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
ret = -EIO;
}
if (!ret)
slpc->min_freq_softlimit = val;
return ret;
}
@ -411,6 +451,79 @@ void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
}
static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
{
int ret = 0;
/*
* Softlimits are initially equivalent to platform limits
* unless they have deviated from defaults, in which case,
* we retain the values and set min/max accordingly.
*/
if (!slpc->max_freq_softlimit)
slpc->max_freq_softlimit = slpc->rp0_freq;
else if (slpc->max_freq_softlimit != slpc->rp0_freq)
ret = intel_guc_slpc_set_max_freq(slpc,
slpc->max_freq_softlimit);
if (unlikely(ret))
return ret;
if (!slpc->min_freq_softlimit)
slpc->min_freq_softlimit = slpc->min_freq;
else if (slpc->min_freq_softlimit != slpc->min_freq)
return intel_guc_slpc_set_min_freq(slpc,
slpc->min_freq_softlimit);
return 0;
}
static int slpc_ignore_eff_freq(struct intel_guc_slpc *slpc, bool ignore)
{
int ret = 0;
if (ignore) {
ret = slpc_set_param(slpc,
SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
ignore);
if (!ret)
return slpc_set_param(slpc,
SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
slpc->min_freq);
} else {
ret = slpc_unset_param(slpc,
SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY);
if (!ret)
return slpc_unset_param(slpc,
SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ);
}
return ret;
}
static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
{
/* Force SLPC to used platform rp0 */
return slpc_set_param(slpc,
SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
slpc->rp0_freq);
}
static void slpc_get_rp_values(struct intel_guc_slpc *slpc)
{
u32 rp_state_cap;
rp_state_cap = intel_uncore_read(slpc_to_gt(slpc)->uncore,
GEN6_RP_STATE_CAP);
slpc->rp0_freq = REG_FIELD_GET(RP0_CAP_MASK, rp_state_cap) *
GT_FREQUENCY_MULTIPLIER;
slpc->rp1_freq = REG_FIELD_GET(RP1_CAP_MASK, rp_state_cap) *
GT_FREQUENCY_MULTIPLIER;
slpc->min_freq = REG_FIELD_GET(RPN_CAP_MASK, rp_state_cap) *
GT_FREQUENCY_MULTIPLIER;
}
/*
* intel_guc_slpc_enable() - Start SLPC
* @slpc: pointer to intel_guc_slpc.
@ -446,6 +559,32 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
intel_guc_pm_intrmsk_enable(&i915->gt);
slpc_get_rp_values(slpc);
/* Ignore efficient freq and set min to platform min */
ret = slpc_ignore_eff_freq(slpc, true);
if (unlikely(ret)) {
drm_err(&i915->drm, "Failed to set SLPC min to RPn (%pe)\n",
ERR_PTR(ret));
return ret;
}
/* Set SLPC max limit to RP0 */
ret = slpc_use_fused_rp0(slpc);
if (unlikely(ret)) {
drm_err(&i915->drm, "Failed to set SLPC max to RP0 (%pe)\n",
ERR_PTR(ret));
return ret;
}
/* Revert SLPC min/max to softlimits if necessary */
ret = slpc_set_softlimits(slpc);
if (unlikely(ret)) {
drm_err(&i915->drm, "Failed to set SLPC softlimits (%pe)\n",
ERR_PTR(ret));
return ret;
}
return 0;
}

9
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
View File

@ -15,6 +15,15 @@ struct intel_guc_slpc {
struct slpc_shared_data *vaddr;
bool supported;
bool selected;
/* platform frequency limits */
u32 min_freq;
u32 rp0_freq;
u32 rp1_freq;
/* frequency softlimits */
u32 min_freq_softlimit;
u32 max_freq_softlimit;
};
#endif

3
drivers/gpu/drm/i915/i915_reg.h
View File

@ -4109,6 +4109,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
#define RP0_CAP_MASK REG_GENMASK(7, 0)
#define RP1_CAP_MASK REG_GENMASK(15, 8)
#define RPN_CAP_MASK REG_GENMASK(23, 16)
#define BXT_RP_STATE_CAP _MMIO(0x138170)
#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)