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drm/nouveau/fifo/gf100-: use new interfaces for vmm operations

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2017-11-01 03:56:19 +10:00
parent 8c967c5548
commit 01f349fcad
8 changed files with 28 additions and 36 deletions
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2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h
View File

@ -13,7 +13,7 @@ struct gf100_fifo_chan {
struct { struct {
struct nvkm_gpuobj *inst; struct nvkm_gpuobj *inst;
struct nvkm_vma vma; struct nvkm_vma *vma;
} engn[NVKM_SUBDEV_NR]; } engn[NVKM_SUBDEV_NR];
}; };

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h
View File

@ -14,7 +14,7 @@ struct gk104_fifo_chan {
struct { struct {
struct nvkm_gpuobj *inst; struct nvkm_gpuobj *inst;
struct nvkm_vma vma; struct nvkm_vma *vma;
} engn[NVKM_SUBDEV_NR]; } engn[NVKM_SUBDEV_NR];
}; };

12
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
View File

@ -28,7 +28,6 @@
#include <core/enum.h> #include <core/enum.h>
#include <core/gpuobj.h> #include <core/gpuobj.h>
#include <subdev/bar.h> #include <subdev/bar.h>
#include <subdev/fb.h>
#include <engine/sw.h> #include <engine/sw.h>
#include <nvif/class.h> #include <nvif/class.h>
@ -586,12 +585,12 @@ gf100_fifo_oneinit(struct nvkm_fifo *base)
if (ret) if (ret)
return ret; return ret;
ret = nvkm_vm_get(bar, nvkm_memory_size(fifo->user.mem), 12, ret = nvkm_vmm_get(bar, 12, nvkm_memory_size(fifo->user.mem),
NV_MEM_ACCESS_RW, &fifo->user.bar); &fifo->user.bar);
if (ret) if (ret)
return ret; return ret;
return nvkm_memory_map(fifo->user.mem, 0, bar, &fifo->user.bar, NULL, 0); return nvkm_memory_map(fifo->user.mem, 0, bar, fifo->user.bar, NULL, 0);
} }
static void static void
@ -630,7 +629,7 @@ gf100_fifo_init(struct nvkm_fifo *base)
} }
nvkm_mask(device, 0x002200, 0x00000001, 0x00000001); nvkm_mask(device, 0x002200, 0x00000001, 0x00000001);
nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12); nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar->addr >> 12);
nvkm_wr32(device, 0x002100, 0xffffffff); nvkm_wr32(device, 0x002100, 0xffffffff);
nvkm_wr32(device, 0x002140, 0x7fffffff); nvkm_wr32(device, 0x002140, 0x7fffffff);
@ -641,7 +640,8 @@ static void *
gf100_fifo_dtor(struct nvkm_fifo *base) gf100_fifo_dtor(struct nvkm_fifo *base)
{ {
struct gf100_fifo *fifo = gf100_fifo(base); struct gf100_fifo *fifo = gf100_fifo(base);
nvkm_vm_put(&fifo->user.bar); struct nvkm_device *device = fifo->base.engine.subdev.device;
nvkm_vmm_put(nvkm_bar_bar1_vmm(device), &fifo->user.bar);
nvkm_memory_unref(&fifo->user.mem); nvkm_memory_unref(&fifo->user.mem);
nvkm_memory_unref(&fifo->runlist.mem[0]); nvkm_memory_unref(&fifo->runlist.mem[0]);
nvkm_memory_unref(&fifo->runlist.mem[1]); nvkm_memory_unref(&fifo->runlist.mem[1]);

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h
View File

@ -26,7 +26,7 @@ struct gf100_fifo {
struct { struct {
struct nvkm_memory *mem; struct nvkm_memory *mem;
struct nvkm_vma bar; struct nvkm_vma *bar;
} user; } user;
}; };

12
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
View File

@ -27,7 +27,6 @@
#include <core/client.h> #include <core/client.h>
#include <core/gpuobj.h> #include <core/gpuobj.h>
#include <subdev/bar.h> #include <subdev/bar.h>
#include <subdev/fb.h>
#include <subdev/timer.h> #include <subdev/timer.h>
#include <subdev/top.h> #include <subdev/top.h>
#include <engine/sw.h> #include <engine/sw.h>
@ -836,12 +835,12 @@ gk104_fifo_oneinit(struct nvkm_fifo *base)
if (ret) if (ret)
return ret; return ret;
ret = nvkm_vm_get(bar, nvkm_memory_size(fifo->user.mem), 12, ret = nvkm_vmm_get(bar, 12, nvkm_memory_size(fifo->user.mem),
NV_MEM_ACCESS_RW, &fifo->user.bar); &fifo->user.bar);
if (ret) if (ret)
return ret; return ret;
return nvkm_memory_map(fifo->user.mem, 0, bar, &fifo->user.bar, NULL, 0); return nvkm_memory_map(fifo->user.mem, 0, bar, fifo->user.bar, NULL, 0);
} }
static void static void
@ -867,7 +866,7 @@ gk104_fifo_init(struct nvkm_fifo *base)
nvkm_wr32(device, 0x04014c + (i * 0x2000), 0xffffffff); /* INTREN */ nvkm_wr32(device, 0x04014c + (i * 0x2000), 0xffffffff); /* INTREN */
} }
nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12); nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar->addr >> 12);
nvkm_wr32(device, 0x002100, 0xffffffff); nvkm_wr32(device, 0x002100, 0xffffffff);
nvkm_wr32(device, 0x002140, 0x7fffffff); nvkm_wr32(device, 0x002140, 0x7fffffff);
@ -877,9 +876,10 @@ static void *
gk104_fifo_dtor(struct nvkm_fifo *base) gk104_fifo_dtor(struct nvkm_fifo *base)
{ {
struct gk104_fifo *fifo = gk104_fifo(base); struct gk104_fifo *fifo = gk104_fifo(base);
struct nvkm_device *device = fifo->base.engine.subdev.device;
int i; int i;
nvkm_vm_put(&fifo->user.bar); nvkm_vmm_put(nvkm_bar_bar1_vmm(device), &fifo->user.bar);
nvkm_memory_unref(&fifo->user.mem); nvkm_memory_unref(&fifo->user.mem);
for (i = 0; i < fifo->runlist_nr; i++) { for (i = 0; i < fifo->runlist_nr; i++) {

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
View File

@ -37,7 +37,7 @@ struct gk104_fifo {
struct { struct {
struct nvkm_memory *mem; struct nvkm_memory *mem;
struct nvkm_vma bar; struct nvkm_vma *bar;
} user; } user;
}; };

16
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
View File

@ -111,7 +111,7 @@ gf100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
struct nvkm_gpuobj *inst = chan->base.inst; struct nvkm_gpuobj *inst = chan->base.inst;
if (offset) { if (offset) {
u64 addr = chan->engn[engine->subdev.index].vma.offset; u64 addr = chan->engn[engine->subdev.index].vma->addr;
nvkm_kmap(inst); nvkm_kmap(inst);
nvkm_wo32(inst, offset + 0x00, lower_32_bits(addr) | 4); nvkm_wo32(inst, offset + 0x00, lower_32_bits(addr) | 4);
nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr)); nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr));
@ -126,11 +126,7 @@ gf100_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base,
struct nvkm_engine *engine) struct nvkm_engine *engine)
{ {
struct gf100_fifo_chan *chan = gf100_fifo_chan(base); struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
struct nvkm_vma *vma = &chan->engn[engine->subdev.index].vma; nvkm_vmm_put(chan->base.vmm, &chan->engn[engine->subdev.index].vma);
if (vma->vm) {
nvkm_vm_unmap(vma);
nvkm_vm_put(vma);
}
nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst); nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst);
} }
@ -150,13 +146,13 @@ gf100_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base,
if (ret) if (ret)
return ret; return ret;
ret = nvkm_vm_get(chan->base.vmm, chan->engn[engn].inst->size, 12, ret = nvkm_vmm_get(chan->base.vmm, 12, chan->engn[engn].inst->size,
NV_MEM_ACCESS_RW, &chan->engn[engn].vma); &chan->engn[engn].vma);
if (ret) if (ret)
return ret; return ret;
return nvkm_memory_map(chan->engn[engn].inst, 0, chan->base.vmm, return nvkm_memory_map(chan->engn[engn].inst, 0, chan->base.vmm,
&chan->engn[engn].vma, NULL, 0); chan->engn[engn].vma, NULL, 0);
} }
static void static void
@ -252,7 +248,7 @@ gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
(1ULL << NVKM_ENGINE_MSPPP) | (1ULL << NVKM_ENGINE_MSPPP) |
(1ULL << NVKM_ENGINE_MSVLD) | (1ULL << NVKM_ENGINE_MSVLD) |
(1ULL << NVKM_ENGINE_SW), (1ULL << NVKM_ENGINE_SW),
1, fifo->user.bar.offset, 0x1000, 1, fifo->user.bar->addr, 0x1000,
oclass, &chan->base); oclass, &chan->base);
if (ret) if (ret)
return ret; return ret;

16
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
View File

@ -117,7 +117,7 @@ gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
u32 offset = gk104_fifo_gpfifo_engine_addr(engine); u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
if (offset) { if (offset) {
u64 addr = chan->engn[engine->subdev.index].vma.offset; u64 addr = chan->engn[engine->subdev.index].vma->addr;
u32 datalo = lower_32_bits(addr) | 0x00000004; u32 datalo = lower_32_bits(addr) | 0x00000004;
u32 datahi = upper_32_bits(addr); u32 datahi = upper_32_bits(addr);
nvkm_kmap(inst); nvkm_kmap(inst);
@ -138,11 +138,7 @@ gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base,
struct nvkm_engine *engine) struct nvkm_engine *engine)
{ {
struct gk104_fifo_chan *chan = gk104_fifo_chan(base); struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
struct nvkm_vma *vma = &chan->engn[engine->subdev.index].vma; nvkm_vmm_put(chan->base.vmm, &chan->engn[engine->subdev.index].vma);
if (vma->vm) {
nvkm_vm_unmap(vma);
nvkm_vm_put(vma);
}
nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst); nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst);
} }
@ -162,13 +158,13 @@ gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base,
if (ret) if (ret)
return ret; return ret;
ret = nvkm_vm_get(chan->base.vmm, chan->engn[engn].inst->size, 12, ret = nvkm_vmm_get(chan->base.vmm, 12, chan->engn[engn].inst->size,
NV_MEM_ACCESS_RW, &chan->engn[engn].vma); &chan->engn[engn].vma);
if (ret) if (ret)
return ret; return ret;
return nvkm_memory_map(chan->engn[engn].inst, 0, chan->base.vmm, return nvkm_memory_map(chan->engn[engn].inst, 0, chan->base.vmm,
&chan->engn[engn].vma, NULL, 0); chan->engn[engn].vma, NULL, 0);
} }
static void static void
@ -291,7 +287,7 @@ gk104_fifo_gpfifo_new_(const struct gk104_fifo_chan_func *func,
ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base, ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base,
0x1000, 0x1000, true, vm, 0, subdevs, 0x1000, 0x1000, true, vm, 0, subdevs,
1, fifo->user.bar.offset, 0x200, 1, fifo->user.bar->addr, 0x200,
oclass, &chan->base); oclass, &chan->base);
if (ret) if (ret)
return ret; return ret;