forked from Minki/linux
net/r8169: support RTL8168E
Support RTL8168E/RTL8111E. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
hayeswang
David S. Miller
parent
4804b3b3ae
commit
01dc7fec40
@ -37,6 +37,8 @@
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#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
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#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
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#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
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#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
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#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
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#ifdef RTL8169_DEBUG
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@ -128,6 +130,8 @@ enum mac_version {
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RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
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RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
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RTL_GIGA_MAC_VER_31 = 0x1f, // 8168DP
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RTL_GIGA_MAC_VER_32 = 0x20, // 8168E
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RTL_GIGA_MAC_VER_33 = 0x21, // 8168E
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};
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#define _R(NAME,MAC,MASK) \
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@ -168,7 +172,9 @@ static const struct {
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_R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E
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_R("RTL8105e", RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E
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_R("RTL8105e", RTL_GIGA_MAC_VER_30, 0xff7e1880), // PCI-E
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_R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_31, 0xff7e1880) // PCI-E
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_R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_31, 0xff7e1880), // PCI-E
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_R("RTL8168e/8111e", RTL_GIGA_MAC_VER_32, 0xff7e1880), // PCI-E
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_R("RTL8168e/8111e", RTL_GIGA_MAC_VER_33, 0xff7e1880) // PCI-E
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};
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#undef _R
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@ -317,7 +323,9 @@ enum rtl8168_registers {
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#define OCPAR_FLAG 0x80000000
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#define OCPAR_GPHY_WRITE_CMD 0x8000f060
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#define OCPAR_GPHY_READ_CMD 0x0000f060
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RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
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RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
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MISC = 0xf0, /* 8168e only. */
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txpla_rst = (1 << 29)
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};
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enum rtl_register_content {
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@ -395,6 +403,7 @@ enum rtl_register_content {
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BWF = (1 << 6), /* Accept Broadcast wakeup frame */
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MWF = (1 << 5), /* Accept Multicast wakeup frame */
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UWF = (1 << 4), /* Accept Unicast wakeup frame */
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spi_en = (1 << 3),
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LanWake = (1 << 1), /* LanWake enable/disable */
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PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
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@ -579,6 +588,8 @@ MODULE_LICENSE("GPL");
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MODULE_VERSION(RTL8169_VERSION);
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MODULE_FIRMWARE(FIRMWARE_8168D_1);
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MODULE_FIRMWARE(FIRMWARE_8168D_2);
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MODULE_FIRMWARE(FIRMWARE_8168E_1);
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MODULE_FIRMWARE(FIRMWARE_8168E_2);
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MODULE_FIRMWARE(FIRMWARE_8105E_1);
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static int rtl8169_open(struct net_device *dev);
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@ -1575,6 +1586,11 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
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u32 val;
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int mac_version;
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} mac_info[] = {
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/* 8168E family. */
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{ 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
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{ 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
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{ 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
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/* 8168D family. */
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{ 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
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{ 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
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@ -2466,6 +2482,93 @@ static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
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rtl_patchphy(tp, 0x0d, 1 << 5);
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}
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static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
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{
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static const struct phy_reg phy_reg_init[] = {
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/* Enable Delay cap */
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{ 0x1f, 0x0005 },
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{ 0x05, 0x8b80 },
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{ 0x06, 0xc896 },
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{ 0x1f, 0x0000 },
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/* Channel estimation fine tune */
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{ 0x1f, 0x0001 },
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{ 0x0b, 0x6c20 },
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{ 0x07, 0x2872 },
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{ 0x1c, 0xefff },
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{ 0x1f, 0x0003 },
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{ 0x14, 0x6420 },
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{ 0x1f, 0x0000 },
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/* Update PFM & 10M TX idle timer */
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{ 0x1f, 0x0007 },
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{ 0x1e, 0x002f },
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{ 0x15, 0x1919 },
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{ 0x1f, 0x0000 },
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{ 0x1f, 0x0007 },
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{ 0x1e, 0x00ac },
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{ 0x18, 0x0006 },
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{ 0x1f, 0x0000 }
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};
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rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
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/* DCO enable for 10M IDLE Power */
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rtl_writephy(tp, 0x1f, 0x0007);
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rtl_writephy(tp, 0x1e, 0x0023);
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rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
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rtl_writephy(tp, 0x1f, 0x0000);
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/* For impedance matching */
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rtl_writephy(tp, 0x1f, 0x0002);
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rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
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rtl_writephy(tp, 0x1F, 0x0000);
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/* PHY auto speed down */
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rtl_writephy(tp, 0x1f, 0x0007);
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rtl_writephy(tp, 0x1e, 0x002d);
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rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
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rtl_writephy(tp, 0x1f, 0x0000);
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rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
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rtl_writephy(tp, 0x1f, 0x0005);
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rtl_writephy(tp, 0x05, 0x8b86);
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rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
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rtl_writephy(tp, 0x1f, 0x0000);
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rtl_writephy(tp, 0x1f, 0x0005);
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rtl_writephy(tp, 0x05, 0x8b85);
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rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
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rtl_writephy(tp, 0x1f, 0x0007);
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rtl_writephy(tp, 0x1e, 0x0020);
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rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
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rtl_writephy(tp, 0x1f, 0x0006);
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rtl_writephy(tp, 0x00, 0x5a00);
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rtl_writephy(tp, 0x1f, 0x0000);
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rtl_writephy(tp, 0x0d, 0x0007);
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rtl_writephy(tp, 0x0e, 0x003c);
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rtl_writephy(tp, 0x0d, 0x4007);
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rtl_writephy(tp, 0x0e, 0x0000);
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rtl_writephy(tp, 0x0d, 0x0000);
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}
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static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
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{
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if (rtl_apply_firmware(tp, FIRMWARE_8168E_1) < 0)
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netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
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rtl8168e_hw_phy_config(tp);
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}
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static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
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{
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if (rtl_apply_firmware(tp, FIRMWARE_8168E_2) < 0)
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netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
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rtl8168e_hw_phy_config(tp);
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}
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static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
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{
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static const struct phy_reg phy_reg_init[] = {
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@ -2581,6 +2684,12 @@ static void rtl_hw_phy_config(struct net_device *dev)
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case RTL_GIGA_MAC_VER_30:
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rtl8105e_hw_phy_config(tp);
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break;
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case RTL_GIGA_MAC_VER_32:
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rtl8168e_1_hw_phy_config(tp);
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break;
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case RTL_GIGA_MAC_VER_33:
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rtl8168e_2_hw_phy_config(tp);
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break;
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default:
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break;
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@ -2931,15 +3040,59 @@ static void r810x_pll_power_up(struct rtl8169_private *tp)
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static void r8168_phy_power_up(struct rtl8169_private *tp)
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{
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rtl_writephy(tp, 0x1f, 0x0000);
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rtl_writephy(tp, 0x0e, 0x0000);
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_11:
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case RTL_GIGA_MAC_VER_12:
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case RTL_GIGA_MAC_VER_17:
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case RTL_GIGA_MAC_VER_18:
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case RTL_GIGA_MAC_VER_19:
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case RTL_GIGA_MAC_VER_20:
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case RTL_GIGA_MAC_VER_21:
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case RTL_GIGA_MAC_VER_22:
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case RTL_GIGA_MAC_VER_23:
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case RTL_GIGA_MAC_VER_24:
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case RTL_GIGA_MAC_VER_25:
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case RTL_GIGA_MAC_VER_26:
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case RTL_GIGA_MAC_VER_27:
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case RTL_GIGA_MAC_VER_28:
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case RTL_GIGA_MAC_VER_31:
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rtl_writephy(tp, 0x0e, 0x0000);
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break;
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default:
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break;
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}
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rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
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}
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static void r8168_phy_power_down(struct rtl8169_private *tp)
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{
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rtl_writephy(tp, 0x1f, 0x0000);
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rtl_writephy(tp, 0x0e, 0x0200);
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rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_32:
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case RTL_GIGA_MAC_VER_33:
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rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
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break;
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case RTL_GIGA_MAC_VER_11:
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case RTL_GIGA_MAC_VER_12:
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case RTL_GIGA_MAC_VER_17:
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case RTL_GIGA_MAC_VER_18:
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case RTL_GIGA_MAC_VER_19:
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case RTL_GIGA_MAC_VER_20:
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case RTL_GIGA_MAC_VER_21:
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case RTL_GIGA_MAC_VER_22:
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case RTL_GIGA_MAC_VER_23:
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case RTL_GIGA_MAC_VER_24:
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case RTL_GIGA_MAC_VER_25:
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case RTL_GIGA_MAC_VER_26:
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case RTL_GIGA_MAC_VER_27:
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case RTL_GIGA_MAC_VER_28:
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case RTL_GIGA_MAC_VER_31:
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rtl_writephy(tp, 0x0e, 0x0200);
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default:
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rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
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break;
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}
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}
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static void r8168_pll_power_down(struct rtl8169_private *tp)
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@ -2959,6 +3112,10 @@ static void r8168_pll_power_down(struct rtl8169_private *tp)
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return;
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}
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if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
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tp->mac_version == RTL_GIGA_MAC_VER_33)
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rtl_ephy_write(ioaddr, 0x19, 0xff64);
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if (__rtl8169_get_wol(tp) & WAKE_ANY) {
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rtl_writephy(tp, 0x1f, 0x0000);
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rtl_writephy(tp, MII_BMCR, 0x0000);
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@ -2976,6 +3133,8 @@ static void r8168_pll_power_down(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_27:
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case RTL_GIGA_MAC_VER_28:
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case RTL_GIGA_MAC_VER_31:
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case RTL_GIGA_MAC_VER_32:
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case RTL_GIGA_MAC_VER_33:
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RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
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break;
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}
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@ -2998,6 +3157,8 @@ static void r8168_pll_power_up(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_27:
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case RTL_GIGA_MAC_VER_28:
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case RTL_GIGA_MAC_VER_31:
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case RTL_GIGA_MAC_VER_32:
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case RTL_GIGA_MAC_VER_33:
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RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
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break;
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}
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@ -3053,6 +3214,8 @@ static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_27:
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case RTL_GIGA_MAC_VER_28:
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case RTL_GIGA_MAC_VER_31:
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case RTL_GIGA_MAC_VER_32:
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case RTL_GIGA_MAC_VER_33:
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ops->down = r8168_pll_power_down;
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ops->up = r8168_pll_power_up;
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break;
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@ -3855,6 +4018,41 @@ static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
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rtl_enable_clock_request(pdev);
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}
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static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
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{
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static const struct ephy_info e_info_8168e[] = {
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{ 0x00, 0x0200, 0x0100 },
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{ 0x00, 0x0000, 0x0004 },
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{ 0x06, 0x0002, 0x0001 },
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{ 0x06, 0x0000, 0x0030 },
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{ 0x07, 0x0000, 0x2000 },
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{ 0x00, 0x0000, 0x0020 },
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{ 0x03, 0x5800, 0x2000 },
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{ 0x03, 0x0000, 0x0001 },
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{ 0x01, 0x0800, 0x1000 },
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{ 0x07, 0x0000, 0x4000 },
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{ 0x1e, 0x0000, 0x2000 },
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{ 0x19, 0xffff, 0xfe6c },
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{ 0x0a, 0x0000, 0x0040 }
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};
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rtl_csi_access_enable_2(ioaddr);
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rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
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rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
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RTL_W8(MaxTxPacketSize, TxPacketMax);
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rtl_disable_clock_request(pdev);
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/* Reset tx FIFO pointer */
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RTL_W32(MISC, RTL_R32(MISC) | txpla_rst);
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RTL_W32(MISC, RTL_R32(MISC) & ~txpla_rst);
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RTL_W8(Config5, RTL_R8(Config5) & ~spi_en);
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}
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static void rtl_hw_start_8168(struct net_device *dev)
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{
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struct rtl8169_private *tp = netdev_priv(dev);
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@ -3940,6 +4138,10 @@ static void rtl_hw_start_8168(struct net_device *dev)
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rtl_hw_start_8168dp(ioaddr, pdev);
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break;
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case RTL_GIGA_MAC_VER_32:
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case RTL_GIGA_MAC_VER_33:
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rtl_hw_start_8168e(ioaddr, pdev);
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break;
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default:
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printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
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