forked from Minki/linux
edac: Improve the comments to better describe the memory concepts
The Computer memory terminology has changed with time since EDAC was originally written: new concepts were introduced, and some things have different meanings, depending on the memory architecture. Improve the definition of all related terms. Also, describe each memory type in a more detailed fashion. No functional changes. Just comments were touched. Acked-by: Borislav Petkov <borislav.petkov@amd.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab
parent
b877763ea0
commit
01a6e28b50
@ -66,25 +66,64 @@ enum dev_type {
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#define DEV_FLAG_X32 BIT(DEV_X32)
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#define DEV_FLAG_X64 BIT(DEV_X64)
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/* memory types */
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/**
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* enum mem_type - memory types. For a more detailed reference, please see
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* http://en.wikipedia.org/wiki/DRAM
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*
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* @MEM_EMPTY Empty csrow
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* @MEM_RESERVED: Reserved csrow type
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* @MEM_UNKNOWN: Unknown csrow type
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* @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
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* @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
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* @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
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* @MEM_SDR: SDR - Single data rate SDRAM
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* http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
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* They use 3 pins for chip select: Pins 0 and 2 are
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* for rank 0; pins 1 and 3 are for rank 1, if the memory
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* is dual-rank.
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* @MEM_RDR: Registered SDR SDRAM
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* @MEM_DDR: Double data rate SDRAM
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* http://en.wikipedia.org/wiki/DDR_SDRAM
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* @MEM_RDDR: Registered Double data rate SDRAM
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* This is a variant of the DDR memories.
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* A registered memory has a buffer inside it, hiding
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* part of the memory details to the memory controller.
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* @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
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* @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
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* Those memories are labed as "PC2-" instead of "PC" to
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* differenciate from DDR.
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* @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
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* and JESD206.
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* Those memories are accessed per DIMM slot, and not by
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* a chip select signal.
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* @MEM_RDDR2: Registered DDR2 RAM
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* This is a variant of the DDR2 memories.
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* @MEM_XDR: Rambus XDR
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* It is an evolution of the original RAMBUS memories,
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* created to compete with DDR2. Weren't used on any
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* x86 arch, but cell_edac PPC memory controller uses it.
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* @MEM_DDR3: DDR3 RAM
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* @MEM_RDDR3: Registered DDR3 RAM
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* This is a variant of the DDR3 memories.
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*/
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enum mem_type {
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MEM_EMPTY = 0, /* Empty csrow */
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MEM_RESERVED, /* Reserved csrow type */
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MEM_UNKNOWN, /* Unknown csrow type */
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MEM_FPM, /* Fast page mode */
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MEM_EDO, /* Extended data out */
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MEM_BEDO, /* Burst Extended data out */
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MEM_SDR, /* Single data rate SDRAM */
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MEM_RDR, /* Registered single data rate SDRAM */
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MEM_DDR, /* Double data rate SDRAM */
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MEM_RDDR, /* Registered Double data rate SDRAM */
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MEM_RMBS, /* Rambus DRAM */
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MEM_DDR2, /* DDR2 RAM */
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MEM_FB_DDR2, /* fully buffered DDR2 */
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MEM_RDDR2, /* Registered DDR2 RAM */
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MEM_XDR, /* Rambus XDR */
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MEM_DDR3, /* DDR3 RAM */
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MEM_RDDR3, /* Registered DDR3 RAM */
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MEM_EMPTY = 0,
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MEM_RESERVED,
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MEM_UNKNOWN,
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MEM_FPM,
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MEM_EDO,
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MEM_BEDO,
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MEM_SDR,
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MEM_RDR,
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MEM_DDR,
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MEM_RDDR,
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MEM_RMBS,
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MEM_DDR2,
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MEM_FB_DDR2,
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MEM_RDDR2,
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MEM_XDR,
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MEM_DDR3,
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MEM_RDDR3,
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};
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#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
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@ -162,8 +201,9 @@ enum scrub_type {
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#define OP_OFFLINE 0x300
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/*
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* There are several things to be aware of that aren't at all obvious:
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* Concepts used at the EDAC subsystem
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*
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* There are several things to be aware of that aren't at all obvious:
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*
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* SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
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*
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@ -172,36 +212,61 @@ enum scrub_type {
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* creating a common ground for discussion, terms and their definitions
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* will be established.
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*
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* Memory devices: The individual chip on a memory stick. These devices
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* commonly output 4 and 8 bits each. Grouping several
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* of these in parallel provides 64 bits which is common
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* for a memory stick.
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* Memory devices: The individual DRAM chips on a memory stick. These
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* devices commonly output 4 and 8 bits each (x4, x8).
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* Grouping several of these in parallel provides the
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* number of bits that the memory controller expects:
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* typically 72 bits, in order to provide 64 bits +
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* 8 bits of ECC data.
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*
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* Memory Stick: A printed circuit board that aggregates multiple
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* memory devices in parallel. This is the atomic
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* memory component that is purchaseable by Joe consumer
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* and loaded into a memory socket.
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* memory devices in parallel. In general, this is the
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* Field Replaceable Unit (FRU) which gets replaced, in
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* the case of excessive errors. Most often it is also
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* called DIMM (Dual Inline Memory Module).
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*
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* Socket: A physical connector on the motherboard that accepts
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* a single memory stick.
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* Memory Socket: A physical connector on the motherboard that accepts
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* a single memory stick. Also called as "slot" on several
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* datasheets.
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*
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* Channel: Set of memory devices on a memory stick that must be
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* grouped in parallel with one or more additional
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* channels from other memory sticks. This parallel
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* grouping of the output from multiple channels are
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* necessary for the smallest granularity of memory access.
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* Some memory controllers are capable of single channel -
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* which means that memory sticks can be loaded
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* individually. Other memory controllers are only
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* capable of dual channel - which means that memory
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* sticks must be loaded as pairs (see "socket set").
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* Channel: A memory controller channel, responsible to communicate
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* with a group of DIMMs. Each channel has its own
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* independent control (command) and data bus, and can
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* be used independently or grouped with other channels.
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*
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* Chip-select row: All of the memory devices that are selected together.
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* for a single, minimum grain of memory access.
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* This selects all of the parallel memory devices across
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* all of the parallel channels. Common chip-select rows
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* for single channel are 64 bits, for dual channel 128
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* bits.
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* Branch: It is typically the highest hierarchy on a
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* Fully-Buffered DIMM memory controller.
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* Typically, it contains two channels.
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* Two channels at the same branch can be used in single
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* mode or in lockstep mode.
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* When lockstep is enabled, the cacheline is doubled,
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* but it generally brings some performance penalty.
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* Also, it is generally not possible to point to just one
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* memory stick when an error occurs, as the error
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* correction code is calculated using two DIMMs instead
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* of one. Due to that, it is capable of correcting more
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* errors than on single mode.
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*
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* Single-channel: The data accessed by the memory controller is contained
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* into one dimm only. E. g. if the data is 64 bits-wide,
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* the data flows to the CPU using one 64 bits parallel
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* access.
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* Typically used with SDR, DDR, DDR2 and DDR3 memories.
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* FB-DIMM and RAMBUS use a different concept for channel,
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* so this concept doesn't apply there.
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*
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* Double-channel: The data size accessed by the memory controller is
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* interlaced into two dimms, accessed at the same time.
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* E. g. if the DIMM is 64 bits-wide (72 bits with ECC),
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* the data flows to the CPU using a 128 bits parallel
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* access.
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*
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* Chip-select row: This is the name of the DRAM signal used to select the
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* DRAM ranks to be accessed. Common chip-select rows for
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* single channel are 64 bits, for dual channel 128 bits.
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* It may not be visible by the memory controller, as some
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* DIMM types have a memory buffer that can hide direct
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* access to it from the Memory Controller.
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*
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* Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
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* Motherboards commonly drive two chip-select pins to
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@ -214,8 +279,8 @@ enum scrub_type {
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*
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* Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
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* A double-sided stick has two chip-select rows which
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* access different sets of memory devices. The two
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* rows cannot be accessed concurrently. "Double-sided"
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* access different sets of memory devices. The two
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* rows cannot be accessed concurrently. "Double-sided"
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* is irrespective of the memory devices being mounted
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* on both sides of the memory stick.
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*
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