drm/amd/display: Enable 3 plane for DCN 3.0 and 3.02
[WHY&HOW] Increase num of bottom planes to 2. Note that DCN 3.03 is left out since it has max 2 planes. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2602,9 +2602,9 @@ static bool dcn30_resource_construct(
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dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
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dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
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dc->caps.max_slave_planes = 1;
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dc->caps.max_slave_yuv_planes = 1;
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dc->caps.max_slave_rgb_planes = 1;
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dc->caps.max_slave_planes = 2;
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dc->caps.max_slave_yuv_planes = 2;
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dc->caps.max_slave_rgb_planes = 2;
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dc->caps.post_blend_color_processing = true;
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dc->caps.force_dp_tps4_for_cp2520 = true;
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dc->caps.extended_aux_timeout_support = true;
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@ -1219,9 +1219,9 @@ static bool dcn302_resource_construct(
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/* total size = mall per channel * num channels * 1024 * 1024 */
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dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
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dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
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dc->caps.max_slave_planes = 1;
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dc->caps.max_slave_yuv_planes = 1;
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dc->caps.max_slave_rgb_planes = 1;
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dc->caps.max_slave_planes = 2;
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dc->caps.max_slave_yuv_planes = 2;
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dc->caps.max_slave_rgb_planes = 2;
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dc->caps.post_blend_color_processing = true;
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dc->caps.force_dp_tps4_for_cp2520 = true;
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dc->caps.extended_aux_timeout_support = true;
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