Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson: "Driver updates for ARM SoCs: Reset subsystem, merged through arm-soc by tradition: - Make bool drivers explicitly non-modular - New support for i.MX7 and Arria10 reset controllers PATA driver for Palmchip BK371 (acked by Tejun) Power domain drivers for i.MX (GPC, GPCv2) - Moved out of mach-imx for GPC - Bunch of tweaks, fixes, etc PMC support for Tegra186 SoC detection support for Renesas RZ/G1H and RZ/G1N Move Tegra flow controller driver from mach directory to drivers/soc - (Power management / CPU power driver) Misc smaller tweaks for other platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits) soc: pm-domain: Fix the mangled urls soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0 soc: renesas: rcar-sysc: Add support for fixing up power area tables soc: renesas: Register SoC device early soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible soc: imx: gpc: add defines for domain index soc: imx: Add GPCv2 power gating driver dt-bindings: Add GPCv2 power gating driver ARM/clk: move the ICST library to drivers/clk ARM: plat-versatile: remove stale clock header ARM: keystone: Drop PM domain support for k2g soc: ti: Add ti_sci_pm_domains driver dt-bindings: Add TI SCI PM Domains PM / Domains: Do not check if simple providers have phandle cells PM / Domains: Add generic data pointer to genpd data struct soc/tegra: Add initial flowctrl support for Tegra132/210 soc/tegra: flowctrl: Add basic platform driver soc/tegra: Move Tegra flowctrl driver ARM: tegra: Remove unnecessary inclusion of flowctrl header ...
This commit is contained in:
Linus Torvalds
90
include/dt-bindings/genpd/k2g.h
Normal file
90
include/dt-bindings/genpd/k2g.h
Normal file
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* TI K2G SoC Device definitions
|
||||
*
|
||||
* Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_GENPD_K2G_H
|
||||
#define _DT_BINDINGS_GENPD_K2G_H
|
||||
|
||||
/* Documented in http://processors.wiki.ti.com/index.php/TISCI */
|
||||
|
||||
#define K2G_DEV_PMMC0 0x0000
|
||||
#define K2G_DEV_MLB0 0x0001
|
||||
#define K2G_DEV_DSS0 0x0002
|
||||
#define K2G_DEV_MCBSP0 0x0003
|
||||
#define K2G_DEV_MCASP0 0x0004
|
||||
#define K2G_DEV_MCASP1 0x0005
|
||||
#define K2G_DEV_MCASP2 0x0006
|
||||
#define K2G_DEV_DCAN0 0x0008
|
||||
#define K2G_DEV_DCAN1 0x0009
|
||||
#define K2G_DEV_EMIF0 0x000a
|
||||
#define K2G_DEV_MMCHS0 0x000b
|
||||
#define K2G_DEV_MMCHS1 0x000c
|
||||
#define K2G_DEV_GPMC0 0x000d
|
||||
#define K2G_DEV_ELM0 0x000e
|
||||
#define K2G_DEV_SPI0 0x0010
|
||||
#define K2G_DEV_SPI1 0x0011
|
||||
#define K2G_DEV_SPI2 0x0012
|
||||
#define K2G_DEV_SPI3 0x0013
|
||||
#define K2G_DEV_ICSS0 0x0014
|
||||
#define K2G_DEV_ICSS1 0x0015
|
||||
#define K2G_DEV_USB0 0x0016
|
||||
#define K2G_DEV_USB1 0x0017
|
||||
#define K2G_DEV_NSS0 0x0018
|
||||
#define K2G_DEV_PCIE0 0x0019
|
||||
#define K2G_DEV_GPIO0 0x001b
|
||||
#define K2G_DEV_GPIO1 0x001c
|
||||
#define K2G_DEV_TIMER64_0 0x001d
|
||||
#define K2G_DEV_TIMER64_1 0x001e
|
||||
#define K2G_DEV_TIMER64_2 0x001f
|
||||
#define K2G_DEV_TIMER64_3 0x0020
|
||||
#define K2G_DEV_TIMER64_4 0x0021
|
||||
#define K2G_DEV_TIMER64_5 0x0022
|
||||
#define K2G_DEV_TIMER64_6 0x0023
|
||||
#define K2G_DEV_MSGMGR0 0x0025
|
||||
#define K2G_DEV_BOOTCFG0 0x0026
|
||||
#define K2G_DEV_ARM_BOOTROM0 0x0027
|
||||
#define K2G_DEV_DSP_BOOTROM0 0x0029
|
||||
#define K2G_DEV_DEBUGSS0 0x002b
|
||||
#define K2G_DEV_UART0 0x002c
|
||||
#define K2G_DEV_UART1 0x002d
|
||||
#define K2G_DEV_UART2 0x002e
|
||||
#define K2G_DEV_EHRPWM0 0x002f
|
||||
#define K2G_DEV_EHRPWM1 0x0030
|
||||
#define K2G_DEV_EHRPWM2 0x0031
|
||||
#define K2G_DEV_EHRPWM3 0x0032
|
||||
#define K2G_DEV_EHRPWM4 0x0033
|
||||
#define K2G_DEV_EHRPWM5 0x0034
|
||||
#define K2G_DEV_EQEP0 0x0035
|
||||
#define K2G_DEV_EQEP1 0x0036
|
||||
#define K2G_DEV_EQEP2 0x0037
|
||||
#define K2G_DEV_ECAP0 0x0038
|
||||
#define K2G_DEV_ECAP1 0x0039
|
||||
#define K2G_DEV_I2C0 0x003a
|
||||
#define K2G_DEV_I2C1 0x003b
|
||||
#define K2G_DEV_I2C2 0x003c
|
||||
#define K2G_DEV_EDMA0 0x003f
|
||||
#define K2G_DEV_SEMAPHORE0 0x0040
|
||||
#define K2G_DEV_INTC0 0x0041
|
||||
#define K2G_DEV_GIC0 0x0042
|
||||
#define K2G_DEV_QSPI0 0x0043
|
||||
#define K2G_DEV_ARM_64B_COUNTER0 0x0044
|
||||
#define K2G_DEV_TETRIS0 0x0045
|
||||
#define K2G_DEV_CGEM0 0x0046
|
||||
#define K2G_DEV_MSMC0 0x0047
|
||||
#define K2G_DEV_CBASS0 0x0049
|
||||
#define K2G_DEV_BOARD0 0x004c
|
||||
#define K2G_DEV_EDMA1 0x004f
|
||||
|
||||
#endif
|
||||
16
include/dt-bindings/power/imx7-power.h
Normal file
16
include/dt-bindings/power/imx7-power.h
Normal file
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Impinj
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_IMX7_POWER_H__
|
||||
#define __DT_BINDINGS_IMX7_POWER_H__
|
||||
|
||||
#define IMX7_POWER_DOMAIN_MIPI_PHY 0
|
||||
#define IMX7_POWER_DOMAIN_PCIE_PHY 1
|
||||
#define IMX7_POWER_DOMAIN_USB_HSIC_PHY 2
|
||||
|
||||
#endif
|
||||
@@ -33,7 +33,7 @@
|
||||
#define R8A7795_PD_CA53_SCU 21
|
||||
#define R8A7795_PD_3DG_E 22
|
||||
#define R8A7795_PD_A3IR 24
|
||||
#define R8A7795_PD_A2VC0 25
|
||||
#define R8A7795_PD_A2VC0 25 /* ES1.x only */
|
||||
#define R8A7795_PD_A2VC1 26
|
||||
|
||||
/* Always-on power area */
|
||||
|
||||
33
include/dt-bindings/reset/altr,rst-mgr-a10sr.h
Normal file
33
include/dt-bindings/reset/altr,rst-mgr-a10sr.h
Normal file
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright Intel Corporation (C) 2017. All Rights Reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Reset binding definitions for Altera Arria10 MAX5 System Resource Chip
|
||||
*
|
||||
* Adapted from altr,rst-mgr-a10.h
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H
|
||||
#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H
|
||||
|
||||
/* Peripheral PHY resets */
|
||||
#define A10SR_RESET_ENET_HPS 0
|
||||
#define A10SR_RESET_PCIE 1
|
||||
#define A10SR_RESET_FILE 2
|
||||
#define A10SR_RESET_BQSPI 3
|
||||
#define A10SR_RESET_USB 4
|
||||
|
||||
#define A10SR_RESET_NUM 5
|
||||
|
||||
#endif
|
||||
62
include/dt-bindings/reset/imx7-reset.h
Normal file
62
include/dt-bindings/reset/imx7-reset.h
Normal file
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Impinj, Inc.
|
||||
*
|
||||
* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDING_RESET_IMX7_H
|
||||
#define DT_BINDING_RESET_IMX7_H
|
||||
|
||||
#define IMX7_RESET_A7_CORE_POR_RESET0 0
|
||||
#define IMX7_RESET_A7_CORE_POR_RESET1 1
|
||||
#define IMX7_RESET_A7_CORE_RESET0 2
|
||||
#define IMX7_RESET_A7_CORE_RESET1 3
|
||||
#define IMX7_RESET_A7_DBG_RESET0 4
|
||||
#define IMX7_RESET_A7_DBG_RESET1 5
|
||||
#define IMX7_RESET_A7_ETM_RESET0 6
|
||||
#define IMX7_RESET_A7_ETM_RESET1 7
|
||||
#define IMX7_RESET_A7_SOC_DBG_RESET 8
|
||||
#define IMX7_RESET_A7_L2RESET 9
|
||||
#define IMX7_RESET_SW_M4C_RST 10
|
||||
#define IMX7_RESET_SW_M4P_RST 11
|
||||
#define IMX7_RESET_EIM_RST 12
|
||||
#define IMX7_RESET_HSICPHY_PORT_RST 13
|
||||
#define IMX7_RESET_USBPHY1_POR 14
|
||||
#define IMX7_RESET_USBPHY1_PORT_RST 15
|
||||
#define IMX7_RESET_USBPHY2_POR 16
|
||||
#define IMX7_RESET_USBPHY2_PORT_RST 17
|
||||
#define IMX7_RESET_MIPI_PHY_MRST 18
|
||||
#define IMX7_RESET_MIPI_PHY_SRST 19
|
||||
|
||||
/*
|
||||
* IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN
|
||||
* and PCIEPHY_G_RST
|
||||
*/
|
||||
#define IMX7_RESET_PCIEPHY 20
|
||||
#define IMX7_RESET_PCIEPHY_PERST 21
|
||||
|
||||
/*
|
||||
* IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it
|
||||
* can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht
|
||||
* of as one
|
||||
*/
|
||||
#define IMX7_RESET_PCIE_CTRL_APPS_EN 22
|
||||
#define IMX7_RESET_DDRC_PRST 23
|
||||
#define IMX7_RESET_DDRC_CORE_RST 24
|
||||
|
||||
#define IMX7_RESET_NUM 25
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user