Merge tag 'kvm-3.10-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm updates from Gleb Natapov:
"Highlights of the updates are:
general:
- new emulated device API
- legacy device assignment is now optional
- irqfd interface is more generic and can be shared between arches
x86:
- VMCS shadow support and other nested VMX improvements
- APIC virtualization and Posted Interrupt hardware support
- Optimize mmio spte zapping
ppc:
- BookE: in-kernel MPIC emulation with irqfd support
- Book3S: in-kernel XICS emulation (incomplete)
- Book3S: HV: migration fixes
- BookE: more debug support preparation
- BookE: e6500 support
ARM:
- reworking of Hyp idmaps
s390:
- ioeventfd for virtio-ccw
And many other bug fixes, cleanups and improvements"
* tag 'kvm-3.10-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (204 commits)
kvm: Add compat_ioctl for device control API
KVM: x86: Account for failing enable_irq_window for NMI window request
KVM: PPC: Book3S: Add API for in-kernel XICS emulation
kvm/ppc/mpic: fix missing unlock in set_base_addr()
kvm/ppc: Hold srcu lock when calling kvm_io_bus_read/write
kvm/ppc/mpic: remove users
kvm/ppc/mpic: fix mmio region lists when multiple guests used
kvm/ppc/mpic: remove default routes from documentation
kvm: KVM_CAP_IOMMU only available with device assignment
ARM: KVM: iterate over all CPUs for CPU compatibility check
KVM: ARM: Fix spelling in error message
ARM: KVM: define KVM_ARM_MAX_VCPUS unconditionally
KVM: ARM: Fix API documentation for ONE_REG encoding
ARM: KVM: promote vfp_host pointer to generic host cpu context
ARM: KVM: add architecture specific hook for capabilities
ARM: KVM: perform HYP initilization for hotplugged CPUs
ARM: KVM: switch to a dual-step HYP init code
ARM: KVM: rework HYP page table freeing
ARM: KVM: enforce maximum size for identity mapped code
ARM: KVM: move to a KVM provided HYP idmap
...
This commit is contained in:
Linus Torvalds
@@ -25,6 +25,8 @@
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/* Select powerpc specific features in <linux/kvm.h> */
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#define __KVM_HAVE_SPAPR_TCE
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#define __KVM_HAVE_PPC_SMT
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#define __KVM_HAVE_IRQCHIP
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#define __KVM_HAVE_IRQ_LINE
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struct kvm_regs {
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__u64 pc;
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@@ -272,8 +274,31 @@ struct kvm_debug_exit_arch {
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/* for KVM_SET_GUEST_DEBUG */
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struct kvm_guest_debug_arch {
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struct {
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/* H/W breakpoint/watchpoint address */
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__u64 addr;
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/*
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* Type denotes h/w breakpoint, read watchpoint, write
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* watchpoint or watchpoint (both read and write).
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*/
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#define KVMPPC_DEBUG_NONE 0x0
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#define KVMPPC_DEBUG_BREAKPOINT (1UL << 1)
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#define KVMPPC_DEBUG_WATCH_WRITE (1UL << 2)
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#define KVMPPC_DEBUG_WATCH_READ (1UL << 3)
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__u32 type;
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__u32 reserved;
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} bp[16];
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};
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/* Debug related defines */
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/*
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* kvm_guest_debug->control is a 32 bit field. The lower 16 bits are generic
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* and upper 16 bits are architecture specific. Architecture specific defines
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* that ioctl is for setting hardware breakpoint or software breakpoint.
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*/
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#define KVM_GUESTDBG_USE_SW_BP 0x00010000
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#define KVM_GUESTDBG_USE_HW_BP 0x00020000
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/* definition of registers in kvm_run */
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struct kvm_sync_regs {
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};
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@@ -299,6 +324,12 @@ struct kvm_allocate_rma {
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__u64 rma_size;
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};
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/* for KVM_CAP_PPC_RTAS */
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struct kvm_rtas_token_args {
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char name[120];
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__u64 token; /* Use a token of 0 to undefine a mapping */
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};
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struct kvm_book3e_206_tlb_entry {
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__u32 mas8;
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__u32 mas1;
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@@ -359,6 +390,26 @@ struct kvm_get_htab_header {
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__u16 n_invalid;
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};
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/* Per-vcpu XICS interrupt controller state */
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#define KVM_REG_PPC_ICP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
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#define KVM_REG_PPC_ICP_CPPR_SHIFT 56 /* current proc priority */
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#define KVM_REG_PPC_ICP_CPPR_MASK 0xff
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#define KVM_REG_PPC_ICP_XISR_SHIFT 32 /* interrupt status field */
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#define KVM_REG_PPC_ICP_XISR_MASK 0xffffff
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#define KVM_REG_PPC_ICP_MFRR_SHIFT 24 /* pending IPI priority */
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#define KVM_REG_PPC_ICP_MFRR_MASK 0xff
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#define KVM_REG_PPC_ICP_PPRI_SHIFT 16 /* pending irq priority */
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#define KVM_REG_PPC_ICP_PPRI_MASK 0xff
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/* Device control API: PPC-specific devices */
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#define KVM_DEV_MPIC_GRP_MISC 1
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#define KVM_DEV_MPIC_BASE_ADDR 0 /* 64-bit */
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#define KVM_DEV_MPIC_GRP_REGISTER 2 /* 32-bit */
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#define KVM_DEV_MPIC_GRP_IRQ_ACTIVE 3 /* 32-bit */
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/* One-Reg API: PPC-specific registers */
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#define KVM_REG_PPC_HIOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1)
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#define KVM_REG_PPC_IAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2)
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#define KVM_REG_PPC_IAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3)
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@@ -417,4 +468,47 @@ struct kvm_get_htab_header {
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#define KVM_REG_PPC_EPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85)
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#define KVM_REG_PPC_EPR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x86)
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/* Timer Status Register OR/CLEAR interface */
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#define KVM_REG_PPC_OR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x87)
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#define KVM_REG_PPC_CLEAR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88)
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#define KVM_REG_PPC_TCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89)
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#define KVM_REG_PPC_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a)
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/* Debugging: Special instruction for software breakpoint */
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#define KVM_REG_PPC_DEBUG_INST (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8b)
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/* MMU registers */
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#define KVM_REG_PPC_MAS0 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8c)
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#define KVM_REG_PPC_MAS1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8d)
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#define KVM_REG_PPC_MAS2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8e)
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#define KVM_REG_PPC_MAS7_3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8f)
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#define KVM_REG_PPC_MAS4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x90)
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#define KVM_REG_PPC_MAS6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x91)
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#define KVM_REG_PPC_MMUCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x92)
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/*
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* TLBnCFG fields TLBnCFG_N_ENTRY and TLBnCFG_ASSOC can be changed only using
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* KVM_CAP_SW_TLB ioctl
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*/
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#define KVM_REG_PPC_TLB0CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x93)
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#define KVM_REG_PPC_TLB1CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x94)
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#define KVM_REG_PPC_TLB2CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x95)
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#define KVM_REG_PPC_TLB3CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x96)
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#define KVM_REG_PPC_TLB0PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x97)
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#define KVM_REG_PPC_TLB1PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x98)
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#define KVM_REG_PPC_TLB2PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x99)
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#define KVM_REG_PPC_TLB3PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a)
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#define KVM_REG_PPC_EPTCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9b)
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/* PPC64 eXternal Interrupt Controller Specification */
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#define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */
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/* Layout of 64-bit source attribute values */
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#define KVM_XICS_DESTINATION_SHIFT 0
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#define KVM_XICS_DESTINATION_MASK 0xffffffffULL
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#define KVM_XICS_PRIORITY_SHIFT 32
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#define KVM_XICS_PRIORITY_MASK 0xff
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#define KVM_XICS_LEVEL_SENSITIVE (1ULL << 40)
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#define KVM_XICS_MASKED (1ULL << 41)
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#define KVM_XICS_PENDING (1ULL << 42)
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#endif /* __LINUX_KVM_POWERPC_H */
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