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drm/amd/display: Fix applying surface to underlay pipe

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1. Locking all pipes before doing any changes
2. Applying surface for both top and bottom pipes

Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Leon Elazar 2017-03-17 12:02:58 -04:00 committed by Alex Deucher
parent 0702a01f97
commit 00f0201999
1 changed files with 26 additions and 16 deletions
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42
drivers/gpu/drm/amd/display/dc/core/dc.c
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@ -1331,9 +1331,34 @@ void dc_update_surfaces_and_stream(struct dc *dc,
if (!surface_count) /* reset */ if (!surface_count) /* reset */
core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context); core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
/* Lock pipes for provided surfaces */
for (i = 0; i < surface_count; i++) { for (i = 0; i < surface_count; i++) {
struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface); struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (pipe_ctx->surface != surface)
continue;
if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
core_dc->hwss.pipe_control_lock(
core_dc,
pipe_ctx,
true);
}
}
}
/* Perform requested Updates */
for (i = 0; i < surface_count; i++) {
struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
if (update_type >= UPDATE_TYPE_MED) {
core_dc->hwss.apply_ctx_for_surface(
core_dc, surface, context);
context_timing_trace(dc, &context->res_ctx);
}
for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
struct pipe_ctx *cur_pipe_ctx; struct pipe_ctx *cur_pipe_ctx;
@ -1342,22 +1367,6 @@ void dc_update_surfaces_and_stream(struct dc *dc,
if (pipe_ctx->surface != surface) if (pipe_ctx->surface != surface)
continue; continue;
if (update_type >= UPDATE_TYPE_MED) {
/* only apply for top pipe */
if (!pipe_ctx->top_pipe) {
core_dc->hwss.apply_ctx_for_surface(core_dc,
surface, context);
context_timing_trace(dc, &context->res_ctx);
}
}
if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
core_dc->hwss.pipe_control_lock(
core_dc,
pipe_ctx,
true);
}
if (srf_updates[i].flip_addr) if (srf_updates[i].flip_addr)
core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
@ -1387,6 +1396,7 @@ void dc_update_surfaces_and_stream(struct dc *dc,
} }
} }
/* Unlock pipes */
for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) { for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];