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[POWERPC] Remove barriers from the SLB shadow buffer update

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After talking to an IBM POWER hypervisor (PHYP) design and development
guy, there seems to be no need for memory barriers when updating the SLB
shadow buffer provided we only update it from the current CPU, which we
do.

Also, these guys see no need in the future for these barriers.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Michael Neuling
2007-08-24 16:58:37 +10:00
committed by Paul Mackerras
parent 61a564fd2e
commit 00efee7d5d
2 changed files with 6 additions and 8 deletions
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8
arch/powerpc/kernel/entry_64.S
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@@ -385,15 +385,15 @@ BEGIN_FTR_SECTION
oris r0,r6,(SLB_ESID_V)@h
ori r0,r0,(SLB_NUM_BOLTED-1)@l
/* Update the last bolted SLB */
/* Update the last bolted SLB. No write barriers are needed
* here, provided we only update the current CPU's SLB shadow
* buffer.
*/
ld r9,PACA_SLBSHADOWPTR(r13)
li r12,0
std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
eieio
std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
eieio
std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
eieio
slbie r6
slbie r6 /* Workaround POWER5 < DD2.1 issue */