forked from Minki/linux
[SCSI] mvsas: fix phy sas address
The phy sas address is showing wrongly (wrong endianness). Fix up the endian transforms to make this correct. Signed-off-by: Ke Wei <kewei@marvell.com> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
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11
drivers/scsi/mvsas.c
Normal file → Executable file
11
drivers/scsi/mvsas.c
Normal file → Executable file
@ -40,7 +40,7 @@
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#include <asm/io.h>
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#define DRV_NAME "mvsas"
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#define DRV_VERSION "0.5"
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#define DRV_VERSION "0.5.1"
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#define _MV_DUMP 0
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#define MVS_DISABLE_NVRAM
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#define MVS_DISABLE_MSI
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@ -1005,7 +1005,7 @@ err_out:
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return rc;
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#else
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/* FIXME , For SAS target mode */
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memcpy(buf, "\x00\x00\xab\x11\x30\x04\x05\x50", 8);
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memcpy(buf, "\x50\x05\x04\x30\x11\xab\x00\x00", 8);
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return 0;
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#endif
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}
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@ -1330,7 +1330,7 @@ static int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
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mvs_hba_cq_dump(mvi);
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if (unlikely(rx_desc & RXQ_DONE))
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if (likely(rx_desc & RXQ_DONE))
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mvs_slot_complete(mvi, rx_desc);
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if (rx_desc & RXQ_ATTN) {
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attn = true;
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@ -2720,9 +2720,8 @@ static int __devinit mvs_hw_init(struct mvs_info *mvi)
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msleep(100);
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/* init and reset phys */
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for (i = 0; i < mvi->chip->n_phy; i++) {
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/* FIXME: is this the correct dword order? */
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u32 lo = *((u32 *)&mvi->sas_addr[0]);
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u32 hi = *((u32 *)&mvi->sas_addr[4]);
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u32 lo = be32_to_cpu(*(u32 *)&mvi->sas_addr[4]);
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u32 hi = be32_to_cpu(*(u32 *)&mvi->sas_addr[0]);
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mvs_detect_porttype(mvi, i);
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