staging: wilc1000: modified code comments as per linux coding style
Cleanup patch to follow the comments style as per the Linux coding style. Signed-off-by: Ajay Singh <ajay.kathat@microchip.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ajay Singh
Greg Kroah-Hartman
parent
10660003be
commit
00c2903b16
@ -422,9 +422,9 @@ static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
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return N_FAIL;
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}
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/**
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/*
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* Command/Control response
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**/
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*/
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if (cmd == CMD_RESET ||
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cmd == CMD_TERMINATE ||
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cmd == CMD_REPEAT) {
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@ -443,9 +443,9 @@ static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
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return N_FAIL;
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}
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/**
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/*
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* State response
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**/
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*/
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rsp = rb[rix++];
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if (rsp != 0x00) {
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dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
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@ -458,12 +458,15 @@ static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
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int retry;
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/* u16 crc1, crc2; */
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u8 crc[2];
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/**
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/*
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* Data Respnose header
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**/
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*/
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retry = 100;
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do {
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/* ensure there is room in buffer later to read data and crc */
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/*
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* ensure there is room in buffer later
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* to read data and crc
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*/
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if (rix < len2) {
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rsp = rb[rix++];
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} else {
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@ -481,9 +484,9 @@ static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
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}
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if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
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/**
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/*
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* Read bytes
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**/
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*/
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if ((rix + 3) < len2) {
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b[0] = rb[rix++];
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b[1] = rb[rix++];
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@ -496,9 +499,9 @@ static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
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}
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if (!g_spi.crc_off) {
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/**
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/*
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* Read Crc
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**/
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*/
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if ((rix + 1) < len2) {
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crc[0] = rb[rix++];
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crc[1] = rb[rix++];
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@ -524,18 +527,18 @@ static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
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else
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nbytes = DATA_PKT_SZ - ix;
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/**
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/*
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* Read bytes
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**/
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*/
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if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
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dev_err(&spi->dev, "Failed data block read, bus error...\n");
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result = N_FAIL;
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goto _error_;
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}
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/**
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/*
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* Read Crc
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**/
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*/
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if (!g_spi.crc_off) {
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if (wilc_spi_rx(wilc, crc, 2)) {
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dev_err(&spi->dev, "Failed data block crc read, bus error...\n");
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@ -548,7 +551,10 @@ static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
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sz -= nbytes;
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}
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/* if any data in left unread, then read the rest using normal DMA code.*/
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/*
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* if any data in left unread,
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* then read the rest using normal DMA code.
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*/
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while (sz > 0) {
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int nbytes;
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@ -557,14 +563,14 @@ static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
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else
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nbytes = DATA_PKT_SZ;
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/**
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/*
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* read data response only on the next DMA cycles not
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* the first DMA since data response header is already
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* handled above for the first DMA.
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**/
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/**
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*/
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/*
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* Data Respnose header
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**/
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*/
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retry = 10;
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do {
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if (wilc_spi_rx(wilc, &rsp, 1)) {
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@ -579,18 +585,18 @@ static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
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if (result == N_FAIL)
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break;
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/**
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/*
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* Read bytes
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**/
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*/
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if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
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dev_err(&spi->dev, "Failed data block read, bus error...\n");
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result = N_FAIL;
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break;
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}
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/**
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/*
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* Read Crc
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**/
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*/
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if (!g_spi.crc_off) {
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if (wilc_spi_rx(wilc, crc, 2)) {
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dev_err(&spi->dev, "Failed data block crc read, bus error...\n");
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@ -616,9 +622,9 @@ static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
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u8 cmd, order, crc[2] = {0};
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/* u8 rsp; */
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/**
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* Data
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**/
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/*
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* Data
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*/
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ix = 0;
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do {
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if (sz <= DATA_PKT_SZ)
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@ -626,9 +632,9 @@ static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
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else
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nbytes = DATA_PKT_SZ;
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/**
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* Write command
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**/
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/*
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* Write command
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*/
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cmd = 0xf0;
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if (ix == 0) {
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if (sz <= DATA_PKT_SZ)
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@ -650,9 +656,9 @@ static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
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break;
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}
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/**
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* Write data
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**/
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/*
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* Write data
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*/
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if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
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dev_err(&spi->dev,
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"Failed data block write, bus error...\n");
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@ -660,9 +666,9 @@ static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
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break;
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}
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/**
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* Write Crc
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**/
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/*
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* Write Crc
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*/
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if (!g_spi.crc_off) {
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if (wilc_spi_tx(wilc, crc, 2)) {
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dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
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@ -671,9 +677,9 @@ static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
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}
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}
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/**
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* No need to wait for response
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**/
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/*
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* No need to wait for response
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*/
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ix += nbytes;
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sz -= nbytes;
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} while (sz);
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@ -733,7 +739,7 @@ static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
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data = cpu_to_le32(data);
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if (addr < 0x30) {
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/* Clockless register*/
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/* Clockless register */
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cmd = CMD_INTERNAL_WRITE;
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clockless = 1;
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}
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@ -751,9 +757,9 @@ static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
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int result;
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u8 cmd = CMD_DMA_EXT_WRITE;
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/**
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* has to be greated than 4
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**/
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/*
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* has to be greated than 4
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*/
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if (size <= 4)
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return 0;
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@ -764,9 +770,9 @@ static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
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return 0;
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}
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/**
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* Data
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**/
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/*
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* Data
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*/
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result = spi_data_write(wilc, buf, size);
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if (result != N_OK)
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dev_err(&spi->dev, "Failed block data write...\n");
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@ -783,7 +789,7 @@ static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
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if (addr < 0x30) {
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/* dev_err(&spi->dev, "***** read addr %d\n\n", addr); */
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/* Clockless register*/
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/* Clockless register */
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cmd = CMD_INTERNAL_READ;
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clockless = 1;
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}
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@ -825,9 +831,9 @@ static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
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static int _wilc_spi_deinit(struct wilc *wilc)
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{
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/**
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* TODO:
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**/
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/*
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* TODO:
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*/
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return 1;
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}
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@ -849,15 +855,19 @@ static int wilc_spi_init(struct wilc *wilc, bool resume)
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memset(&g_spi, 0, sizeof(struct wilc_spi));
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/**
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* configure protocol
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**/
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/*
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* configure protocol
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*/
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g_spi.crc_off = 0;
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/* TODO: We can remove the CRC trials if there is a definite way to reset */
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/*
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* TODO: We can remove the CRC trials if there is a definite
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* way to reset
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*/
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/* the SPI to it's initial value. */
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if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®)) {
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/* Read failed. Try with CRC off. This might happen when module
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/*
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* Read failed. Try with CRC off. This might happen when module
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* is removed but chip isn't reset
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*/
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g_spi.crc_off = 1;
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@ -870,7 +880,7 @@ static int wilc_spi_init(struct wilc *wilc, bool resume)
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}
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}
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if (g_spi.crc_off == 0) {
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reg &= ~0xc; /* disable crc checking */
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reg &= ~0xc; /* disable crc checking */
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reg &= ~0x70;
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reg |= (0x5 << 4);
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if (!spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg)) {
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@ -880,9 +890,9 @@ static int wilc_spi_init(struct wilc *wilc, bool resume)
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g_spi.crc_off = 1;
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}
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/**
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* make sure can read back chip id correctly
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**/
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/*
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* make sure can read back chip id correctly
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*/
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if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
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dev_err(&spi->dev, "Fail cmd read chip id...\n");
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return 0;
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@ -994,7 +1004,10 @@ static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
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ret = 1;
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for (i = 0; i < g_spi.nint; i++) {
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/* No matter what you write 1 or 0, it will clear interrupt. */
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/*
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* No matter what you write 1 or 0,
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* it will clear interrupt.
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*/
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if (flags & 1)
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ret = wilc_spi_write_reg(wilc, 0x10c8 + i * 4, 1);
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if (!ret)
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@ -1036,9 +1049,9 @@ static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
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}
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if ((val & EN_VMM) == EN_VMM) {
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/**
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* enable vmm transfer.
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**/
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/*
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* enable vmm transfer.
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*/
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ret = wilc_spi_write_reg(wilc,
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WILC_VMM_CORE_CTL, 1);
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if (!ret) {
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@ -1065,9 +1078,9 @@ static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
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g_spi.nint = nint;
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/**
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* interrupt pin mux select
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**/
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/*
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* interrupt pin mux select
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*/
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ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®);
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if (!ret) {
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dev_err(&spi->dev, "Failed read reg (%08x)...\n",
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@ -1082,9 +1095,9 @@ static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
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return 0;
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}
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/**
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* interrupt enable
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**/
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/*
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* interrupt enable
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*/
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ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®);
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if (!ret) {
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dev_err(&spi->dev, "Failed read reg (%08x)...\n",
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