forked from Minki/linux
nds32: Kernel booting and initialization
This patch includes the kernel startup code. It can get dtb pointer passed from bootloader. It will create a temp mapping by tlb instructions at beginning and goto start_kernel. Signed-off-by: Vincent Chen <vincentc@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Greentime Hu
parent
e1d82de681
commit
001d953ede
188
arch/nds32/kernel/head.S
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188
arch/nds32/kernel/head.S
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@ -0,0 +1,188 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2005-2017 Andes Technology Corporation
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/sizes.h>
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#include <asm/thread_info.h>
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define OF_DT_MAGIC 0xd00dfeed
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#else
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#define OF_DT_MAGIC 0xedfe0dd0
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#endif
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.globl swapper_pg_dir
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.equ swapper_pg_dir, TEXTADDR - 0x4000
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/*
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* Kernel startup entry point.
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*/
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.section ".head.text", "ax"
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.type _stext, %function
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ENTRY(_stext)
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setgie.d ! Disable interrupt
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isb
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/*
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* Disable I/D-cache and enable it at a proper time
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*/
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mfsr $r0, $mr8
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li $r1, #~(CACHE_CTL_mskIC_EN|CACHE_CTL_mskDC_EN)
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and $r0, $r0, $r1
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mtsr $r0, $mr8
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/*
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* Process device tree blob
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*/
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andi $r0,$r2,#0x3
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li $r10, 0
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bne $r0, $r10, _nodtb
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lwi $r0, [$r2]
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li $r1, OF_DT_MAGIC
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bne $r0, $r1, _nodtb
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move $r10, $r2
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_nodtb:
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/*
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* Create a temporary mapping area for booting, before start_kernel
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*/
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sethi $r4, hi20(swapper_pg_dir)
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li $p0, (PAGE_OFFSET - PHYS_OFFSET)
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sub $r4, $r4, $p0
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tlbop FlushAll ! invalidate TLB\n"
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isb
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mtsr $r4, $L1_PPTB ! load page table pointer\n"
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/* set NTC0 cacheable/writeback, mutliple page size in use */
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mfsr $r3, $MMU_CTL
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li $r0, #~MMU_CTL_mskNTC0
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and $r3, $r3, $r0
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#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
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ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << MMU_CTL_offNTC0))
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#else
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ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << MMU_CTL_offNTC0)|MMU_CTL_D8KB)
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#endif
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#ifdef CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS
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li $r0, #MMU_CTL_UNA
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or $r3, $r3, $r0
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#endif
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mtsr $r3, $MMU_CTL
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isb
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/* set page size and size of kernel image */
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mfsr $r0, $MMU_CFG
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srli $r3, $r0, MMU_CFG_offfEPSZ
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zeb $r3, $r3
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bnez $r3, _extra_page_size_support
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#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
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li $r5, #SZ_4K ! Use 4KB page size
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#else
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li $r5, #SZ_8K ! Use 8KB page size
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li $r3, #1
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#endif
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mtsr $r3, $TLB_MISC
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b _image_size_check
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_extra_page_size_support: ! Use epzs pages size
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clz $r6, $r3
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subri $r2, $r6, #31
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li $r3, #1
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sll $r3, $r3, $r2
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/* MMU_CFG.EPSZ value -> meaning */
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mul $r5, $r3, $r3
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slli $r5, $r5, #14
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/* MMU_CFG.EPSZ -> TLB_MISC.ACC_PSZ */
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addi $r3, $r2, #0x2
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mtsr $r3, $TLB_MISC
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_image_size_check:
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/* calculate the image maximum size accepted by TLB config */
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andi $r6, $r0, MMU_CFG_mskTBW
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andi $r0, $r0, MMU_CFG_mskTBS
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srli $r6, $r6, MMU_CFG_offTBW
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srli $r0, $r0, MMU_CFG_offTBS
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/*
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* we just map the kernel to the maximum way - 1 of tlb
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* reserver one way for UART VA mapping
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* it will cause page fault if UART mapping cover the kernel mapping
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*
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* direct mapping is not supported now.
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*/
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li $r2, 't'
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beqz $r6, __error ! MMU_CFG.TBW = 0 is direct mappin
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addi $r0, $r0, #0x2 ! MMU_CFG.TBS value -> meaning
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sll $r0, $r6, $r0 ! entries = k-way * n-set
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mul $r6, $r0, $r5 ! max size = entries * page size
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/* check kernel image size */
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la $r3, (_end - PAGE_OFFSET)
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li $r2, 's'
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bgt $r3, $r6, __error
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li $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr)
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li $r3, PAGE_OFFSET
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add $r6, $r6, $r3
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_tlb:
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mtsr $r3, $TLB_VPN
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dsb
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tlbop $r2, RWR
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isb
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add $r3, $r3, $r5
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add $r2, $r2, $r5
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bgt $r6, $r3, _tlb
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mfsr $r3, $TLB_MISC ! setup access page size
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li $r2, #~0xf
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and $r3, $r3, $r2
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#ifdef CONFIG_ANDES_PAGE_SIZE_8KB
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ori $r3, $r3, #0x1
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#endif
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mtsr $r3, $TLB_MISC
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mfsr $r0, $MISC_CTL ! Enable BTB and RTP and shadow sp
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ori $r0, $r0, #MISC_init
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mtsr $r0, $MISC_CTL
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mfsr $p1, $PSW
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li $r15, #~PSW_clr ! clear WBNA|DME|IME|DT|IT|POM|INTL|GIE
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and $p1, $p1, $r15
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ori $p1, $p1, #PSW_init
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mtsr $p1, $IPSW ! when iret, it will automatically enable MMU
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la $lp, __mmap_switched
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mtsr $lp, $IPC
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iret
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nop
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.type __switch_data, %object
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__switch_data:
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.long __bss_start ! $r6
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.long _end ! $r7
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.long __atags_pointer ! $atag_pointer
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.long init_task ! $r9, move to $r25
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.long init_thread_union + THREAD_SIZE ! $sp
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/*
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* The following fragment of code is executed with the MMU on in MMU mode,
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* and uses absolute addresses; this is not position independent.
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*/
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.align
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.type __mmap_switched, %function
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__mmap_switched:
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la $r3, __switch_data
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lmw.bim $r6, [$r3], $r9, #0b0001
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move $r25, $r9
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move $fp, #0 ! Clear BSS (and zero $fp)
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beq $r7, $r6, _RRT
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1: swi.bi $fp, [$r6], #4
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bne $r7, $r6, 1b
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swi $r10, [$r8]
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_RRT:
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b start_kernel
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__error:
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b __error
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363
arch/nds32/kernel/setup.c
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363
arch/nds32/kernel/setup.c
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@ -0,0 +1,363 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2005-2017 Andes Technology Corporation
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#include <linux/cpu.h>
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#include <linux/bootmem.h>
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#include <linux/seq_file.h>
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#include <linux/memblock.h>
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#include <linux/console.h>
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#include <linux/screen_info.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <asm/setup.h>
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#include <asm/sections.h>
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#include <asm/proc-fns.h>
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#include <asm/cache_info.h>
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#include <asm/elf.h>
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#include <nds32_intrinsic.h>
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#define HWCAP_MFUSR_PC 0x000001
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#define HWCAP_EXT 0x000002
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#define HWCAP_EXT2 0x000004
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#define HWCAP_FPU 0x000008
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#define HWCAP_AUDIO 0x000010
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#define HWCAP_BASE16 0x000020
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#define HWCAP_STRING 0x000040
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#define HWCAP_REDUCED_REGS 0x000080
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#define HWCAP_VIDEO 0x000100
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#define HWCAP_ENCRYPT 0x000200
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#define HWCAP_EDM 0x000400
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#define HWCAP_LMDMA 0x000800
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#define HWCAP_PFM 0x001000
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#define HWCAP_HSMP 0x002000
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#define HWCAP_TRACE 0x004000
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#define HWCAP_DIV 0x008000
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#define HWCAP_MAC 0x010000
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#define HWCAP_L2C 0x020000
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#define HWCAP_FPU_DP 0x040000
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#define HWCAP_V2 0x080000
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#define HWCAP_DX_REGS 0x100000
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unsigned long cpu_id, cpu_rev, cpu_cfgid;
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char cpu_series;
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char *endianness = NULL;
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unsigned int __atags_pointer __initdata;
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unsigned int elf_hwcap;
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EXPORT_SYMBOL(elf_hwcap);
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/*
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* The following string table, must sync with HWCAP_xx bitmask,
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* which is defined in <asm/procinfo.h>
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*/
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static const char *hwcap_str[] = {
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"mfusr_pc",
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"perf1",
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"perf2",
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"fpu",
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"audio",
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"16b",
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"string",
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"reduced_regs",
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"video",
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"encrypt",
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"edm",
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"lmdma",
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"pfm",
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"hsmp",
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"trace",
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"div",
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"mac",
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"l2c",
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"dx_regs",
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"v2",
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NULL,
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};
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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#define WRITE_METHOD "write through"
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#else
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#define WRITE_METHOD "write back"
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#endif
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struct cache_info L1_cache_info[2];
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static void __init dump_cpu_info(int cpu)
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{
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int i, p = 0;
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char str[sizeof(hwcap_str) + 16];
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for (i = 0; hwcap_str[i]; i++) {
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if (elf_hwcap & (1 << i)) {
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sprintf(str + p, "%s ", hwcap_str[i]);
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p += strlen(hwcap_str[i]) + 1;
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}
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}
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pr_info("CPU%d Features: %s\n", cpu, str);
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L1_cache_info[ICACHE].ways = CACHE_WAY(ICACHE);
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L1_cache_info[ICACHE].line_size = CACHE_LINE_SIZE(ICACHE);
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L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE);
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L1_cache_info[ICACHE].size =
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L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].line_size *
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L1_cache_info[ICACHE].sets / 1024;
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pr_info("L1I:%dKB/%dS/%dW/%dB\n", L1_cache_info[ICACHE].size,
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L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways,
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L1_cache_info[ICACHE].line_size);
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L1_cache_info[DCACHE].ways = CACHE_WAY(DCACHE);
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L1_cache_info[DCACHE].line_size = CACHE_LINE_SIZE(DCACHE);
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L1_cache_info[DCACHE].sets = CACHE_SET(DCACHE);
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L1_cache_info[DCACHE].size =
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L1_cache_info[DCACHE].ways * L1_cache_info[DCACHE].line_size *
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L1_cache_info[DCACHE].sets / 1024;
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pr_info("L1D:%dKB/%dS/%dW/%dB\n", L1_cache_info[DCACHE].size,
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L1_cache_info[DCACHE].sets, L1_cache_info[DCACHE].ways,
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L1_cache_info[DCACHE].line_size);
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pr_info("L1 D-Cache is %s\n", WRITE_METHOD);
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if (L1_cache_info[DCACHE].size != L1_CACHE_BYTES)
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pr_crit
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("The cache line size(%d) of this processor is not the same as L1_CACHE_BYTES(%d).\n",
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L1_cache_info[DCACHE].size, L1_CACHE_BYTES);
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#ifdef CONFIG_CPU_CACHE_ALIASING
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{
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int aliasing_num;
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aliasing_num =
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L1_cache_info[ICACHE].size * 1024 / PAGE_SIZE /
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L1_cache_info[ICACHE].ways;
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L1_cache_info[ICACHE].aliasing_num = aliasing_num;
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L1_cache_info[ICACHE].aliasing_mask =
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(aliasing_num - 1) << PAGE_SHIFT;
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aliasing_num =
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L1_cache_info[DCACHE].size * 1024 / PAGE_SIZE /
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L1_cache_info[DCACHE].ways;
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L1_cache_info[DCACHE].aliasing_num = aliasing_num;
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L1_cache_info[DCACHE].aliasing_mask =
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(aliasing_num - 1) << PAGE_SHIFT;
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}
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#endif
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}
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static void __init setup_cpuinfo(void)
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{
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unsigned long tmp = 0, cpu_name;
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cpu_dcache_inval_all();
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cpu_icache_inval_all();
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__nds32__isb();
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cpu_id = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCPUID) >> CPU_VER_offCPUID;
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cpu_name = ((cpu_id) & 0xf0) >> 4;
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cpu_series = cpu_name ? cpu_name - 10 + 'A' : 'N';
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cpu_id = cpu_id & 0xf;
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cpu_rev = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskREV) >> CPU_VER_offREV;
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cpu_cfgid = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCFGID) >> CPU_VER_offCFGID;
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pr_info("CPU:%c%ld, CPU_VER 0x%08x(id %lu, rev %lu, cfg %lu)\n",
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cpu_series, cpu_id, __nds32__mfsr(NDS32_SR_CPU_VER), cpu_id, cpu_rev, cpu_cfgid);
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elf_hwcap |= HWCAP_MFUSR_PC;
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if (((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskBASEV) >> MSC_CFG_offBASEV) == 0) {
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskDIV)
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elf_hwcap |= HWCAP_DIV;
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if ((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskMAC)
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|| (cpu_id == 12 && cpu_rev < 4))
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elf_hwcap |= HWCAP_MAC;
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} else {
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elf_hwcap |= HWCAP_V2;
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elf_hwcap |= HWCAP_DIV;
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elf_hwcap |= HWCAP_MAC;
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}
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if (cpu_cfgid & 0x0001)
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elf_hwcap |= HWCAP_EXT;
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if (cpu_cfgid & 0x0002)
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elf_hwcap |= HWCAP_BASE16;
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if (cpu_cfgid & 0x0004)
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elf_hwcap |= HWCAP_EXT2;
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if (cpu_cfgid & 0x0008)
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elf_hwcap |= HWCAP_FPU;
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if (cpu_cfgid & 0x0010)
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elf_hwcap |= HWCAP_STRING;
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if (__nds32__mfsr(NDS32_SR_MMU_CFG) & MMU_CFG_mskDE)
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endianness = "MSB";
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else
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endianness = "LSB";
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskEDM)
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elf_hwcap |= HWCAP_EDM;
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskLMDMA)
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elf_hwcap |= HWCAP_LMDMA;
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskPFM)
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elf_hwcap |= HWCAP_PFM;
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskHSMP)
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elf_hwcap |= HWCAP_HSMP;
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskTRACE)
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elf_hwcap |= HWCAP_TRACE;
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskAUDIO)
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elf_hwcap |= HWCAP_AUDIO;
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C)
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elf_hwcap |= HWCAP_L2C;
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tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL);
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if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE))
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tmp |= CACHE_CTL_mskDC_EN;
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if (!IS_ENABLED(CONFIG_CPU_ICACHE_DISABLE))
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tmp |= CACHE_CTL_mskIC_EN;
|
||||
__nds32__mtsr_isb(tmp, NDS32_SR_CACHE_CTL);
|
||||
|
||||
dump_cpu_info(smp_processor_id());
|
||||
}
|
||||
|
||||
static void __init setup_memory(void)
|
||||
{
|
||||
unsigned long ram_start_pfn;
|
||||
unsigned long free_ram_start_pfn;
|
||||
phys_addr_t memory_start, memory_end;
|
||||
struct memblock_region *region;
|
||||
|
||||
memory_end = memory_start = 0;
|
||||
|
||||
/* Find main memory where is the kernel */
|
||||
for_each_memblock(memory, region) {
|
||||
memory_start = region->base;
|
||||
memory_end = region->base + region->size;
|
||||
pr_info("%s: Memory: 0x%x-0x%x\n", __func__,
|
||||
memory_start, memory_end);
|
||||
}
|
||||
|
||||
if (!memory_end) {
|
||||
panic("No memory!");
|
||||
}
|
||||
|
||||
ram_start_pfn = PFN_UP(memblock_start_of_DRAM());
|
||||
/* free_ram_start_pfn is first page after kernel */
|
||||
free_ram_start_pfn = PFN_UP(__pa(&_end));
|
||||
max_pfn = PFN_DOWN(memblock_end_of_DRAM());
|
||||
/* it could update max_pfn */
|
||||
if (max_pfn - ram_start_pfn <= MAXMEM_PFN)
|
||||
max_low_pfn = max_pfn;
|
||||
else {
|
||||
max_low_pfn = MAXMEM_PFN + ram_start_pfn;
|
||||
if (!IS_ENABLED(CONFIG_HIGHMEM))
|
||||
max_pfn = MAXMEM_PFN + ram_start_pfn;
|
||||
}
|
||||
/* high_memory is related with VMALLOC */
|
||||
high_memory = (void *)__va(max_low_pfn * PAGE_SIZE);
|
||||
min_low_pfn = free_ram_start_pfn;
|
||||
|
||||
/*
|
||||
* initialize the boot-time allocator (with low memory only).
|
||||
*
|
||||
* This makes the memory from the end of the kernel to the end of
|
||||
* RAM usable.
|
||||
*/
|
||||
memblock_set_bottom_up(true);
|
||||
memblock_reserve(PFN_PHYS(ram_start_pfn), PFN_PHYS(free_ram_start_pfn - ram_start_pfn));
|
||||
|
||||
early_init_fdt_reserve_self();
|
||||
early_init_fdt_scan_reserved_mem();
|
||||
|
||||
memblock_dump_all();
|
||||
}
|
||||
|
||||
void __init setup_arch(char **cmdline_p)
|
||||
{
|
||||
early_init_devtree( __dtb_start);
|
||||
|
||||
setup_cpuinfo();
|
||||
|
||||
init_mm.start_code = (unsigned long)&_stext;
|
||||
init_mm.end_code = (unsigned long)&_etext;
|
||||
init_mm.end_data = (unsigned long)&_edata;
|
||||
init_mm.brk = (unsigned long)&_end;
|
||||
|
||||
/* setup bootmem allocator */
|
||||
setup_memory();
|
||||
|
||||
/* paging_init() sets up the MMU and marks all pages as reserved */
|
||||
paging_init();
|
||||
|
||||
/* use generic way to parse */
|
||||
parse_early_param();
|
||||
|
||||
unflatten_and_copy_device_tree();
|
||||
|
||||
if(IS_ENABLED(CONFIG_VT)) {
|
||||
if(IS_ENABLED(CONFIG_DUMMY_CONSOLE))
|
||||
conswitchp = &dummy_con;
|
||||
}
|
||||
|
||||
*cmdline_p = boot_command_line;
|
||||
early_trap_init();
|
||||
}
|
||||
|
||||
static int c_show(struct seq_file *m, void *v)
|
||||
{
|
||||
int i;
|
||||
|
||||
seq_printf(m, "Processor\t: %c%ld (id %lu, rev %lu, cfg %lu)\n",
|
||||
cpu_series, cpu_id, cpu_id, cpu_rev, cpu_cfgid);
|
||||
|
||||
seq_printf(m, "L1I\t\t: %luKB/%luS/%luW/%luB\n",
|
||||
CACHE_SET(ICACHE) * CACHE_WAY(ICACHE) *
|
||||
CACHE_LINE_SIZE(ICACHE) / 1024, CACHE_SET(ICACHE),
|
||||
CACHE_WAY(ICACHE), CACHE_LINE_SIZE(ICACHE));
|
||||
|
||||
seq_printf(m, "L1D\t\t: %luKB/%luS/%luW/%luB\n",
|
||||
CACHE_SET(DCACHE) * CACHE_WAY(DCACHE) *
|
||||
CACHE_LINE_SIZE(DCACHE) / 1024, CACHE_SET(DCACHE),
|
||||
CACHE_WAY(DCACHE), CACHE_LINE_SIZE(DCACHE));
|
||||
|
||||
seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
|
||||
loops_per_jiffy / (500000 / HZ),
|
||||
(loops_per_jiffy / (5000 / HZ)) % 100);
|
||||
|
||||
/* dump out the processor features */
|
||||
seq_puts(m, "Features\t: ");
|
||||
|
||||
for (i = 0; hwcap_str[i]; i++)
|
||||
if (elf_hwcap & (1 << i))
|
||||
seq_printf(m, "%s ", hwcap_str[i]);
|
||||
|
||||
seq_puts(m, "\n\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void *c_start(struct seq_file *m, loff_t * pos)
|
||||
{
|
||||
return *pos < 1 ? (void *)1 : NULL;
|
||||
}
|
||||
|
||||
static void *c_next(struct seq_file *m, void *v, loff_t * pos)
|
||||
{
|
||||
++*pos;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void c_stop(struct seq_file *m, void *v)
|
||||
{
|
||||
}
|
||||
|
||||
struct seq_operations cpuinfo_op = {
|
||||
.start = c_start,
|
||||
.next = c_next,
|
||||
.stop = c_stop,
|
||||
.show = c_show
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user