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drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes

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The pattern of a power well backing a set of pipe IRQ or VGA
functionality applies to all HSW+ platforms. Using power well attributes
instead of platform checks to decide whether to init/reset pipe IRQs and
VGA correspondingly is cleaner and it allows us to unify the HSW/BDW and
GEN9+ power well code in follow-up patches.

Also use u8 for pipe_mask in related helpers to match the type in the
power well struct.

v2:
- Use u8 instead of u32 for irq_pipe_mask. (Ville)

v3:
- Use u8 for pipe_mask in related helpers too for clarity.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170712155413.29839-1-imre.deak@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Imre Deak 2017-07-12 18:54:13 +03:00 committed by Daniel Vetter
parent 1af474fef2
commit 001bd2cb17
4 changed files with 31 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/drm/i915/i915_drv.h
View File

@ -1392,6 +1392,12 @@ struct i915_power_well {
struct {
enum dpio_phy phy;
} bxt;
struct {
/* Mask of pipes whose IRQ logic is backed by the pw */
u8 irq_pipe_mask;
/* The pw is backing the VGA functionality */
bool has_vga:1;
} hsw;
};
const struct i915_power_well_ops *ops;
};

4
drivers/gpu/drm/i915/i915_irq.c
View File

@ -3038,7 +3038,7 @@ static void gen8_irq_reset(struct drm_device *dev)
}
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
unsigned int pipe_mask)
u8 pipe_mask)
{
uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
enum pipe pipe;
@ -3052,7 +3052,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
}
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
unsigned int pipe_mask)
u8 pipe_mask)
{
enum pipe pipe;

4
drivers/gpu/drm/i915/intel_drv.h
View File

@ -1230,9 +1230,9 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
int intel_get_crtc_scanline(struct intel_crtc *crtc);
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
unsigned int pipe_mask);
u8 pipe_mask);
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
unsigned int pipe_mask);
u8 pipe_mask);
void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);

34
drivers/gpu/drm/i915/intel_runtime_pm.c
View File

@ -281,7 +281,8 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv,
* to be enabled, and it will only be disabled if none of the registers is
* requesting it to be enabled.
*/
static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
u8 irq_pipe_mask, bool has_vga)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
@ -295,20 +296,21 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
* sure vgacon can keep working normally without triggering interrupts
* and error messages.
*/
vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
vga_put(pdev, VGA_RSRC_LEGACY_IO);
if (has_vga) {
vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
vga_put(pdev, VGA_RSRC_LEGACY_IO);
}
if (IS_BROADWELL(dev_priv))
gen8_irq_power_well_post_enable(dev_priv,
1 << PIPE_C | 1 << PIPE_B);
if (irq_pipe_mask)
gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
}
static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
u8 irq_pipe_mask)
{
if (IS_BROADWELL(dev_priv))
gen8_irq_power_well_pre_disable(dev_priv,
1 << PIPE_C | 1 << PIPE_B);
if (irq_pipe_mask)
gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
}
static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
@ -413,7 +415,9 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
HSW_PWR_WELL_CTL_STATE(id),
20))
DRM_ERROR("Timeout enabling power well\n");
hsw_power_well_post_enable(dev_priv);
hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
power_well->hsw.has_vga);
}
static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
@ -422,7 +426,8 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
enum i915_power_well_id id = power_well->id;
u32 val;
hsw_power_well_pre_disable(dev_priv);
hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask);
val = I915_READ(HSW_PWR_WELL_DRIVER);
I915_WRITE(HSW_PWR_WELL_DRIVER, val & ~HSW_PWR_WELL_CTL_REQ(id));
POSTING_READ(HSW_PWR_WELL_DRIVER);
@ -2057,6 +2062,7 @@ static struct i915_power_well hsw_power_wells[] = {
.domains = HSW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
.hsw.has_vga = true,
},
};
@ -2073,6 +2079,8 @@ static struct i915_power_well bdw_power_wells[] = {
.domains = BDW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = HSW_DISP_PW_GLOBAL,
.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.hsw.has_vga = true,
},
};