drm/amdgpu: open GFX clock gating for sienna_cichlid
Open GFX MGCG, CGCG and 3DCG for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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				| @ -714,7 +714,10 @@ static int nv_common_early_init(void *handle) | ||||
| 		adev->external_rev_id = adev->rev_id + 0xa; | ||||
| 		break; | ||||
| 	case CHIP_SIENNA_CICHLID: | ||||
| 		adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | | ||||
| 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | | ||||
| 			AMD_CG_SUPPORT_GFX_CGCG | | ||||
| 			AMD_CG_SUPPORT_GFX_3D_CGCG | | ||||
| 			AMD_CG_SUPPORT_VCN_MGCG | | ||||
| 			AMD_CG_SUPPORT_JPEG_MGCG; | ||||
| 		adev->pg_flags = AMD_PG_SUPPORT_VCN | | ||||
| 			AMD_PG_SUPPORT_JPEG; | ||||
|  | ||||
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