2016-08-05 12:24:21 +00:00
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/*
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* Driver for Microsemi VSC85xx PHYs
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*
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* Author: Nagaraju Lakkaraju
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* License: Dual MIT/GPL
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* Copyright (c) 2016 Microsemi Corporation
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mdio.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
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#include <linux/of.h>
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2016-10-05 08:49:27 +00:00
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#include <linux/netdevice.h>
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2016-08-05 12:24:21 +00:00
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enum rgmii_rx_clock_delay {
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2016-09-08 08:39:31 +00:00
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RGMII_RX_CLK_DELAY_0_2_NS = 0,
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RGMII_RX_CLK_DELAY_0_8_NS = 1,
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RGMII_RX_CLK_DELAY_1_1_NS = 2,
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RGMII_RX_CLK_DELAY_1_7_NS = 3,
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RGMII_RX_CLK_DELAY_2_0_NS = 4,
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RGMII_RX_CLK_DELAY_2_3_NS = 5,
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RGMII_RX_CLK_DELAY_2_6_NS = 6,
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RGMII_RX_CLK_DELAY_3_4_NS = 7
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2016-08-05 12:24:21 +00:00
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};
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2016-09-19 10:03:54 +00:00
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/* Microsemi VSC85xx PHY registers */
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/* IEEE 802. Std Registers */
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2016-11-29 09:46:48 +00:00
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#define MSCC_PHY_BYPASS_CONTROL 18
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#define DISABLE_HP_AUTO_MDIX_MASK 0x0080
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#define DISABLE_PAIR_SWAP_CORR_MASK 0x0020
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#define DISABLE_POLARITY_CORR_MASK 0x0010
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2016-09-19 10:03:54 +00:00
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#define MSCC_PHY_EXT_PHY_CNTL_1 23
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#define MAC_IF_SELECTION_MASK 0x1800
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#define MAC_IF_SELECTION_GMII 0
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#define MAC_IF_SELECTION_RMII 1
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#define MAC_IF_SELECTION_RGMII 2
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#define MAC_IF_SELECTION_POS 11
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#define FAR_END_LOOPBACK_MODE_MASK 0x0008
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2016-09-08 08:39:31 +00:00
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#define MII_VSC85XX_INT_MASK 25
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#define MII_VSC85XX_INT_MASK_MASK 0xa000
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2016-10-05 08:49:27 +00:00
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#define MII_VSC85XX_INT_MASK_WOL 0x0040
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2016-09-08 08:39:31 +00:00
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#define MII_VSC85XX_INT_STATUS 26
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2016-08-05 12:24:21 +00:00
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net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
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#define MSCC_PHY_WOL_MAC_CONTROL 27
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#define EDGE_RATE_CNTL_POS 5
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#define EDGE_RATE_CNTL_MASK 0x00E0
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2016-11-29 09:46:48 +00:00
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#define MSCC_PHY_DEV_AUX_CNTL 28
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#define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
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2016-09-08 08:39:31 +00:00
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#define MSCC_EXT_PAGE_ACCESS 31
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#define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
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2016-11-17 12:07:24 +00:00
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#define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */
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2016-09-08 08:39:31 +00:00
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#define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
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2016-08-05 12:24:21 +00:00
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2016-11-17 12:07:24 +00:00
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/* Extended Page 1 Registers */
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2016-11-29 09:46:48 +00:00
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#define MSCC_PHY_EXT_MODE_CNTL 19
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#define FORCE_MDI_CROSSOVER_MASK 0x000C
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#define FORCE_MDI_CROSSOVER_MDIX 0x000C
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#define FORCE_MDI_CROSSOVER_MDI 0x0008
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2016-11-17 12:07:24 +00:00
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#define MSCC_PHY_ACTIPHY_CNTL 20
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#define DOWNSHIFT_CNTL_MASK 0x001C
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#define DOWNSHIFT_EN 0x0010
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#define DOWNSHIFT_CNTL_POS 2
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2016-08-05 12:24:21 +00:00
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/* Extended Page 2 Registers */
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2016-09-08 08:39:31 +00:00
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#define MSCC_PHY_RGMII_CNTL 20
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#define RGMII_RX_CLK_DELAY_MASK 0x0070
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#define RGMII_RX_CLK_DELAY_POS 4
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2016-08-05 12:24:21 +00:00
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2016-10-05 08:49:27 +00:00
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#define MSCC_PHY_WOL_LOWER_MAC_ADDR 21
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#define MSCC_PHY_WOL_MID_MAC_ADDR 22
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#define MSCC_PHY_WOL_UPPER_MAC_ADDR 23
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#define MSCC_PHY_WOL_LOWER_PASSWD 24
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#define MSCC_PHY_WOL_MID_PASSWD 25
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#define MSCC_PHY_WOL_UPPER_PASSWD 26
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#define MSCC_PHY_WOL_MAC_CONTROL 27
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#define SECURE_ON_ENABLE 0x8000
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#define SECURE_ON_PASSWD_LEN_4 0x4000
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2016-08-05 12:24:21 +00:00
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/* Microsemi PHY ID's */
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2016-10-28 10:10:11 +00:00
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#define PHY_ID_VSC8530 0x00070560
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2016-09-08 08:39:31 +00:00
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#define PHY_ID_VSC8531 0x00070570
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2016-10-28 10:10:11 +00:00
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#define PHY_ID_VSC8540 0x00070760
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2016-09-08 08:39:31 +00:00
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#define PHY_ID_VSC8541 0x00070770
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2016-08-05 12:24:21 +00:00
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2016-10-12 13:47:51 +00:00
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#define MSCC_VDDMAC_1500 1500
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#define MSCC_VDDMAC_1800 1800
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#define MSCC_VDDMAC_2500 2500
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#define MSCC_VDDMAC_3300 3300
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net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
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2016-11-17 12:07:24 +00:00
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#define DOWNSHIFT_COUNT_MAX 5
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2016-10-12 13:47:51 +00:00
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struct vsc8531_private {
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int rate_magic;
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net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
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};
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2016-10-12 13:47:51 +00:00
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#ifdef CONFIG_OF_MDIO
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struct vsc8531_edge_rate_table {
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net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
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u16 vddmac;
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2016-10-12 13:47:51 +00:00
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u8 slowdown[8];
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net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
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};
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2016-10-12 13:47:51 +00:00
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static const struct vsc8531_edge_rate_table edge_table[] = {
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{MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} },
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{MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} },
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{MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} },
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{MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
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};
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#endif /* CONFIG_OF_MDIO */
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2016-08-05 12:24:21 +00:00
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static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page)
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{
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2016-09-08 08:39:31 +00:00
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int rc;
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2016-08-05 12:24:21 +00:00
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2016-09-08 08:39:31 +00:00
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rc = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
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return rc;
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2016-08-05 12:24:21 +00:00
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}
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2016-11-29 09:46:48 +00:00
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static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
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{
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u16 reg_val;
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reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
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if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
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*mdix = ETH_TP_MDI_X;
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else
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*mdix = ETH_TP_MDI;
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return 0;
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}
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static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
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{
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int rc;
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u16 reg_val;
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reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
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if ((mdix == ETH_TP_MDI) || (mdix == ETH_TP_MDI_X)) {
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reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
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DISABLE_POLARITY_CORR_MASK |
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DISABLE_HP_AUTO_MDIX_MASK);
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} else {
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reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
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DISABLE_POLARITY_CORR_MASK |
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DISABLE_HP_AUTO_MDIX_MASK);
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}
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rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
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if (rc != 0)
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return rc;
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED);
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if (rc != 0)
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return rc;
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reg_val = phy_read(phydev, MSCC_PHY_EXT_MODE_CNTL);
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reg_val &= ~(FORCE_MDI_CROSSOVER_MASK);
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if (mdix == ETH_TP_MDI)
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reg_val |= FORCE_MDI_CROSSOVER_MDI;
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else if (mdix == ETH_TP_MDI_X)
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reg_val |= FORCE_MDI_CROSSOVER_MDIX;
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rc = phy_write(phydev, MSCC_PHY_EXT_MODE_CNTL, reg_val);
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if (rc != 0)
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return rc;
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
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if (rc != 0)
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return rc;
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return genphy_restart_aneg(phydev);
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}
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2016-11-17 12:07:24 +00:00
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static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
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{
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int rc;
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u16 reg_val;
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED);
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if (rc != 0)
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2016-11-22 21:55:31 +00:00
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goto out;
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2016-11-17 12:07:24 +00:00
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reg_val = phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
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reg_val &= DOWNSHIFT_CNTL_MASK;
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if (!(reg_val & DOWNSHIFT_EN))
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*count = DOWNSHIFT_DEV_DISABLE;
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else
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*count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
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2016-11-22 21:55:31 +00:00
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out:
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2016-11-17 12:07:24 +00:00
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return rc;
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}
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static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
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{
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int rc;
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u16 reg_val;
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if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) {
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|
|
|
|
/* Default downshift count 3 (i.e. Bit3:2 = 0b01) */
|
|
|
|
|
count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
|
|
|
|
|
} else if (count > DOWNSHIFT_COUNT_MAX || count == 1) {
|
|
|
|
|
phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
|
|
|
|
|
return -ERANGE;
|
|
|
|
|
} else if (count) {
|
|
|
|
|
/* Downshift count is either 2,3,4 or 5 */
|
|
|
|
|
count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED);
|
|
|
|
|
if (rc != 0)
|
2016-11-22 21:55:31 +00:00
|
|
|
goto out;
|
2016-11-17 12:07:24 +00:00
|
|
|
|
|
|
|
|
reg_val = phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
|
|
|
|
|
reg_val &= ~(DOWNSHIFT_CNTL_MASK);
|
|
|
|
|
reg_val |= count;
|
|
|
|
|
rc = phy_write(phydev, MSCC_PHY_ACTIPHY_CNTL, reg_val);
|
|
|
|
|
if (rc != 0)
|
2016-11-22 21:55:31 +00:00
|
|
|
goto out;
|
2016-11-17 12:07:24 +00:00
|
|
|
|
|
|
|
|
rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
|
|
|
|
|
|
2016-11-22 21:55:31 +00:00
|
|
|
out:
|
2016-11-17 12:07:24 +00:00
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-05 08:49:27 +00:00
|
|
|
static int vsc85xx_wol_set(struct phy_device *phydev,
|
|
|
|
|
struct ethtool_wolinfo *wol)
|
|
|
|
|
{
|
|
|
|
|
int rc;
|
|
|
|
|
u16 reg_val;
|
|
|
|
|
u8 i;
|
|
|
|
|
u16 pwd[3] = {0, 0, 0};
|
|
|
|
|
struct ethtool_wolinfo *wol_conf = wol;
|
|
|
|
|
u8 *mac_addr = phydev->attached_dev->dev_addr;
|
|
|
|
|
|
|
|
|
|
mutex_lock(&phydev->lock);
|
|
|
|
|
rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
|
|
|
|
|
if (rc != 0)
|
|
|
|
|
goto out_unlock;
|
|
|
|
|
|
|
|
|
|
if (wol->wolopts & WAKE_MAGIC) {
|
|
|
|
|
/* Store the device address for the magic packet */
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pwd); i++)
|
|
|
|
|
pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
|
|
|
|
|
mac_addr[5 - i * 2];
|
|
|
|
|
phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
|
|
|
|
|
phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
|
|
|
|
|
phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
|
|
|
|
|
} else {
|
|
|
|
|
phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
|
|
|
|
|
phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
|
|
|
|
|
phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (wol_conf->wolopts & WAKE_MAGICSECURE) {
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pwd); i++)
|
|
|
|
|
pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
|
|
|
|
|
wol_conf->sopass[5 - i * 2];
|
|
|
|
|
phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
|
|
|
|
|
phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
|
|
|
|
|
phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
|
|
|
|
|
} else {
|
|
|
|
|
phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
|
|
|
|
|
phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
|
|
|
|
|
phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
|
|
|
|
|
if (wol_conf->wolopts & WAKE_MAGICSECURE)
|
|
|
|
|
reg_val |= SECURE_ON_ENABLE;
|
|
|
|
|
else
|
|
|
|
|
reg_val &= ~SECURE_ON_ENABLE;
|
|
|
|
|
phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
|
|
|
|
|
|
|
|
|
|
rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
|
|
|
|
|
if (rc != 0)
|
|
|
|
|
goto out_unlock;
|
|
|
|
|
|
|
|
|
|
if (wol->wolopts & WAKE_MAGIC) {
|
|
|
|
|
/* Enable the WOL interrupt */
|
|
|
|
|
reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
|
|
|
|
|
reg_val |= MII_VSC85XX_INT_MASK_WOL;
|
|
|
|
|
rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
|
|
|
|
|
if (rc != 0)
|
|
|
|
|
goto out_unlock;
|
|
|
|
|
} else {
|
|
|
|
|
/* Disable the WOL interrupt */
|
|
|
|
|
reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
|
|
|
|
|
reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
|
|
|
|
|
rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
|
|
|
|
|
if (rc != 0)
|
|
|
|
|
goto out_unlock;
|
|
|
|
|
}
|
|
|
|
|
/* Clear WOL iterrupt status */
|
|
|
|
|
reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
|
|
|
|
|
|
|
|
|
|
out_unlock:
|
|
|
|
|
mutex_unlock(&phydev->lock);
|
|
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void vsc85xx_wol_get(struct phy_device *phydev,
|
|
|
|
|
struct ethtool_wolinfo *wol)
|
|
|
|
|
{
|
|
|
|
|
int rc;
|
|
|
|
|
u16 reg_val;
|
|
|
|
|
u8 i;
|
|
|
|
|
u16 pwd[3] = {0, 0, 0};
|
|
|
|
|
struct ethtool_wolinfo *wol_conf = wol;
|
|
|
|
|
|
|
|
|
|
mutex_lock(&phydev->lock);
|
|
|
|
|
rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
|
|
|
|
|
if (rc != 0)
|
|
|
|
|
goto out_unlock;
|
|
|
|
|
|
|
|
|
|
reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
|
|
|
|
|
if (reg_val & SECURE_ON_ENABLE)
|
|
|
|
|
wol_conf->wolopts |= WAKE_MAGICSECURE;
|
|
|
|
|
if (wol_conf->wolopts & WAKE_MAGICSECURE) {
|
|
|
|
|
pwd[0] = phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
|
|
|
|
|
pwd[1] = phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
|
|
|
|
|
pwd[2] = phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pwd); i++) {
|
|
|
|
|
wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
|
|
|
|
|
wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
|
|
|
|
|
>> 8;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
|
|
|
|
|
|
|
|
|
|
out_unlock:
|
|
|
|
|
mutex_unlock(&phydev->lock);
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-12 13:47:51 +00:00
|
|
|
#ifdef CONFIG_OF_MDIO
|
|
|
|
|
static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
|
net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
|
|
|
{
|
|
|
|
|
u8 sd;
|
2016-10-12 13:47:51 +00:00
|
|
|
u16 vdd;
|
|
|
|
|
int rc, i, j;
|
|
|
|
|
struct device *dev = &phydev->mdio.dev;
|
|
|
|
|
struct device_node *of_node = dev->of_node;
|
|
|
|
|
u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown);
|
net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
|
|
|
|
2016-10-12 13:47:51 +00:00
|
|
|
if (!of_node)
|
|
|
|
|
return -ENODEV;
|
net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
|
|
|
|
2016-10-12 13:47:51 +00:00
|
|
|
rc = of_property_read_u16(of_node, "vsc8531,vddmac", &vdd);
|
|
|
|
|
if (rc != 0)
|
|
|
|
|
vdd = MSCC_VDDMAC_3300;
|
|
|
|
|
|
|
|
|
|
rc = of_property_read_u8(of_node, "vsc8531,edge-slowdown", &sd);
|
|
|
|
|
if (rc != 0)
|
|
|
|
|
sd = 0;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(edge_table); i++)
|
|
|
|
|
if (edge_table[i].vddmac == vdd)
|
|
|
|
|
for (j = 0; j < sd_array_size; j++)
|
|
|
|
|
if (edge_table[i].slowdown[j] == sd)
|
|
|
|
|
return (sd_array_size - j - 1);
|
|
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
|
|
|
|
|
{
|
|
|
|
|
return 0;
|
net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
|
|
|
}
|
2016-10-12 13:47:51 +00:00
|
|
|
#endif /* CONFIG_OF_MDIO */
|
net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
|
|
|
|
2016-10-12 13:47:51 +00:00
|
|
|
static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
|
net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
|
|
|
{
|
|
|
|
|
int rc;
|
|
|
|
|
u16 reg_val;
|
|
|
|
|
|
|
|
|
|
mutex_lock(&phydev->lock);
|
|
|
|
|
rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
|
|
|
|
|
if (rc != 0)
|
|
|
|
|
goto out_unlock;
|
|
|
|
|
reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
|
|
|
|
|
reg_val &= ~(EDGE_RATE_CNTL_MASK);
|
|
|
|
|
reg_val |= (edge_rate << EDGE_RATE_CNTL_POS);
|
|
|
|
|
rc = phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
|
|
|
|
|
if (rc != 0)
|
|
|
|
|
goto out_unlock;
|
|
|
|
|
rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
|
|
|
|
|
|
|
|
|
|
out_unlock:
|
|
|
|
|
mutex_unlock(&phydev->lock);
|
|
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
|
2016-09-19 10:03:54 +00:00
|
|
|
static int vsc85xx_mac_if_set(struct phy_device *phydev,
|
|
|
|
|
phy_interface_t interface)
|
|
|
|
|
{
|
|
|
|
|
int rc;
|
|
|
|
|
u16 reg_val;
|
|
|
|
|
|
|
|
|
|
mutex_lock(&phydev->lock);
|
|
|
|
|
reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
|
|
|
|
|
reg_val &= ~(MAC_IF_SELECTION_MASK);
|
|
|
|
|
switch (interface) {
|
|
|
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
|
|
|
reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
|
|
|
|
|
break;
|
|
|
|
|
case PHY_INTERFACE_MODE_RMII:
|
|
|
|
|
reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
|
|
|
|
|
break;
|
|
|
|
|
case PHY_INTERFACE_MODE_MII:
|
|
|
|
|
case PHY_INTERFACE_MODE_GMII:
|
|
|
|
|
reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
rc = -EINVAL;
|
|
|
|
|
goto out_unlock;
|
|
|
|
|
}
|
|
|
|
|
rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
|
|
|
|
|
if (rc != 0)
|
|
|
|
|
goto out_unlock;
|
|
|
|
|
|
|
|
|
|
rc = genphy_soft_reset(phydev);
|
|
|
|
|
|
|
|
|
|
out_unlock:
|
|
|
|
|
mutex_unlock(&phydev->lock);
|
|
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
|
2016-08-05 12:24:21 +00:00
|
|
|
static int vsc85xx_default_config(struct phy_device *phydev)
|
|
|
|
|
{
|
2016-09-08 08:39:31 +00:00
|
|
|
int rc;
|
|
|
|
|
u16 reg_val;
|
2016-08-05 12:24:21 +00:00
|
|
|
|
2016-11-29 09:46:48 +00:00
|
|
|
phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
|
2016-09-08 08:39:31 +00:00
|
|
|
mutex_lock(&phydev->lock);
|
|
|
|
|
rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
|
|
|
|
|
if (rc != 0)
|
|
|
|
|
goto out_unlock;
|
2016-08-05 12:24:21 +00:00
|
|
|
|
2016-09-08 08:39:31 +00:00
|
|
|
reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);
|
|
|
|
|
reg_val &= ~(RGMII_RX_CLK_DELAY_MASK);
|
|
|
|
|
reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS);
|
|
|
|
|
phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);
|
|
|
|
|
rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
|
2016-08-05 12:24:21 +00:00
|
|
|
|
|
|
|
|
out_unlock:
|
2016-09-08 08:39:31 +00:00
|
|
|
mutex_unlock(&phydev->lock);
|
2016-08-05 12:24:21 +00:00
|
|
|
|
2016-09-08 08:39:31 +00:00
|
|
|
return rc;
|
2016-08-05 12:24:21 +00:00
|
|
|
}
|
|
|
|
|
|
2016-11-17 12:07:24 +00:00
|
|
|
static int vsc85xx_get_tunable(struct phy_device *phydev,
|
|
|
|
|
struct ethtool_tunable *tuna, void *data)
|
|
|
|
|
{
|
|
|
|
|
switch (tuna->id) {
|
|
|
|
|
case ETHTOOL_PHY_DOWNSHIFT:
|
|
|
|
|
return vsc85xx_downshift_get(phydev, (u8 *)data);
|
|
|
|
|
default:
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int vsc85xx_set_tunable(struct phy_device *phydev,
|
|
|
|
|
struct ethtool_tunable *tuna,
|
|
|
|
|
const void *data)
|
|
|
|
|
{
|
|
|
|
|
switch (tuna->id) {
|
|
|
|
|
case ETHTOOL_PHY_DOWNSHIFT:
|
|
|
|
|
return vsc85xx_downshift_set(phydev, *(u8 *)data);
|
|
|
|
|
default:
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-08-05 12:24:21 +00:00
|
|
|
static int vsc85xx_config_init(struct phy_device *phydev)
|
|
|
|
|
{
|
2016-09-08 08:39:31 +00:00
|
|
|
int rc;
|
net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
|
|
|
struct vsc8531_private *vsc8531 = phydev->priv;
|
2016-08-05 12:24:21 +00:00
|
|
|
|
2016-09-08 08:39:31 +00:00
|
|
|
rc = vsc85xx_default_config(phydev);
|
|
|
|
|
if (rc)
|
|
|
|
|
return rc;
|
2016-09-19 10:03:54 +00:00
|
|
|
|
|
|
|
|
rc = vsc85xx_mac_if_set(phydev, phydev->interface);
|
|
|
|
|
if (rc)
|
|
|
|
|
return rc;
|
|
|
|
|
|
2016-10-12 13:47:51 +00:00
|
|
|
rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
|
net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
|
|
|
if (rc)
|
|
|
|
|
return rc;
|
|
|
|
|
|
2016-09-08 08:39:31 +00:00
|
|
|
rc = genphy_config_init(phydev);
|
2016-08-05 12:24:21 +00:00
|
|
|
|
2016-09-08 08:39:31 +00:00
|
|
|
return rc;
|
2016-08-05 12:24:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int vsc85xx_ack_interrupt(struct phy_device *phydev)
|
|
|
|
|
{
|
2016-09-08 08:39:31 +00:00
|
|
|
int rc = 0;
|
2016-08-05 12:24:21 +00:00
|
|
|
|
2016-09-08 08:39:31 +00:00
|
|
|
if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
|
|
|
|
|
rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
|
2016-08-05 12:24:21 +00:00
|
|
|
|
2016-09-08 08:39:31 +00:00
|
|
|
return (rc < 0) ? rc : 0;
|
2016-08-05 12:24:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int vsc85xx_config_intr(struct phy_device *phydev)
|
|
|
|
|
{
|
2016-09-08 08:39:31 +00:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
|
|
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
|
|
|
|
|
rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
|
|
|
|
|
MII_VSC85XX_INT_MASK_MASK);
|
|
|
|
|
} else {
|
|
|
|
|
rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
|
|
|
|
|
if (rc < 0)
|
|
|
|
|
return rc;
|
|
|
|
|
rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return rc;
|
2016-08-05 12:24:21 +00:00
|
|
|
}
|
|
|
|
|
|
2016-11-29 09:46:48 +00:00
|
|
|
static int vsc85xx_config_aneg(struct phy_device *phydev)
|
|
|
|
|
{
|
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
|
|
rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
|
|
|
|
|
if (rc < 0)
|
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
|
|
return genphy_config_aneg(phydev);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int vsc85xx_read_status(struct phy_device *phydev)
|
|
|
|
|
{
|
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
|
|
rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
|
|
|
|
|
if (rc < 0)
|
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
|
|
return genphy_read_status(phydev);
|
|
|
|
|
}
|
|
|
|
|
|
net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
|
|
|
static int vsc85xx_probe(struct phy_device *phydev)
|
|
|
|
|
{
|
2016-10-12 13:47:51 +00:00
|
|
|
int rate_magic;
|
net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
|
|
|
struct vsc8531_private *vsc8531;
|
|
|
|
|
|
2016-10-12 13:47:51 +00:00
|
|
|
rate_magic = vsc85xx_edge_rate_magic_get(phydev);
|
|
|
|
|
if (rate_magic < 0)
|
|
|
|
|
return rate_magic;
|
|
|
|
|
|
net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
|
|
|
vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
|
|
|
|
|
if (!vsc8531)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
phydev->priv = vsc8531;
|
|
|
|
|
|
2016-10-12 13:47:51 +00:00
|
|
|
vsc8531->rate_magic = rate_magic;
|
|
|
|
|
|
net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate:
As system and networking speeds increase, a signal's output transition,
also know as the edge rate or slew rate (V/ns), takes on greater importance
because high-speed signals come with a price. That price is an assortment of
interference problems like ringing on the line, signal overshoot and
undershoot, extended signal settling times, crosstalk noise, transmission
line reflections, false signal detection by the receiving device and
electromagnetic interference (EMI) -- all of which can negate the potential
gains designers are seeking when they try to increase system speeds through
the use of higher performance logic devices. The fact is, faster signaling
edge rates can cause a higher level of electrical noise or other type of
interference that can actually lead to slower line speeds and lower maximum
system frequencies. This parameter allow the board designers to change the
driving strange, and thereby change the EMI behavioral.
Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree.
Tested on Beaglebone Black with VSC 8531 PHY.
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-10-03 07:23:13 +00:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2016-08-05 12:24:21 +00:00
|
|
|
/* Microsemi VSC85xx PHYs */
|
|
|
|
|
static struct phy_driver vsc85xx_driver[] = {
|
2016-10-28 10:10:11 +00:00
|
|
|
{
|
|
|
|
|
.phy_id = PHY_ID_VSC8530,
|
|
|
|
|
.name = "Microsemi FE VSC8530",
|
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
|
.features = PHY_BASIC_FEATURES,
|
|
|
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
|
|
|
.soft_reset = &genphy_soft_reset,
|
|
|
|
|
.config_init = &vsc85xx_config_init,
|
2016-11-29 09:46:48 +00:00
|
|
|
.config_aneg = &vsc85xx_config_aneg,
|
2016-10-28 10:10:11 +00:00
|
|
|
.aneg_done = &genphy_aneg_done,
|
2016-11-29 09:46:48 +00:00
|
|
|
.read_status = &vsc85xx_read_status,
|
2016-10-28 10:10:11 +00:00
|
|
|
.ack_interrupt = &vsc85xx_ack_interrupt,
|
|
|
|
|
.config_intr = &vsc85xx_config_intr,
|
|
|
|
|
.suspend = &genphy_suspend,
|
|
|
|
|
.resume = &genphy_resume,
|
|
|
|
|
.probe = &vsc85xx_probe,
|
|
|
|
|
.set_wol = &vsc85xx_wol_set,
|
|
|
|
|
.get_wol = &vsc85xx_wol_get,
|
2016-11-17 12:07:24 +00:00
|
|
|
.get_tunable = &vsc85xx_get_tunable,
|
|
|
|
|
.set_tunable = &vsc85xx_set_tunable,
|
2016-10-28 10:10:11 +00:00
|
|
|
},
|
2016-08-05 12:24:21 +00:00
|
|
|
{
|
2016-09-08 08:39:31 +00:00
|
|
|
.phy_id = PHY_ID_VSC8531,
|
|
|
|
|
.name = "Microsemi VSC8531",
|
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
|
.features = PHY_GBIT_FEATURES,
|
|
|
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
|
|
|
.soft_reset = &genphy_soft_reset,
|
|
|
|
|
.config_init = &vsc85xx_config_init,
|
2016-11-29 09:46:48 +00:00
|
|
|
.config_aneg = &vsc85xx_config_aneg,
|
2016-09-08 08:39:31 +00:00
|
|
|
.aneg_done = &genphy_aneg_done,
|
2016-11-29 09:46:48 +00:00
|
|
|
.read_status = &vsc85xx_read_status,
|
2016-09-08 08:39:31 +00:00
|
|
|
.ack_interrupt = &vsc85xx_ack_interrupt,
|
|
|
|
|
.config_intr = &vsc85xx_config_intr,
|
|
|
|
|
.suspend = &genphy_suspend,
|
|
|
|
|
.resume = &genphy_resume,
|
2016-10-12 13:47:51 +00:00
|
|
|
.probe = &vsc85xx_probe,
|
|
|
|
|
.set_wol = &vsc85xx_wol_set,
|
|
|
|
|
.get_wol = &vsc85xx_wol_get,
|
2016-11-17 12:07:24 +00:00
|
|
|
.get_tunable = &vsc85xx_get_tunable,
|
|
|
|
|
.set_tunable = &vsc85xx_set_tunable,
|
2016-08-05 12:24:21 +00:00
|
|
|
},
|
2016-10-28 10:10:11 +00:00
|
|
|
{
|
|
|
|
|
.phy_id = PHY_ID_VSC8540,
|
|
|
|
|
.name = "Microsemi FE VSC8540 SyncE",
|
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
|
.features = PHY_BASIC_FEATURES,
|
|
|
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
|
|
|
.soft_reset = &genphy_soft_reset,
|
|
|
|
|
.config_init = &vsc85xx_config_init,
|
2016-11-29 09:46:48 +00:00
|
|
|
.config_aneg = &vsc85xx_config_aneg,
|
2016-10-28 10:10:11 +00:00
|
|
|
.aneg_done = &genphy_aneg_done,
|
2016-11-29 09:46:48 +00:00
|
|
|
.read_status = &vsc85xx_read_status,
|
2016-10-28 10:10:11 +00:00
|
|
|
.ack_interrupt = &vsc85xx_ack_interrupt,
|
|
|
|
|
.config_intr = &vsc85xx_config_intr,
|
|
|
|
|
.suspend = &genphy_suspend,
|
|
|
|
|
.resume = &genphy_resume,
|
|
|
|
|
.probe = &vsc85xx_probe,
|
|
|
|
|
.set_wol = &vsc85xx_wol_set,
|
|
|
|
|
.get_wol = &vsc85xx_wol_get,
|
2016-11-17 12:07:24 +00:00
|
|
|
.get_tunable = &vsc85xx_get_tunable,
|
|
|
|
|
.set_tunable = &vsc85xx_set_tunable,
|
2016-10-28 10:10:11 +00:00
|
|
|
},
|
2016-08-05 12:24:21 +00:00
|
|
|
{
|
2016-09-08 08:39:31 +00:00
|
|
|
.phy_id = PHY_ID_VSC8541,
|
|
|
|
|
.name = "Microsemi VSC8541 SyncE",
|
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
|
.features = PHY_GBIT_FEATURES,
|
|
|
|
|
.flags = PHY_HAS_INTERRUPT,
|
|
|
|
|
.soft_reset = &genphy_soft_reset,
|
|
|
|
|
.config_init = &vsc85xx_config_init,
|
2016-11-29 09:46:48 +00:00
|
|
|
.config_aneg = &vsc85xx_config_aneg,
|
2016-09-08 08:39:31 +00:00
|
|
|
.aneg_done = &genphy_aneg_done,
|
2016-11-29 09:46:48 +00:00
|
|
|
.read_status = &vsc85xx_read_status,
|
2016-09-08 08:39:31 +00:00
|
|
|
.ack_interrupt = &vsc85xx_ack_interrupt,
|
|
|
|
|
.config_intr = &vsc85xx_config_intr,
|
|
|
|
|
.suspend = &genphy_suspend,
|
|
|
|
|
.resume = &genphy_resume,
|
2016-10-12 13:47:51 +00:00
|
|
|
.probe = &vsc85xx_probe,
|
|
|
|
|
.set_wol = &vsc85xx_wol_set,
|
|
|
|
|
.get_wol = &vsc85xx_wol_get,
|
2016-11-17 12:07:24 +00:00
|
|
|
.get_tunable = &vsc85xx_get_tunable,
|
|
|
|
|
.set_tunable = &vsc85xx_set_tunable,
|
2016-08-05 12:24:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
module_phy_driver(vsc85xx_driver);
|
|
|
|
|
|
|
|
|
|
static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
|
2016-10-28 10:10:11 +00:00
|
|
|
{ PHY_ID_VSC8530, 0xfffffff0, },
|
2016-09-08 08:39:31 +00:00
|
|
|
{ PHY_ID_VSC8531, 0xfffffff0, },
|
2016-10-28 10:10:11 +00:00
|
|
|
{ PHY_ID_VSC8540, 0xfffffff0, },
|
2016-09-08 08:39:31 +00:00
|
|
|
{ PHY_ID_VSC8541, 0xfffffff0, },
|
|
|
|
|
{ }
|
2016-08-05 12:24:21 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
|
|
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
|
|
|
|
|
MODULE_AUTHOR("Nagaraju Lakkaraju");
|
|
|
|
|
MODULE_LICENSE("Dual MIT/GPL");
|
