forked from Minki/linux
327 lines
9.8 KiB
C
327 lines
9.8 KiB
C
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/*
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* MPC86xx HPCN board specific routines
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*
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* Recode: ZHANG WEI <wei.zhang@freescale.com>
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* Initial author: Xianghua Xiao <x.xiao@freescale.com>
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpc86xx.h>
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#include <asm/prom.h>
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#include <mm/mmu_decl.h>
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#include <asm/udbg.h>
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#include <asm/i8259.h>
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#include <asm/mpic.h>
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#include <sysdev/fsl_soc.h>
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#include "mpc86xx.h"
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#ifndef CONFIG_PCI
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unsigned long isa_io_base = 0;
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unsigned long isa_mem_base = 0;
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unsigned long pci_dram_offset = 0;
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#endif
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/*
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* Internal interrupts are all Level Sensitive, and Positive Polarity
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*/
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static u_char mpc86xx_hpcn_openpic_initsenses[] __initdata = {
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: Reserved */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: MCM */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCIE1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: PCIE2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: Reserved */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: Reserved */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: DUART2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 1 Transmit */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 1 Receive */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: TSEC 3 transmit */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: TSEC 3 receive */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: TSEC 3 error */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 1 Receive/Transmit Error */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 2 Transmit */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 2 Receive */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: TSEC 4 transmit */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: TSEC 4 receive */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: TSEC 4 error */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 2 Receive/Transmit Error */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32: SRIO error/write-port unit */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33: SRIO outbound doorbell */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34: SRIO inbound doorbell */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37: SRIO outbound message unit 1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38: SRIO inbound message unit 1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39: SRIO outbound message unit 2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40: SRIO inbound message unit 2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 47: Unused */
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0x0, /* External 0: */
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0x0, /* External 1: */
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0x0, /* External 2: */
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0x0, /* External 3: */
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0x0, /* External 4: */
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0x0, /* External 5: */
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0x0, /* External 6: */
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0x0, /* External 7: */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 8: Pixis FPGA */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 9: ULI 8259 INTR Cascade */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 10: Quad ETH PHY */
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0x0, /* External 11: */
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0x0,
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0x0,
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0x0,
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0x0,
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};
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void __init
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mpc86xx_hpcn_init_irq(void)
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{
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struct mpic *mpic1;
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phys_addr_t openpic_paddr;
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/* Determine the Physical Address of the OpenPIC regs */
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openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
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/* Alloc mpic structure and per isu has 16 INT entries. */
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mpic1 = mpic_alloc(openpic_paddr,
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MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
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16, MPC86xx_OPENPIC_IRQ_OFFSET, 0, 250,
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mpc86xx_hpcn_openpic_initsenses,
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sizeof(mpc86xx_hpcn_openpic_initsenses),
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" MPIC ");
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BUG_ON(mpic1 == NULL);
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/* 48 Internal Interrupts */
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mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10200);
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mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10400);
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mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10600);
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/* 16 External interrupts */
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mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10000);
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mpic_init(mpic1);
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#ifdef CONFIG_PCI
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mpic_setup_cascade(MPC86xx_IRQ_EXT9, i8259_irq_cascade, NULL);
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i8259_init(0, I8259_OFFSET);
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#endif
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}
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#ifdef CONFIG_PCI
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/*
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* interrupt routing
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*/
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int
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mpc86xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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static char pci_irq_table[][4] = {
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 17 -- PCI Slot 1 */
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{PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 18 -- PCI Slot 2 */
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{0, 0, 0, 0}, /* IDSEL 19 */
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{0, 0, 0, 0}, /* IDSEL 20 */
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{0, 0, 0, 0}, /* IDSEL 21 */
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{0, 0, 0, 0}, /* IDSEL 22 */
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{0, 0, 0, 0}, /* IDSEL 23 */
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{0, 0, 0, 0}, /* IDSEL 24 */
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{0, 0, 0, 0}, /* IDSEL 25 */
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{PIRQD, PIRQA, PIRQB, PIRQC}, /* IDSEL 26 -- PCI Bridge*/
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{PIRQC, 0, 0, 0}, /* IDSEL 27 -- LAN */
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{PIRQE, PIRQF, PIRQH, PIRQ7}, /* IDSEL 28 -- USB 1.1 */
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{PIRQE, PIRQF, PIRQG, 0}, /* IDSEL 29 -- Audio & Modem */
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{PIRQH, 0, 0, 0}, /* IDSEL 30 -- LPC & PMU*/
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{PIRQD, 0, 0, 0}, /* IDSEL 31 -- ATA */
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};
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const long min_idsel = 17, max_idsel = 31, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET;
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}
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int
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mpc86xx_exclude_device(u_char bus, u_char devfn)
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{
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#if !defined(CONFIG_PCI)
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if (bus == 0 && PCI_SLOT(devfn) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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#endif
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return PCIBIOS_SUCCESSFUL;
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}
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#endif /* CONFIG_PCI */
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static void __init
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mpc86xx_hpcn_setup_arch(void)
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{
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struct device_node *np;
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if (ppc_md.progress)
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ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
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np = of_find_node_by_type(NULL, "cpu");
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if (np != 0) {
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unsigned int *fp;
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fp = (int *)get_property(np, "clock-frequency", NULL);
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if (fp != 0)
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loops_per_jiffy = *fp / HZ;
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else
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loops_per_jiffy = 50000000 / HZ;
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of_node_put(np);
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}
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#ifdef CONFIG_PCI
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for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
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add_bridge(np);
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = mpc86xx_map_irq;
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ppc_md.pci_exclude_device = mpc86xx_exclude_device;
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#endif
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printk("MPC86xx HPCN board from Freescale Semiconductor\n");
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_HDA1;
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#endif
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#ifdef CONFIG_SMP
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mpc86xx_smp_init();
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#endif
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}
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void
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mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
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{
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struct device_node *root;
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uint memsize = total_memory;
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const char *model = "";
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uint svid = mfspr(SPRN_SVR);
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seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
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root = of_find_node_by_path("/");
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if (root)
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model = get_property(root, "model", NULL);
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seq_printf(m, "Machine\t\t: %s\n", model);
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of_node_put(root);
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seq_printf(m, "SVR\t\t: 0x%x\n", svid);
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seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
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}
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init mpc86xx_hpcn_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (of_flat_dt_is_compatible(root, "mpc86xx"))
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return 1; /* Looks good */
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return 0;
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}
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void
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mpc86xx_restart(char *cmd)
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{
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void __iomem *rstcr;
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rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
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local_irq_disable();
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/* Assert reset request to Reset Control Register */
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out_be32(rstcr, 0x2);
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/* not reached */
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}
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long __init
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mpc86xx_time_init(void)
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{
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unsigned int temp;
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/* Set the time base to zero */
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mtspr(SPRN_TBWL, 0);
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mtspr(SPRN_TBWU, 0);
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temp = mfspr(SPRN_HID0);
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temp |= HID0_TBEN;
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mtspr(SPRN_HID0, temp);
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asm volatile("isync");
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return 0;
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}
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define_machine(mpc86xx_hpcn) {
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.name = "MPC86xx HPCN",
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.probe = mpc86xx_hpcn_probe,
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.setup_arch = mpc86xx_hpcn_setup_arch,
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.init_IRQ = mpc86xx_hpcn_init_irq,
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.show_cpuinfo = mpc86xx_hpcn_show_cpuinfo,
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.get_irq = mpic_get_irq,
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.restart = mpc86xx_restart,
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.time_init = mpc86xx_time_init,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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