2013-11-30 21:12:10 +00:00
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MSM_KMS_H__
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#define __MSM_KMS_H__
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#include <linux/clk.h>
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#include <linux/regulator/consumer.h>
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#include "msm_drv.h"
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2014-12-08 15:48:57 +00:00
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#define MAX_PLANE 4
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2013-11-30 21:12:10 +00:00
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/* As there are different display controller blocks depending on the
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* snapdragon version, the kms support is split out and the appropriate
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* implementation is loaded at runtime. The kms module is responsible
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* for constructing the appropriate planes/crtcs/encoders/connectors.
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*/
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struct msm_kms_funcs {
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/* hw initialization: */
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int (*hw_init)(struct msm_kms *kms);
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/* irq handling: */
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void (*irq_preinstall)(struct msm_kms *kms);
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int (*irq_postinstall)(struct msm_kms *kms);
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void (*irq_uninstall)(struct msm_kms *kms);
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irqreturn_t (*irq)(struct msm_kms *kms);
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int (*enable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
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void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
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2016-11-04 17:51:42 +00:00
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/* swap global atomic state: */
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void (*swap_state)(struct msm_kms *kms, struct drm_atomic_state *state);
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2015-01-30 22:04:45 +00:00
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/* modeset, bracketing atomic_commit(): */
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void (*prepare_commit)(struct msm_kms *kms, struct drm_atomic_state *state);
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void (*complete_commit)(struct msm_kms *kms, struct drm_atomic_state *state);
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2015-04-28 23:35:37 +00:00
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/* functions to wait for atomic commit completed on each CRTC */
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void (*wait_for_crtc_commit_done)(struct msm_kms *kms,
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struct drm_crtc *crtc);
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2013-11-30 21:12:10 +00:00
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/* misc: */
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const struct msm_format *(*get_format)(struct msm_kms *kms, uint32_t format);
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long (*round_pixclk)(struct msm_kms *kms, unsigned long rate,
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struct drm_encoder *encoder);
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2015-03-26 23:25:15 +00:00
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int (*set_split_display)(struct msm_kms *kms,
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struct drm_encoder *encoder,
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struct drm_encoder *slave_encoder,
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bool is_cmd_mode);
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2016-12-05 09:54:53 +00:00
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void (*set_encoder_mode)(struct msm_kms *kms,
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struct drm_encoder *encoder,
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bool cmd_mode);
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2013-11-30 21:12:10 +00:00
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/* cleanup: */
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void (*destroy)(struct msm_kms *kms);
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2016-10-26 18:06:55 +00:00
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#ifdef CONFIG_DEBUG_FS
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/* debugfs: */
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int (*debugfs_init)(struct msm_kms *kms, struct drm_minor *minor);
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#endif
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2013-11-30 21:12:10 +00:00
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};
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struct msm_kms {
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const struct msm_kms_funcs *funcs;
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2016-05-18 09:36:03 +00:00
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/* irq number to be passed on to drm_irq_install */
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int irq;
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2017-06-13 14:22:37 +00:00
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/* mapper-id used to request GEM buffer mapped for scanout: */
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struct msm_gem_address_space *aspace;
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2013-11-30 21:12:10 +00:00
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};
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2016-11-04 17:51:42 +00:00
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/**
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* Subclass of drm_atomic_state, to allow kms backend to have driver
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* private global state. The kms backend can do whatever it wants
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* with the ->state ptr. On ->atomic_state_clear() the ->state ptr
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* is kfree'd and set back to NULL.
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*/
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struct msm_kms_state {
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struct drm_atomic_state base;
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void *state;
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};
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#define to_kms_state(x) container_of(x, struct msm_kms_state, base)
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2013-11-30 22:24:22 +00:00
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static inline void msm_kms_init(struct msm_kms *kms,
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const struct msm_kms_funcs *funcs)
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{
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kms->funcs = funcs;
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}
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2013-11-30 21:12:10 +00:00
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struct msm_kms *mdp4_kms_init(struct drm_device *dev);
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drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-11-30 22:51:47 +00:00
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struct msm_kms *mdp5_kms_init(struct drm_device *dev);
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2016-05-07 17:41:25 +00:00
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int msm_mdss_init(struct drm_device *dev);
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void msm_mdss_destroy(struct drm_device *dev);
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2013-11-30 21:12:10 +00:00
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#endif /* __MSM_KMS_H__ */
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