2012-05-09 18:37:20 +00:00
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/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eugeni Dodonov <eugeni.dodonov@intel.com>
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*
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*/
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#include "i915_drv.h"
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#include "intel_drv.h"
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2014-08-27 13:27:30 +00:00
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struct ddi_buf_trans {
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u32 trans1; /* balance leg enable, de-emph level */
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u32 trans2; /* vref sel, vswing */
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2015-06-25 08:11:03 +00:00
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u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
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2014-08-27 13:27:30 +00:00
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};
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2012-05-09 18:37:20 +00:00
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/* HDMI/DVI modes ignore everything but the last 2 items. So we share
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* them for both DP and FDI transports, allowing those ports to
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* automatically adapt to HDMI connections as well
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*/
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2014-08-27 13:27:30 +00:00
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static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
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2015-06-25 08:11:03 +00:00
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{ 0x00FFFFFF, 0x0006000E, 0x0 },
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{ 0x00D75FFF, 0x0005000A, 0x0 },
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{ 0x00C30FFF, 0x00040006, 0x0 },
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{ 0x80AAAFFF, 0x000B0000, 0x0 },
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{ 0x00FFFFFF, 0x0005000A, 0x0 },
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{ 0x00D75FFF, 0x000C0004, 0x0 },
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{ 0x80C30FFF, 0x000B0000, 0x0 },
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{ 0x00FFFFFF, 0x00040006, 0x0 },
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{ 0x80D75FFF, 0x000B0000, 0x0 },
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2012-05-09 18:37:20 +00:00
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};
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2014-08-27 13:27:30 +00:00
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static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
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2015-06-25 08:11:03 +00:00
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{ 0x00FFFFFF, 0x0007000E, 0x0 },
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{ 0x00D75FFF, 0x000F000A, 0x0 },
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{ 0x00C30FFF, 0x00060006, 0x0 },
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{ 0x00AAAFFF, 0x001E0000, 0x0 },
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{ 0x00FFFFFF, 0x000F000A, 0x0 },
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{ 0x00D75FFF, 0x00160004, 0x0 },
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{ 0x00C30FFF, 0x001E0000, 0x0 },
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{ 0x00FFFFFF, 0x00060006, 0x0 },
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{ 0x00D75FFF, 0x001E0000, 0x0 },
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2013-09-12 20:06:24 +00:00
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};
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2014-08-27 13:27:30 +00:00
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static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
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/* Idx NT mV d T mV d db */
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2015-06-25 08:11:03 +00:00
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{ 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
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{ 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
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{ 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
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{ 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
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{ 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
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{ 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
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{ 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
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{ 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
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{ 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
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{ 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
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{ 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
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{ 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
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2012-05-09 18:37:20 +00:00
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};
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2014-08-27 13:27:30 +00:00
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static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
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2015-06-25 08:11:03 +00:00
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{ 0x00FFFFFF, 0x00000012, 0x0 },
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{ 0x00EBAFFF, 0x00020011, 0x0 },
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{ 0x00C71FFF, 0x0006000F, 0x0 },
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{ 0x00AAAFFF, 0x000E000A, 0x0 },
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{ 0x00FFFFFF, 0x00020011, 0x0 },
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{ 0x00DB6FFF, 0x0005000F, 0x0 },
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{ 0x00BEEFFF, 0x000A000C, 0x0 },
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{ 0x00FFFFFF, 0x0005000F, 0x0 },
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{ 0x00DB6FFF, 0x000A000C, 0x0 },
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2013-11-03 04:07:42 +00:00
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};
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2014-08-27 13:27:30 +00:00
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static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
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2015-06-25 08:11:03 +00:00
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{ 0x00FFFFFF, 0x0007000E, 0x0 },
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{ 0x00D75FFF, 0x000E000A, 0x0 },
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{ 0x00BEFFFF, 0x00140006, 0x0 },
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{ 0x80B2CFFF, 0x001B0002, 0x0 },
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{ 0x00FFFFFF, 0x000E000A, 0x0 },
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{ 0x00DB6FFF, 0x00160005, 0x0 },
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{ 0x80C71FFF, 0x001A0002, 0x0 },
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{ 0x00F7DFFF, 0x00180004, 0x0 },
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{ 0x80D75FFF, 0x001B0002, 0x0 },
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2013-11-03 04:07:41 +00:00
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};
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2014-08-27 13:27:30 +00:00
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static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
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2015-06-25 08:11:03 +00:00
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{ 0x00FFFFFF, 0x0001000E, 0x0 },
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{ 0x00D75FFF, 0x0004000A, 0x0 },
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{ 0x00C30FFF, 0x00070006, 0x0 },
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{ 0x00AAAFFF, 0x000C0000, 0x0 },
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{ 0x00FFFFFF, 0x0004000A, 0x0 },
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{ 0x00D75FFF, 0x00090004, 0x0 },
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{ 0x00C30FFF, 0x000C0000, 0x0 },
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{ 0x00FFFFFF, 0x00070006, 0x0 },
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{ 0x00D75FFF, 0x000C0000, 0x0 },
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2013-11-03 04:07:41 +00:00
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};
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2014-08-27 13:27:30 +00:00
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static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
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/* Idx NT mV d T mV df db */
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2015-06-25 08:11:03 +00:00
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{ 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
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{ 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
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{ 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
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{ 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
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{ 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
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{ 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
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{ 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
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{ 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
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{ 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
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{ 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
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2014-08-01 10:07:55 +00:00
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};
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2015-08-24 23:48:44 +00:00
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/* Skylake H and S */
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2013-12-03 13:56:25 +00:00
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static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
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2015-06-25 08:11:03 +00:00
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{ 0x00002016, 0x000000A0, 0x0 },
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{ 0x00005012, 0x0000009B, 0x0 },
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{ 0x00007011, 0x00000088, 0x0 },
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2016-01-05 19:18:55 +00:00
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{ 0x80009010, 0x000000C0, 0x1 },
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2015-06-25 08:11:03 +00:00
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{ 0x00002016, 0x0000009B, 0x0 },
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{ 0x00005012, 0x00000088, 0x0 },
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2016-01-05 19:18:55 +00:00
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{ 0x80007011, 0x000000C0, 0x1 },
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2015-06-25 08:11:03 +00:00
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{ 0x00002016, 0x000000DF, 0x0 },
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2016-01-05 19:18:55 +00:00
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{ 0x80005012, 0x000000C0, 0x1 },
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2013-12-03 13:56:25 +00:00
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};
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2015-06-25 08:11:03 +00:00
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/* Skylake U */
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static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
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2015-08-24 23:48:44 +00:00
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{ 0x0000201B, 0x000000A2, 0x0 },
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2015-06-25 08:11:03 +00:00
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{ 0x00005012, 0x00000088, 0x0 },
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2016-08-02 12:21:57 +00:00
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{ 0x80007011, 0x000000CD, 0x1 },
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2016-01-05 19:18:55 +00:00
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{ 0x80009010, 0x000000C0, 0x1 },
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2015-08-24 23:48:44 +00:00
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{ 0x0000201B, 0x0000009D, 0x0 },
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2016-01-05 19:18:55 +00:00
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{ 0x80005012, 0x000000C0, 0x1 },
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{ 0x80007011, 0x000000C0, 0x1 },
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2015-06-25 08:11:03 +00:00
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{ 0x00002016, 0x00000088, 0x0 },
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2016-01-05 19:18:55 +00:00
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{ 0x80005012, 0x000000C0, 0x1 },
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2015-06-25 08:11:03 +00:00
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};
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2015-08-24 23:48:44 +00:00
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/* Skylake Y */
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static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
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2015-06-25 08:11:03 +00:00
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{ 0x00000018, 0x000000A2, 0x0 },
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{ 0x00005012, 0x00000088, 0x0 },
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2016-08-02 12:21:57 +00:00
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{ 0x80007011, 0x000000CD, 0x3 },
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2016-01-05 19:18:55 +00:00
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{ 0x80009010, 0x000000C0, 0x3 },
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2015-06-25 08:11:03 +00:00
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{ 0x00000018, 0x0000009D, 0x0 },
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2016-01-05 19:18:55 +00:00
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{ 0x80005012, 0x000000C0, 0x3 },
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{ 0x80007011, 0x000000C0, 0x3 },
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2015-06-25 08:11:03 +00:00
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{ 0x00000018, 0x00000088, 0x0 },
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2016-01-05 19:18:55 +00:00
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{ 0x80005012, 0x000000C0, 0x3 },
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2015-06-25 08:11:03 +00:00
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};
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/*
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2015-08-24 23:48:44 +00:00
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* Skylake H and S
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2015-06-25 08:11:03 +00:00
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* eDP 1.4 low vswing translation parameters
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*/
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2015-02-25 04:59:12 +00:00
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static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
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2015-06-25 08:11:03 +00:00
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{ 0x00000018, 0x000000A8, 0x0 },
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{ 0x00004013, 0x000000A9, 0x0 },
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{ 0x00007011, 0x000000A2, 0x0 },
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{ 0x00009010, 0x0000009C, 0x0 },
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{ 0x00000018, 0x000000A9, 0x0 },
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{ 0x00006013, 0x000000A2, 0x0 },
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{ 0x00007011, 0x000000A6, 0x0 },
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{ 0x00000018, 0x000000AB, 0x0 },
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{ 0x00007013, 0x0000009F, 0x0 },
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{ 0x00000018, 0x000000DF, 0x0 },
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};
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/*
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* Skylake U
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* eDP 1.4 low vswing translation parameters
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*/
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static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
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{ 0x00000018, 0x000000A8, 0x0 },
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{ 0x00004013, 0x000000A9, 0x0 },
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{ 0x00007011, 0x000000A2, 0x0 },
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{ 0x00009010, 0x0000009C, 0x0 },
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{ 0x00000018, 0x000000A9, 0x0 },
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{ 0x00006013, 0x000000A2, 0x0 },
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{ 0x00007011, 0x000000A6, 0x0 },
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{ 0x00002016, 0x000000AB, 0x0 },
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{ 0x00005013, 0x0000009F, 0x0 },
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{ 0x00000018, 0x000000DF, 0x0 },
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2015-02-25 04:59:12 +00:00
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};
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2015-06-25 08:11:03 +00:00
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/*
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2015-08-24 23:48:44 +00:00
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* Skylake Y
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2015-06-25 08:11:03 +00:00
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* eDP 1.4 low vswing translation parameters
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*/
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2015-08-24 23:48:44 +00:00
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static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
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2015-06-25 08:11:03 +00:00
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{ 0x00000018, 0x000000A8, 0x0 },
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{ 0x00004013, 0x000000AB, 0x0 },
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{ 0x00007011, 0x000000A4, 0x0 },
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{ 0x00009010, 0x000000DF, 0x0 },
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{ 0x00000018, 0x000000AA, 0x0 },
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{ 0x00006013, 0x000000A4, 0x0 },
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{ 0x00007011, 0x0000009D, 0x0 },
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{ 0x00000018, 0x000000A0, 0x0 },
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{ 0x00006012, 0x000000DF, 0x0 },
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{ 0x00000018, 0x0000008A, 0x0 },
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};
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2015-02-25 04:59:12 +00:00
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2015-08-24 23:48:44 +00:00
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/* Skylake U, H and S */
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2013-12-03 13:56:25 +00:00
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static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
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2015-06-25 08:11:03 +00:00
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{ 0x00000018, 0x000000AC, 0x0 },
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{ 0x00005012, 0x0000009D, 0x0 },
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{ 0x00007011, 0x00000088, 0x0 },
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{ 0x00000018, 0x000000A1, 0x0 },
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{ 0x00000018, 0x00000098, 0x0 },
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{ 0x00004013, 0x00000088, 0x0 },
|
2016-01-05 19:11:27 +00:00
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{ 0x80006012, 0x000000CD, 0x1 },
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2015-06-25 08:11:03 +00:00
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{ 0x00000018, 0x000000DF, 0x0 },
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2016-01-05 19:11:27 +00:00
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{ 0x80003015, 0x000000CD, 0x1 }, /* Default */
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{ 0x80003015, 0x000000C0, 0x1 },
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{ 0x80000018, 0x000000C0, 0x1 },
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2015-06-25 08:11:03 +00:00
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};
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2015-08-24 23:48:44 +00:00
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/* Skylake Y */
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static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
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2015-06-25 08:11:03 +00:00
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{ 0x00000018, 0x000000A1, 0x0 },
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{ 0x00005012, 0x000000DF, 0x0 },
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2016-01-05 19:11:27 +00:00
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{ 0x80007011, 0x000000CB, 0x3 },
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2015-06-25 08:11:03 +00:00
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{ 0x00000018, 0x000000A4, 0x0 },
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{ 0x00000018, 0x0000009D, 0x0 },
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{ 0x00004013, 0x00000080, 0x0 },
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2016-01-05 19:11:27 +00:00
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{ 0x80006013, 0x000000C0, 0x3 },
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2015-06-25 08:11:03 +00:00
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{ 0x00000018, 0x0000008A, 0x0 },
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2016-01-05 19:11:27 +00:00
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{ 0x80003015, 0x000000C0, 0x3 }, /* Default */
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{ 0x80003015, 0x000000C0, 0x3 },
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|
|
{ 0x80000018, 0x000000C0, 0x3 },
|
2013-12-03 13:56:25 +00:00
|
|
|
};
|
|
|
|
|
2014-11-18 10:15:27 +00:00
|
|
|
struct bxt_ddi_buf_trans {
|
|
|
|
u32 margin; /* swing value */
|
|
|
|
u32 scale; /* scale value */
|
|
|
|
u32 enable; /* scale enable */
|
|
|
|
u32 deemphasis;
|
|
|
|
bool default_index; /* true if the entry represents default value */
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
|
|
|
|
/* Idx NT mV diff db */
|
2015-06-04 15:01:35 +00:00
|
|
|
{ 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
|
|
|
|
{ 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
|
|
|
|
{ 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
|
|
|
|
{ 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
|
|
|
|
{ 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
|
|
|
|
{ 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
|
|
|
|
{ 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
|
|
|
|
{ 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
|
|
|
|
{ 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
|
2015-06-25 08:11:03 +00:00
|
|
|
{ 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
|
2014-11-18 10:15:27 +00:00
|
|
|
};
|
|
|
|
|
2015-09-24 04:54:56 +00:00
|
|
|
static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
|
|
|
|
/* Idx NT mV diff db */
|
|
|
|
{ 26, 0, 0, 128, false }, /* 0: 200 0 */
|
|
|
|
{ 38, 0, 0, 112, false }, /* 1: 200 1.5 */
|
|
|
|
{ 48, 0, 0, 96, false }, /* 2: 200 4 */
|
|
|
|
{ 54, 0, 0, 69, false }, /* 3: 200 6 */
|
|
|
|
{ 32, 0, 0, 128, false }, /* 4: 250 0 */
|
|
|
|
{ 48, 0, 0, 104, false }, /* 5: 250 1.5 */
|
|
|
|
{ 54, 0, 0, 85, false }, /* 6: 250 4 */
|
|
|
|
{ 43, 0, 0, 128, false }, /* 7: 300 0 */
|
|
|
|
{ 54, 0, 0, 101, false }, /* 8: 300 1.5 */
|
|
|
|
{ 48, 0, 0, 128, false }, /* 9: 300 0 */
|
|
|
|
};
|
|
|
|
|
2014-11-18 10:15:27 +00:00
|
|
|
/* BSpec has 2 recommended values - entries 0 and 8.
|
|
|
|
* Using the entry with higher vswing.
|
|
|
|
*/
|
|
|
|
static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
|
|
|
|
/* Idx NT mV diff db */
|
2015-06-04 15:01:35 +00:00
|
|
|
{ 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
|
|
|
|
{ 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
|
|
|
|
{ 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
|
|
|
|
{ 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
|
|
|
|
{ 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
|
|
|
|
{ 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
|
|
|
|
{ 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
|
|
|
|
{ 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
|
|
|
|
{ 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
|
2014-11-18 10:15:27 +00:00
|
|
|
{ 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
|
|
|
|
};
|
|
|
|
|
2016-07-12 12:59:35 +00:00
|
|
|
enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
|
2012-10-05 15:05:54 +00:00
|
|
|
{
|
2016-07-12 12:59:35 +00:00
|
|
|
switch (encoder->type) {
|
2015-09-29 07:24:26 +00:00
|
|
|
case INTEL_OUTPUT_DP_MST:
|
2016-07-12 12:59:35 +00:00
|
|
|
return enc_to_mst(&encoder->base)->primary->port;
|
2016-06-22 18:57:06 +00:00
|
|
|
case INTEL_OUTPUT_DP:
|
2015-09-29 07:24:26 +00:00
|
|
|
case INTEL_OUTPUT_EDP:
|
|
|
|
case INTEL_OUTPUT_HDMI:
|
|
|
|
case INTEL_OUTPUT_UNKNOWN:
|
2016-07-12 12:59:35 +00:00
|
|
|
return enc_to_dig_port(&encoder->base)->port;
|
2015-09-29 07:24:26 +00:00
|
|
|
case INTEL_OUTPUT_ANALOG:
|
2016-07-12 12:59:35 +00:00
|
|
|
return PORT_E;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(encoder->type);
|
|
|
|
return PORT_A;
|
2012-10-05 15:05:54 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-07-12 12:59:36 +00:00
|
|
|
static const struct ddi_buf_trans *
|
|
|
|
bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
|
|
|
|
{
|
|
|
|
if (dev_priv->vbt.edp.low_vswing) {
|
|
|
|
*n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
|
|
|
|
return bdw_ddi_translations_edp;
|
|
|
|
} else {
|
|
|
|
*n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
|
|
|
|
return bdw_ddi_translations_dp;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-12-08 17:59:39 +00:00
|
|
|
static const struct ddi_buf_trans *
|
2015-12-08 17:59:41 +00:00
|
|
|
skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
|
2015-06-25 08:11:03 +00:00
|
|
|
{
|
2015-12-08 17:59:41 +00:00
|
|
|
if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
|
2015-08-24 23:48:44 +00:00
|
|
|
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
|
2015-12-08 17:59:39 +00:00
|
|
|
return skl_y_ddi_translations_dp;
|
2015-12-08 17:59:41 +00:00
|
|
|
} else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
|
2015-06-25 08:11:03 +00:00
|
|
|
*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
|
2015-12-08 17:59:39 +00:00
|
|
|
return skl_u_ddi_translations_dp;
|
2015-06-25 08:11:03 +00:00
|
|
|
} else {
|
|
|
|
*n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
|
2015-12-08 17:59:39 +00:00
|
|
|
return skl_ddi_translations_dp;
|
2015-06-25 08:11:03 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-12-08 17:59:39 +00:00
|
|
|
static const struct ddi_buf_trans *
|
2015-12-08 17:59:41 +00:00
|
|
|
skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
|
2015-06-25 08:11:03 +00:00
|
|
|
{
|
2016-03-24 15:50:21 +00:00
|
|
|
if (dev_priv->vbt.edp.low_vswing) {
|
2015-12-08 17:59:41 +00:00
|
|
|
if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
|
2015-08-24 23:48:44 +00:00
|
|
|
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
|
2015-12-08 17:59:39 +00:00
|
|
|
return skl_y_ddi_translations_edp;
|
2015-12-08 17:59:41 +00:00
|
|
|
} else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
|
2015-06-25 08:11:03 +00:00
|
|
|
*n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
|
2015-12-08 17:59:39 +00:00
|
|
|
return skl_u_ddi_translations_edp;
|
2015-06-25 08:11:03 +00:00
|
|
|
} else {
|
|
|
|
*n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
|
2015-12-08 17:59:39 +00:00
|
|
|
return skl_ddi_translations_edp;
|
2015-06-25 08:11:03 +00:00
|
|
|
}
|
|
|
|
}
|
2015-12-08 17:59:40 +00:00
|
|
|
|
2015-12-08 17:59:41 +00:00
|
|
|
return skl_get_buf_trans_dp(dev_priv, n_entries);
|
2015-06-25 08:11:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct ddi_buf_trans *
|
2015-12-08 17:59:41 +00:00
|
|
|
skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
|
2015-06-25 08:11:03 +00:00
|
|
|
{
|
2015-12-08 17:59:41 +00:00
|
|
|
if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
|
2015-08-24 23:48:44 +00:00
|
|
|
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
|
2015-12-08 17:59:39 +00:00
|
|
|
return skl_y_ddi_translations_hdmi;
|
2015-06-25 08:11:03 +00:00
|
|
|
} else {
|
|
|
|
*n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
|
2015-12-08 17:59:39 +00:00
|
|
|
return skl_ddi_translations_hdmi;
|
2015-06-25 08:11:03 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-07-12 12:59:30 +00:00
|
|
|
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
|
|
|
|
{
|
|
|
|
int n_hdmi_entries;
|
|
|
|
int hdmi_level;
|
|
|
|
int hdmi_default_entry;
|
|
|
|
|
|
|
|
hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
|
|
|
|
|
|
|
|
if (IS_BROXTON(dev_priv))
|
|
|
|
return hdmi_level;
|
|
|
|
|
|
|
|
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
|
|
|
|
skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
|
|
|
|
hdmi_default_entry = 8;
|
|
|
|
} else if (IS_BROADWELL(dev_priv)) {
|
|
|
|
n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
|
|
|
|
hdmi_default_entry = 7;
|
|
|
|
} else if (IS_HASWELL(dev_priv)) {
|
|
|
|
n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
|
|
|
|
hdmi_default_entry = 6;
|
|
|
|
} else {
|
|
|
|
WARN(1, "ddi translation table missing\n");
|
|
|
|
n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
|
|
|
|
hdmi_default_entry = 7;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Choose a good default if VBT is badly populated */
|
|
|
|
if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
|
|
|
|
hdmi_level >= n_hdmi_entries)
|
|
|
|
hdmi_level = hdmi_default_entry;
|
|
|
|
|
|
|
|
return hdmi_level;
|
|
|
|
}
|
|
|
|
|
2013-11-03 04:07:41 +00:00
|
|
|
/*
|
|
|
|
* Starting with Haswell, DDI port buffers must be programmed with correct
|
2016-07-12 12:59:33 +00:00
|
|
|
* values in advance. This function programs the correct values for
|
|
|
|
* DP/eDP/FDI use cases.
|
2012-05-09 18:37:20 +00:00
|
|
|
*/
|
2016-07-12 12:59:33 +00:00
|
|
|
void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
|
2012-05-09 18:37:20 +00:00
|
|
|
{
|
2015-12-08 17:59:44 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2015-07-10 11:10:55 +00:00
|
|
|
u32 iboost_bit = 0;
|
2016-07-12 12:59:33 +00:00
|
|
|
int i, n_dp_entries, n_edp_entries, size;
|
|
|
|
enum port port = intel_ddi_get_encoder_port(encoder);
|
2014-08-27 13:27:30 +00:00
|
|
|
const struct ddi_buf_trans *ddi_translations_fdi;
|
|
|
|
const struct ddi_buf_trans *ddi_translations_dp;
|
|
|
|
const struct ddi_buf_trans *ddi_translations_edp;
|
|
|
|
const struct ddi_buf_trans *ddi_translations;
|
2013-11-03 04:07:41 +00:00
|
|
|
|
2016-07-12 12:59:31 +00:00
|
|
|
if (IS_BROXTON(dev_priv))
|
2014-11-18 10:15:27 +00:00
|
|
|
return;
|
2015-12-08 17:59:44 +00:00
|
|
|
|
|
|
|
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
|
2015-07-03 15:31:30 +00:00
|
|
|
ddi_translations_fdi = NULL;
|
2015-06-25 08:11:03 +00:00
|
|
|
ddi_translations_dp =
|
2015-12-08 17:59:41 +00:00
|
|
|
skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
|
2015-06-25 08:11:03 +00:00
|
|
|
ddi_translations_edp =
|
2015-12-08 17:59:41 +00:00
|
|
|
skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
|
2016-07-12 12:59:33 +00:00
|
|
|
|
2015-07-10 11:10:55 +00:00
|
|
|
/* If we're boosting the current, set bit 31 of trans1 */
|
2016-07-12 12:59:34 +00:00
|
|
|
if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
|
2016-07-12 12:59:29 +00:00
|
|
|
iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
|
2015-12-08 17:59:43 +00:00
|
|
|
|
2016-01-12 15:28:16 +00:00
|
|
|
if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
|
|
|
|
port != PORT_A && port != PORT_E &&
|
|
|
|
n_edp_entries > 9))
|
2015-12-08 17:59:43 +00:00
|
|
|
n_edp_entries = 9;
|
2015-12-08 17:59:41 +00:00
|
|
|
} else if (IS_BROADWELL(dev_priv)) {
|
2013-11-03 04:07:41 +00:00
|
|
|
ddi_translations_fdi = bdw_ddi_translations_fdi;
|
|
|
|
ddi_translations_dp = bdw_ddi_translations_dp;
|
2016-07-12 12:59:36 +00:00
|
|
|
ddi_translations_edp = bdw_get_buf_trans_edp(dev_priv, &n_edp_entries);
|
2015-02-25 04:59:12 +00:00
|
|
|
n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
|
2015-12-08 17:59:41 +00:00
|
|
|
} else if (IS_HASWELL(dev_priv)) {
|
2013-11-03 04:07:41 +00:00
|
|
|
ddi_translations_fdi = hsw_ddi_translations_fdi;
|
|
|
|
ddi_translations_dp = hsw_ddi_translations_dp;
|
2013-11-03 04:07:42 +00:00
|
|
|
ddi_translations_edp = hsw_ddi_translations_dp;
|
2015-02-25 04:59:12 +00:00
|
|
|
n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
|
2013-11-03 04:07:41 +00:00
|
|
|
} else {
|
|
|
|
WARN(1, "ddi translation table missing\n");
|
2013-11-03 04:07:42 +00:00
|
|
|
ddi_translations_edp = bdw_ddi_translations_dp;
|
2013-11-03 04:07:41 +00:00
|
|
|
ddi_translations_fdi = bdw_ddi_translations_fdi;
|
|
|
|
ddi_translations_dp = bdw_ddi_translations_dp;
|
2015-02-25 04:59:12 +00:00
|
|
|
n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
|
|
|
|
n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
|
2013-11-03 04:07:41 +00:00
|
|
|
}
|
|
|
|
|
2015-12-08 17:59:44 +00:00
|
|
|
switch (encoder->type) {
|
|
|
|
case INTEL_OUTPUT_EDP:
|
2013-11-03 04:07:42 +00:00
|
|
|
ddi_translations = ddi_translations_edp;
|
2015-02-25 04:59:12 +00:00
|
|
|
size = n_edp_entries;
|
2013-11-03 04:07:42 +00:00
|
|
|
break;
|
2016-06-22 18:57:06 +00:00
|
|
|
case INTEL_OUTPUT_DP:
|
2013-11-03 04:07:42 +00:00
|
|
|
ddi_translations = ddi_translations_dp;
|
2015-02-25 04:59:12 +00:00
|
|
|
size = n_dp_entries;
|
2013-11-03 04:07:42 +00:00
|
|
|
break;
|
2015-12-08 17:59:44 +00:00
|
|
|
case INTEL_OUTPUT_ANALOG:
|
|
|
|
ddi_translations = ddi_translations_fdi;
|
2015-02-25 04:59:12 +00:00
|
|
|
size = n_dp_entries;
|
2013-11-03 04:07:42 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
2012-05-09 18:37:20 +00:00
|
|
|
|
2015-09-18 17:03:22 +00:00
|
|
|
for (i = 0; i < size; i++) {
|
|
|
|
I915_WRITE(DDI_BUF_TRANS_LO(port, i),
|
|
|
|
ddi_translations[i].trans1 | iboost_bit);
|
|
|
|
I915_WRITE(DDI_BUF_TRANS_HI(port, i),
|
|
|
|
ddi_translations[i].trans2);
|
2012-05-09 18:37:20 +00:00
|
|
|
}
|
2016-07-12 12:59:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Starting with Haswell, DDI port buffers must be programmed with correct
|
|
|
|
* values in advance. This function programs the correct values for
|
|
|
|
* HDMI/DVI use cases.
|
|
|
|
*/
|
|
|
|
static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
u32 iboost_bit = 0;
|
|
|
|
int n_hdmi_entries, hdmi_level;
|
|
|
|
enum port port = intel_ddi_get_encoder_port(encoder);
|
|
|
|
const struct ddi_buf_trans *ddi_translations_hdmi;
|
2014-08-01 10:07:54 +00:00
|
|
|
|
2016-07-12 12:59:33 +00:00
|
|
|
if (IS_BROXTON(dev_priv))
|
2014-08-04 14:04:43 +00:00
|
|
|
return;
|
|
|
|
|
2016-07-12 12:59:33 +00:00
|
|
|
hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
|
|
|
|
|
|
|
|
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
|
|
|
|
ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
|
2016-07-12 12:59:34 +00:00
|
|
|
|
2016-07-12 12:59:33 +00:00
|
|
|
/* If we're boosting the current, set bit 31 of trans1 */
|
2016-07-12 12:59:34 +00:00
|
|
|
if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
|
2016-07-12 12:59:33 +00:00
|
|
|
iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
|
|
|
|
} else if (IS_BROADWELL(dev_priv)) {
|
|
|
|
ddi_translations_hdmi = bdw_ddi_translations_hdmi;
|
|
|
|
n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
|
|
|
|
} else if (IS_HASWELL(dev_priv)) {
|
|
|
|
ddi_translations_hdmi = hsw_ddi_translations_hdmi;
|
|
|
|
n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
|
|
|
|
} else {
|
|
|
|
WARN(1, "ddi translation table missing\n");
|
|
|
|
ddi_translations_hdmi = bdw_ddi_translations_hdmi;
|
|
|
|
n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
|
|
|
|
}
|
|
|
|
|
2013-09-12 20:06:24 +00:00
|
|
|
/* Entry 9 is for HDMI: */
|
2016-07-12 12:59:32 +00:00
|
|
|
I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
|
2015-09-18 17:03:22 +00:00
|
|
|
ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
|
2016-07-12 12:59:32 +00:00
|
|
|
I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
|
2015-09-18 17:03:22 +00:00
|
|
|
ddi_translations_hdmi[hdmi_level].trans2);
|
2012-05-09 18:37:20 +00:00
|
|
|
}
|
|
|
|
|
2012-11-29 13:29:31 +00:00
|
|
|
static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
|
|
|
{
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
i915_reg_t reg = DDI_BUF_CTL(port);
|
2012-11-29 13:29:31 +00:00
|
|
|
int i;
|
|
|
|
|
2015-03-27 12:19:09 +00:00
|
|
|
for (i = 0; i < 16; i++) {
|
2012-11-29 13:29:31 +00:00
|
|
|
udelay(1);
|
|
|
|
if (I915_READ(reg) & DDI_BUF_IS_IDLE)
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
|
|
|
|
}
|
2012-05-09 18:37:21 +00:00
|
|
|
|
2016-09-01 22:08:07 +00:00
|
|
|
static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
|
|
|
|
{
|
|
|
|
switch (pll->id) {
|
|
|
|
case DPLL_ID_WRPLL1:
|
|
|
|
return PORT_CLK_SEL_WRPLL1;
|
|
|
|
case DPLL_ID_WRPLL2:
|
|
|
|
return PORT_CLK_SEL_WRPLL2;
|
|
|
|
case DPLL_ID_SPLL:
|
|
|
|
return PORT_CLK_SEL_SPLL;
|
|
|
|
case DPLL_ID_LCPLL_810:
|
|
|
|
return PORT_CLK_SEL_LCPLL_810;
|
|
|
|
case DPLL_ID_LCPLL_1350:
|
|
|
|
return PORT_CLK_SEL_LCPLL_1350;
|
|
|
|
case DPLL_ID_LCPLL_2700:
|
|
|
|
return PORT_CLK_SEL_LCPLL_2700;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(pll->id);
|
|
|
|
return PORT_CLK_SEL_NONE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-05-09 18:37:21 +00:00
|
|
|
/* Starting with Haswell, different DDI ports can work in FDI mode for
|
|
|
|
* connection to the PCH-located connectors. For this, it is necessary to train
|
|
|
|
* both the DDI port and PCH receiver for the desired DDI buffer settings.
|
|
|
|
*
|
|
|
|
* The recommended port to work in FDI mode is DDI E, which we use here. Also,
|
|
|
|
* please note that when FDI mode is active on DDI E, it shares 2 lines with
|
|
|
|
* DDI A (which is used for eDP)
|
|
|
|
*/
|
|
|
|
|
|
|
|
void hsw_fdi_link_train(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2012-05-09 18:37:21 +00:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
2015-12-08 17:59:44 +00:00
|
|
|
struct intel_encoder *encoder;
|
2016-09-01 22:08:07 +00:00
|
|
|
u32 temp, i, rx_ctl_val, ddi_pll_sel;
|
2012-05-09 18:37:21 +00:00
|
|
|
|
2015-12-08 17:59:44 +00:00
|
|
|
for_each_encoder_on_crtc(dev, crtc, encoder) {
|
|
|
|
WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
|
2016-07-12 12:59:33 +00:00
|
|
|
intel_prepare_dp_ddi_buffers(encoder);
|
2015-12-08 17:59:44 +00:00
|
|
|
}
|
|
|
|
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
|
|
|
|
* mode set "sequence for CRT port" document:
|
|
|
|
* - TP1 to TP2 time with the default value
|
|
|
|
* - FDI delay to 90h
|
2013-05-03 17:48:11 +00:00
|
|
|
*
|
|
|
|
* WaFDIAutoLinkSetTimingOverrride:hsw
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
*/
|
2015-09-18 17:03:30 +00:00
|
|
|
I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
FDI_RX_PWRDN_LANE0_VAL(2) |
|
|
|
|
FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
|
|
|
|
|
|
|
|
/* Enable the PCH Receiver FDI PLL */
|
2012-12-11 18:48:29 +00:00
|
|
|
rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
|
2013-02-13 17:04:45 +00:00
|
|
|
FDI_RX_PLL_ENABLE |
|
2015-01-15 12:55:25 +00:00
|
|
|
FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
|
2015-09-18 17:03:30 +00:00
|
|
|
I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
|
|
|
|
POSTING_READ(FDI_RX_CTL(PIPE_A));
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
udelay(220);
|
|
|
|
|
|
|
|
/* Switch from Rawclk to PCDclk */
|
|
|
|
rx_ctl_val |= FDI_PCDCLK;
|
2015-09-18 17:03:30 +00:00
|
|
|
I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
|
|
|
|
/* Configure Port Clock Select */
|
2016-09-01 22:08:07 +00:00
|
|
|
ddi_pll_sel = hsw_pll_to_ddi_pll_sel(intel_crtc->config->shared_dpll);
|
|
|
|
I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
|
|
|
|
WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
|
|
|
|
/* Start the training iterating through available voltages and emphasis,
|
|
|
|
* testing each value twice. */
|
2014-08-27 13:27:30 +00:00
|
|
|
for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
|
2012-05-09 18:37:21 +00:00
|
|
|
/* Configure DP_TP_CTL with auto-training */
|
|
|
|
I915_WRITE(DP_TP_CTL(PORT_E),
|
|
|
|
DP_TP_CTL_FDI_AUTOTRAIN |
|
|
|
|
DP_TP_CTL_ENHANCED_FRAME_ENABLE |
|
|
|
|
DP_TP_CTL_LINK_TRAIN_PAT1 |
|
|
|
|
DP_TP_CTL_ENABLE);
|
|
|
|
|
2012-12-11 18:48:30 +00:00
|
|
|
/* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
|
|
|
|
* DDI E does not support port reversal, the functionality is
|
|
|
|
* achieved on the PCH side in FDI_RX_CTL, so no need to set the
|
|
|
|
* port reversal bit */
|
2012-05-09 18:37:21 +00:00
|
|
|
I915_WRITE(DDI_BUF_CTL(PORT_E),
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
DDI_BUF_CTL_ENABLE |
|
2015-01-15 12:55:25 +00:00
|
|
|
((intel_crtc->config->fdi_lanes - 1) << 1) |
|
2014-08-11 03:27:36 +00:00
|
|
|
DDI_BUF_TRANS_SELECT(i / 2));
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
POSTING_READ(DDI_BUF_CTL(PORT_E));
|
2012-05-09 18:37:21 +00:00
|
|
|
|
|
|
|
udelay(600);
|
|
|
|
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
/* Program PCH FDI Receiver TU */
|
2015-09-18 17:03:30 +00:00
|
|
|
I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
|
|
|
|
/* Enable PCH FDI Receiver with auto-training */
|
|
|
|
rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
|
2015-09-18 17:03:30 +00:00
|
|
|
I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
|
|
|
|
POSTING_READ(FDI_RX_CTL(PIPE_A));
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
|
|
|
|
/* Wait for FDI receiver lane calibration */
|
|
|
|
udelay(30);
|
|
|
|
|
|
|
|
/* Unset FDI_RX_MISC pwrdn lanes */
|
2015-09-18 17:03:30 +00:00
|
|
|
temp = I915_READ(FDI_RX_MISC(PIPE_A));
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
|
2015-09-18 17:03:30 +00:00
|
|
|
I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
|
|
|
|
POSTING_READ(FDI_RX_MISC(PIPE_A));
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
|
|
|
|
/* Wait for FDI auto training time */
|
|
|
|
udelay(5);
|
2012-05-09 18:37:21 +00:00
|
|
|
|
|
|
|
temp = I915_READ(DP_TP_STATUS(PORT_E));
|
|
|
|
if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
|
2015-12-04 20:22:50 +00:00
|
|
|
break;
|
|
|
|
}
|
2012-05-09 18:37:21 +00:00
|
|
|
|
2015-12-04 20:22:50 +00:00
|
|
|
/*
|
|
|
|
* Leave things enabled even if we failed to train FDI.
|
|
|
|
* Results in less fireworks from the state checker.
|
|
|
|
*/
|
|
|
|
if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
|
|
|
|
DRM_ERROR("FDI link training failed!\n");
|
|
|
|
break;
|
2012-05-09 18:37:21 +00:00
|
|
|
}
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
|
drm/i915: Disable FDI RX before DDI_BUF_CTL
Bspec is confused w.r.t. the HSW/BDW FDI disable sequence. It lists
FDI RX disable both as step 13 and step 18 in the sequence. But I dug
up an old BUN mail from Art that moved the FDI RX disable to happen
before DDI_BUF_CTL disable. That BUN did not renumber the steps and just
added a note:
"Workaround: Disable PCH FDI Receiver before disabling DDI_BUF_CTL."
The BUN described the symptoms of the fixed issue as:
"PCH display underflow and a black screen on the analog CRT port that
happened after a FDI re-train"
I suppose later someone tried to renumber the steps to match, but forgot
to remove the FDI RX disable from its old position in the sequence.
They also forgot to update the note describing what should be done in
case of an FDI training failure. Currently it says:
"To retry FDI training, follow the Disable Sequence steps to Disable FDI,
but skip the steps related to clocks and PLLs (16, 19, and 20), ..."
It should really say "17, 20, and 21" with the current sequence because
those are the steps that deal with PLLs and whatnot, after step 13 became
FDI RX disable. And had the step 18 FDI RX disable been removed, as I
suspect it should have, the note should actually say "17, 19, and 20".
So, let's move the FDI RX disable to happen before DDI_BUF_CTL disable,
as that would appear to be the correct order based on the BUN.
Note that Art has since unconfused the spec, and so this patch should
now match the steps listed in the spec.
v2: Add a note that the spec is now correct
Cc: Paulo Zanoni <przanoni@gmail.com>
Cc: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456841783-4779-1-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2016-03-01 14:16:23 +00:00
|
|
|
rx_ctl_val &= ~FDI_RX_ENABLE;
|
|
|
|
I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
|
|
|
|
POSTING_READ(FDI_RX_CTL(PIPE_A));
|
|
|
|
|
2012-11-29 13:29:31 +00:00
|
|
|
temp = I915_READ(DDI_BUF_CTL(PORT_E));
|
|
|
|
temp &= ~DDI_BUF_CTL_ENABLE;
|
|
|
|
I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
|
|
|
|
POSTING_READ(DDI_BUF_CTL(PORT_E));
|
|
|
|
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
|
2012-11-29 13:29:31 +00:00
|
|
|
temp = I915_READ(DP_TP_CTL(PORT_E));
|
|
|
|
temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
|
|
|
|
I915_WRITE(DP_TP_CTL(PORT_E), temp);
|
|
|
|
POSTING_READ(DP_TP_CTL(PORT_E));
|
|
|
|
|
|
|
|
intel_wait_ddi_buf_idle(dev_priv, PORT_E);
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
|
|
|
|
/* Reset FDI_RX_MISC pwrdn lanes */
|
2015-09-18 17:03:30 +00:00
|
|
|
temp = I915_READ(FDI_RX_MISC(PIPE_A));
|
drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-11-01 23:00:59 +00:00
|
|
|
temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
|
|
|
|
temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
|
2015-09-18 17:03:30 +00:00
|
|
|
I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
|
|
|
|
POSTING_READ(FDI_RX_MISC(PIPE_A));
|
2012-05-09 18:37:21 +00:00
|
|
|
}
|
|
|
|
|
2015-12-04 20:22:50 +00:00
|
|
|
/* Enable normal pixel sending for FDI */
|
|
|
|
I915_WRITE(DP_TP_CTL(PORT_E),
|
|
|
|
DP_TP_CTL_FDI_AUTOTRAIN |
|
|
|
|
DP_TP_CTL_LINK_TRAIN_NORMAL |
|
|
|
|
DP_TP_CTL_ENHANCED_FRAME_ENABLE |
|
|
|
|
DP_TP_CTL_ENABLE);
|
2012-05-09 18:37:21 +00:00
|
|
|
}
|
2012-05-09 18:37:27 +00:00
|
|
|
|
2014-05-02 03:36:43 +00:00
|
|
|
void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
struct intel_digital_port *intel_dig_port =
|
|
|
|
enc_to_dig_port(&encoder->base);
|
|
|
|
|
|
|
|
intel_dp->DP = intel_dig_port->saved_port_bits |
|
2014-08-11 03:27:36 +00:00
|
|
|
DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
|
2015-08-17 15:05:12 +00:00
|
|
|
intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
|
2014-05-02 03:36:43 +00:00
|
|
|
}
|
|
|
|
|
2012-10-05 15:05:53 +00:00
|
|
|
static struct intel_encoder *
|
|
|
|
intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
struct intel_encoder *intel_encoder, *ret = NULL;
|
|
|
|
int num_encoders = 0;
|
|
|
|
|
|
|
|
for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
|
|
|
|
ret = intel_encoder;
|
|
|
|
num_encoders++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (num_encoders != 1)
|
2013-04-17 14:48:49 +00:00
|
|
|
WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
|
|
|
|
pipe_name(intel_crtc->pipe));
|
2012-10-05 15:05:53 +00:00
|
|
|
|
|
|
|
BUG_ON(ret == NULL);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-08-22 04:19:10 +00:00
|
|
|
struct intel_encoder *
|
2015-03-20 14:18:12 +00:00
|
|
|
intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
|
2014-10-29 09:32:30 +00:00
|
|
|
{
|
2015-03-20 14:18:12 +00:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
|
|
|
|
struct intel_encoder *ret = NULL;
|
|
|
|
struct drm_atomic_state *state;
|
2015-04-21 14:12:59 +00:00
|
|
|
struct drm_connector *connector;
|
|
|
|
struct drm_connector_state *connector_state;
|
2014-10-29 09:32:30 +00:00
|
|
|
int num_encoders = 0;
|
2015-03-20 14:18:12 +00:00
|
|
|
int i;
|
2014-10-29 09:32:30 +00:00
|
|
|
|
2015-03-20 14:18:12 +00:00
|
|
|
state = crtc_state->base.state;
|
|
|
|
|
2015-04-21 14:12:59 +00:00
|
|
|
for_each_connector_in_state(state, connector, connector_state, i) {
|
|
|
|
if (connector_state->crtc != crtc_state->base.crtc)
|
2015-03-20 14:18:12 +00:00
|
|
|
continue;
|
|
|
|
|
2015-04-21 14:12:59 +00:00
|
|
|
ret = to_intel_encoder(connector_state->best_encoder);
|
2015-03-20 14:18:12 +00:00
|
|
|
num_encoders++;
|
2014-10-29 09:32:30 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
|
|
|
|
pipe_name(crtc->pipe));
|
|
|
|
|
|
|
|
BUG_ON(ret == NULL);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-05-10 13:01:51 +00:00
|
|
|
#define LC_FREQ 2700
|
|
|
|
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
|
|
|
|
i915_reg_t reg)
|
2014-01-21 20:42:10 +00:00
|
|
|
{
|
|
|
|
int refclk = LC_FREQ;
|
|
|
|
int n, p, r;
|
|
|
|
u32 wrpll;
|
|
|
|
|
|
|
|
wrpll = I915_READ(reg);
|
2014-06-25 19:01:48 +00:00
|
|
|
switch (wrpll & WRPLL_PLL_REF_MASK) {
|
|
|
|
case WRPLL_PLL_SSC:
|
|
|
|
case WRPLL_PLL_NON_SSC:
|
2014-01-21 20:42:10 +00:00
|
|
|
/*
|
|
|
|
* We could calculate spread here, but our checking
|
|
|
|
* code only cares about 5% accuracy, and spread is a max of
|
|
|
|
* 0.5% downspread.
|
|
|
|
*/
|
|
|
|
refclk = 135;
|
|
|
|
break;
|
2014-06-25 19:01:48 +00:00
|
|
|
case WRPLL_PLL_LCPLL:
|
2014-01-21 20:42:10 +00:00
|
|
|
refclk = LC_FREQ;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN(1, "bad wrpll refclk\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
r = wrpll & WRPLL_DIVIDER_REF_MASK;
|
|
|
|
p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
|
|
|
|
n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
|
|
|
|
|
2014-01-22 20:58:04 +00:00
|
|
|
/* Convert to KHz, p & r have a fixed point portion */
|
|
|
|
return (refclk * n * 100) / (p * r);
|
2014-01-21 20:42:10 +00:00
|
|
|
}
|
|
|
|
|
2014-11-13 14:55:16 +00:00
|
|
|
static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
|
|
|
|
uint32_t dpll)
|
|
|
|
{
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
i915_reg_t cfgcr1_reg, cfgcr2_reg;
|
2014-11-13 14:55:16 +00:00
|
|
|
uint32_t cfgcr1_val, cfgcr2_val;
|
|
|
|
uint32_t p0, p1, p2, dco_freq;
|
|
|
|
|
2015-09-30 14:06:43 +00:00
|
|
|
cfgcr1_reg = DPLL_CFGCR1(dpll);
|
|
|
|
cfgcr2_reg = DPLL_CFGCR2(dpll);
|
2014-11-13 14:55:16 +00:00
|
|
|
|
|
|
|
cfgcr1_val = I915_READ(cfgcr1_reg);
|
|
|
|
cfgcr2_val = I915_READ(cfgcr2_reg);
|
|
|
|
|
|
|
|
p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
|
|
|
|
p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
|
|
|
|
|
|
|
|
if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
|
|
|
|
p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
|
|
|
|
else
|
|
|
|
p1 = 1;
|
|
|
|
|
|
|
|
|
|
|
|
switch (p0) {
|
|
|
|
case DPLL_CFGCR2_PDIV_1:
|
|
|
|
p0 = 1;
|
|
|
|
break;
|
|
|
|
case DPLL_CFGCR2_PDIV_2:
|
|
|
|
p0 = 2;
|
|
|
|
break;
|
|
|
|
case DPLL_CFGCR2_PDIV_3:
|
|
|
|
p0 = 3;
|
|
|
|
break;
|
|
|
|
case DPLL_CFGCR2_PDIV_7:
|
|
|
|
p0 = 7;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (p2) {
|
|
|
|
case DPLL_CFGCR2_KDIV_5:
|
|
|
|
p2 = 5;
|
|
|
|
break;
|
|
|
|
case DPLL_CFGCR2_KDIV_2:
|
|
|
|
p2 = 2;
|
|
|
|
break;
|
|
|
|
case DPLL_CFGCR2_KDIV_3:
|
|
|
|
p2 = 3;
|
|
|
|
break;
|
|
|
|
case DPLL_CFGCR2_KDIV_1:
|
|
|
|
p2 = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
|
|
|
|
|
|
|
|
dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
|
|
|
|
1000) / 0x8000;
|
|
|
|
|
|
|
|
return dco_freq / (p0 * p1 * p2 * 5);
|
|
|
|
}
|
|
|
|
|
2015-06-30 12:33:51 +00:00
|
|
|
static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
|
|
|
|
{
|
|
|
|
int dotclock;
|
|
|
|
|
|
|
|
if (pipe_config->has_pch_encoder)
|
|
|
|
dotclock = intel_dotclock_calculate(pipe_config->port_clock,
|
|
|
|
&pipe_config->fdi_m_n);
|
2016-06-22 18:57:04 +00:00
|
|
|
else if (intel_crtc_has_dp_encoder(pipe_config))
|
2015-06-30 12:33:51 +00:00
|
|
|
dotclock = intel_dotclock_calculate(pipe_config->port_clock,
|
|
|
|
&pipe_config->dp_m_n);
|
|
|
|
else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
|
|
|
|
dotclock = pipe_config->port_clock * 2 / 3;
|
|
|
|
else
|
|
|
|
dotclock = pipe_config->port_clock;
|
|
|
|
|
|
|
|
if (pipe_config->pixel_multiplier)
|
|
|
|
dotclock /= pipe_config->pixel_multiplier;
|
|
|
|
|
|
|
|
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
|
|
|
|
}
|
2014-11-13 14:55:16 +00:00
|
|
|
|
|
|
|
static void skl_ddi_clock_get(struct intel_encoder *encoder,
|
2015-01-15 12:55:21 +00:00
|
|
|
struct intel_crtc_state *pipe_config)
|
2014-11-13 14:55:16 +00:00
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2014-11-13 14:55:16 +00:00
|
|
|
int link_clock = 0;
|
|
|
|
uint32_t dpll_ctl1, dpll;
|
|
|
|
|
2016-09-01 22:08:07 +00:00
|
|
|
dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
|
2014-11-13 14:55:16 +00:00
|
|
|
|
|
|
|
dpll_ctl1 = I915_READ(DPLL_CTRL1);
|
|
|
|
|
|
|
|
if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
|
|
|
|
link_clock = skl_calc_wrpll_link(dev_priv, dpll);
|
|
|
|
} else {
|
2015-04-30 15:39:17 +00:00
|
|
|
link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
|
|
|
|
link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
|
2014-11-13 14:55:16 +00:00
|
|
|
|
|
|
|
switch (link_clock) {
|
2015-04-30 15:39:17 +00:00
|
|
|
case DPLL_CTRL1_LINK_RATE_810:
|
2014-11-13 14:55:16 +00:00
|
|
|
link_clock = 81000;
|
|
|
|
break;
|
2015-04-30 15:39:17 +00:00
|
|
|
case DPLL_CTRL1_LINK_RATE_1080:
|
2015-03-05 04:32:30 +00:00
|
|
|
link_clock = 108000;
|
|
|
|
break;
|
2015-04-30 15:39:17 +00:00
|
|
|
case DPLL_CTRL1_LINK_RATE_1350:
|
2014-11-13 14:55:16 +00:00
|
|
|
link_clock = 135000;
|
|
|
|
break;
|
2015-04-30 15:39:17 +00:00
|
|
|
case DPLL_CTRL1_LINK_RATE_1620:
|
2015-03-05 04:32:30 +00:00
|
|
|
link_clock = 162000;
|
|
|
|
break;
|
2015-04-30 15:39:17 +00:00
|
|
|
case DPLL_CTRL1_LINK_RATE_2160:
|
2015-03-05 04:32:30 +00:00
|
|
|
link_clock = 216000;
|
|
|
|
break;
|
2015-04-30 15:39:17 +00:00
|
|
|
case DPLL_CTRL1_LINK_RATE_2700:
|
2014-11-13 14:55:16 +00:00
|
|
|
link_clock = 270000;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN(1, "Unsupported link rate\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
link_clock *= 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
pipe_config->port_clock = link_clock;
|
|
|
|
|
2015-06-30 12:33:51 +00:00
|
|
|
ddi_dotclock_get(pipe_config);
|
2014-11-13 14:55:16 +00:00
|
|
|
}
|
|
|
|
|
2014-07-29 18:57:08 +00:00
|
|
|
static void hsw_ddi_clock_get(struct intel_encoder *encoder,
|
2015-01-15 12:55:21 +00:00
|
|
|
struct intel_crtc_state *pipe_config)
|
2014-01-21 20:42:10 +00:00
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2014-01-21 20:42:10 +00:00
|
|
|
int link_clock = 0;
|
|
|
|
u32 val, pll;
|
|
|
|
|
2016-09-01 22:08:07 +00:00
|
|
|
val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
|
2014-01-21 20:42:10 +00:00
|
|
|
switch (val & PORT_CLK_SEL_MASK) {
|
|
|
|
case PORT_CLK_SEL_LCPLL_810:
|
|
|
|
link_clock = 81000;
|
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_LCPLL_1350:
|
|
|
|
link_clock = 135000;
|
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_LCPLL_2700:
|
|
|
|
link_clock = 270000;
|
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_WRPLL1:
|
2015-09-18 17:03:33 +00:00
|
|
|
link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
|
2014-01-21 20:42:10 +00:00
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_WRPLL2:
|
2015-09-18 17:03:33 +00:00
|
|
|
link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
|
2014-01-21 20:42:10 +00:00
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_SPLL:
|
|
|
|
pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
|
|
|
|
if (pll == SPLL_PLL_FREQ_810MHz)
|
|
|
|
link_clock = 81000;
|
|
|
|
else if (pll == SPLL_PLL_FREQ_1350MHz)
|
|
|
|
link_clock = 135000;
|
|
|
|
else if (pll == SPLL_PLL_FREQ_2700MHz)
|
|
|
|
link_clock = 270000;
|
|
|
|
else {
|
|
|
|
WARN(1, "bad spll freq\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN(1, "bad port clock sel\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
pipe_config->port_clock = link_clock * 2;
|
|
|
|
|
2015-06-30 12:33:51 +00:00
|
|
|
ddi_dotclock_get(pipe_config);
|
2014-01-21 20:42:10 +00:00
|
|
|
}
|
|
|
|
|
2014-08-22 04:19:12 +00:00
|
|
|
static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
|
|
|
|
enum intel_dpll_id dpll)
|
|
|
|
{
|
2015-06-22 20:35:52 +00:00
|
|
|
struct intel_shared_dpll *pll;
|
|
|
|
struct intel_dpll_hw_state *state;
|
2016-05-04 09:11:57 +00:00
|
|
|
struct dpll clock;
|
2015-06-22 20:35:52 +00:00
|
|
|
|
|
|
|
/* For DDI ports we always use a shared PLL. */
|
|
|
|
if (WARN_ON(dpll == DPLL_ID_PRIVATE))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
pll = &dev_priv->shared_dplls[dpll];
|
|
|
|
state = &pll->config.hw_state;
|
|
|
|
|
|
|
|
clock.m1 = 2;
|
|
|
|
clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
|
|
|
|
if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
|
|
|
|
clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
|
|
|
|
clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
|
|
|
|
clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
|
|
|
|
clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
|
|
|
|
|
|
|
|
return chv_calc_dpll_params(100000, &clock);
|
2014-08-22 04:19:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void bxt_ddi_clock_get(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2014-08-22 04:19:12 +00:00
|
|
|
enum port port = intel_ddi_get_encoder_port(encoder);
|
|
|
|
uint32_t dpll = port;
|
|
|
|
|
2015-06-30 12:33:51 +00:00
|
|
|
pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
|
2014-08-22 04:19:12 +00:00
|
|
|
|
2015-06-30 12:33:51 +00:00
|
|
|
ddi_dotclock_get(pipe_config);
|
2014-08-22 04:19:12 +00:00
|
|
|
}
|
|
|
|
|
2014-07-29 18:57:08 +00:00
|
|
|
void intel_ddi_clock_get(struct intel_encoder *encoder,
|
2015-01-15 12:55:21 +00:00
|
|
|
struct intel_crtc_state *pipe_config)
|
2014-07-29 18:57:08 +00:00
|
|
|
{
|
2014-12-12 14:26:57 +00:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen <= 8)
|
|
|
|
hsw_ddi_clock_get(encoder, pipe_config);
|
2015-10-28 11:16:45 +00:00
|
|
|
else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
|
2014-12-12 14:26:57 +00:00
|
|
|
skl_ddi_clock_get(encoder, pipe_config);
|
2014-08-22 04:19:12 +00:00
|
|
|
else if (IS_BROXTON(dev))
|
|
|
|
bxt_ddi_clock_get(encoder, pipe_config);
|
2014-07-29 18:57:08 +00:00
|
|
|
}
|
|
|
|
|
2014-07-29 17:06:22 +00:00
|
|
|
static bool
|
2014-07-29 17:06:23 +00:00
|
|
|
hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
|
2015-01-15 12:55:23 +00:00
|
|
|
struct intel_crtc_state *crtc_state,
|
2015-07-06 12:10:02 +00:00
|
|
|
struct intel_encoder *intel_encoder)
|
2012-10-05 15:05:58 +00:00
|
|
|
{
|
2016-03-08 15:46:23 +00:00
|
|
|
struct intel_shared_dpll *pll;
|
2012-10-05 15:05:58 +00:00
|
|
|
|
2016-03-08 15:46:26 +00:00
|
|
|
pll = intel_get_shared_dpll(intel_crtc, crtc_state,
|
|
|
|
intel_encoder);
|
|
|
|
if (!pll)
|
|
|
|
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
|
|
|
|
pipe_name(intel_crtc->pipe));
|
|
|
|
|
|
|
|
return pll;
|
2012-10-05 15:05:58 +00:00
|
|
|
}
|
|
|
|
|
2014-11-13 14:55:20 +00:00
|
|
|
static bool
|
|
|
|
skl_ddi_pll_select(struct intel_crtc *intel_crtc,
|
2015-01-15 12:55:23 +00:00
|
|
|
struct intel_crtc_state *crtc_state,
|
2015-07-06 12:10:02 +00:00
|
|
|
struct intel_encoder *intel_encoder)
|
2014-11-13 14:55:20 +00:00
|
|
|
{
|
|
|
|
struct intel_shared_dpll *pll;
|
|
|
|
|
2016-03-08 15:46:23 +00:00
|
|
|
pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
|
2014-11-13 14:55:20 +00:00
|
|
|
if (pll == NULL) {
|
|
|
|
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
|
|
|
|
pipe_name(intel_crtc->pipe));
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2014-07-29 17:06:22 +00:00
|
|
|
|
2014-08-22 04:19:08 +00:00
|
|
|
static bool
|
|
|
|
bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
2015-07-06 12:10:02 +00:00
|
|
|
struct intel_encoder *intel_encoder)
|
2014-08-22 04:19:08 +00:00
|
|
|
{
|
2016-03-08 15:46:25 +00:00
|
|
|
return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
|
2014-08-22 04:19:08 +00:00
|
|
|
}
|
|
|
|
|
2014-07-29 17:06:22 +00:00
|
|
|
/*
|
|
|
|
* Tries to find a *shared* PLL for the CRTC and store it in
|
|
|
|
* intel_crtc->ddi_pll_sel.
|
|
|
|
*
|
|
|
|
* For private DPLLs, compute_config() should do the selection for us. This
|
|
|
|
* function should be folded into compute_config() eventually.
|
|
|
|
*/
|
2015-01-15 12:55:23 +00:00
|
|
|
bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
2014-07-29 17:06:22 +00:00
|
|
|
{
|
2014-11-13 14:55:20 +00:00
|
|
|
struct drm_device *dev = intel_crtc->base.dev;
|
2014-10-29 09:32:30 +00:00
|
|
|
struct intel_encoder *intel_encoder =
|
2015-03-20 14:18:12 +00:00
|
|
|
intel_ddi_get_crtc_new_encoder(crtc_state);
|
2014-07-29 17:06:22 +00:00
|
|
|
|
2015-10-28 11:16:45 +00:00
|
|
|
if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
|
2015-01-15 12:55:23 +00:00
|
|
|
return skl_ddi_pll_select(intel_crtc, crtc_state,
|
2015-07-06 12:10:02 +00:00
|
|
|
intel_encoder);
|
2014-08-22 04:19:08 +00:00
|
|
|
else if (IS_BROXTON(dev))
|
|
|
|
return bxt_ddi_pll_select(intel_crtc, crtc_state,
|
2015-07-06 12:10:02 +00:00
|
|
|
intel_encoder);
|
2014-11-13 14:55:20 +00:00
|
|
|
else
|
2015-01-15 12:55:23 +00:00
|
|
|
return hsw_ddi_pll_select(intel_crtc, crtc_state,
|
2015-07-06 12:10:02 +00:00
|
|
|
intel_encoder);
|
2014-07-29 17:06:22 +00:00
|
|
|
}
|
|
|
|
|
2012-10-15 18:51:30 +00:00
|
|
|
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
|
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
2012-10-15 18:51:30 +00:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
|
2015-01-15 12:55:25 +00:00
|
|
|
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
|
2012-10-15 18:51:30 +00:00
|
|
|
int type = intel_encoder->type;
|
|
|
|
uint32_t temp;
|
|
|
|
|
2016-06-22 18:57:06 +00:00
|
|
|
if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
|
2016-03-18 15:05:42 +00:00
|
|
|
WARN_ON(transcoder_is_dsi(cpu_transcoder));
|
|
|
|
|
2012-10-23 20:30:00 +00:00
|
|
|
temp = TRANS_MSA_SYNC_CLK;
|
2015-01-15 12:55:25 +00:00
|
|
|
switch (intel_crtc->config->pipe_bpp) {
|
2012-10-15 18:51:30 +00:00
|
|
|
case 18:
|
2012-10-23 20:30:00 +00:00
|
|
|
temp |= TRANS_MSA_6_BPC;
|
2012-10-15 18:51:30 +00:00
|
|
|
break;
|
|
|
|
case 24:
|
2012-10-23 20:30:00 +00:00
|
|
|
temp |= TRANS_MSA_8_BPC;
|
2012-10-15 18:51:30 +00:00
|
|
|
break;
|
|
|
|
case 30:
|
2012-10-23 20:30:00 +00:00
|
|
|
temp |= TRANS_MSA_10_BPC;
|
2012-10-15 18:51:30 +00:00
|
|
|
break;
|
|
|
|
case 36:
|
2012-10-23 20:30:00 +00:00
|
|
|
temp |= TRANS_MSA_12_BPC;
|
2012-10-15 18:51:30 +00:00
|
|
|
break;
|
|
|
|
default:
|
drm/i915: precompute pipe bpp before touching the hw
The procedure has now 3 steps:
1. Compute the bpp that the plane will output, this is done in
pipe_config_set_bpp and stored into pipe_config->pipe_bpp. Also,
this function clamps the pipe_bpp to whatever limit the EDID of any
connected output specifies.
2. Adjust the pipe_bpp in the encoder and crtc functions, according to
whatever constraints there are.
3. Decide whether to use dither by comparing the stored plane bpp with
computed pipe_bpp.
There are a few slight functional changes in this patch:
- LVDS connector are now also going through the EDID clamping. But in
a 2nd change we now unconditionally force the lvds bpc value - this
shouldn't matter in reality when the panel setup is consistent, but
better safe than sorry.
- HDMI now forces the pipe_bpp to the selected value - I think that's
what we actually want, since otherwise at least the pixelclock
computations are wrong (I'm not sure whether the port would accept
e.g. 10 bpc when in 12bpc mode). Contrary to the old code, we pick
the next higher bpc value, since otherwise there's no way to make
use of the 12 bpc mode (since the next patch will remove the 12bpc
plane format, it doesn't exist).
Both of these changes are due to the removal of the
pipe_bpp = min(display_bpp, plane_bpp);
statement.
Another slight change is the reworking of the dp bpc code:
- For the mode_valid callback it's sufficient to only check whether
the mode would fit at the lowest bpc.
- The bandwidth computation code is a bit restructured: It now walks
all available bpp values in an outer loop and the codeblock that
computes derived values (once a good configuration is found) has been
moved out of the for loop maze. This is prep work to allow us to
successively fall back on bpc values, and also correctly support bpc
values != 8 or 6.
v2: Rebased on top of Paulo Zanoni's little refactoring to use more
drm dp helper functions.
v3: Rebased on top of Jani's eDP bpp fix and Ville's limited color
range work.
v4: Remove the INTEL_MODE_DP_FORCE_6BPC #define, no longer needed.
v5: Remove intel_crtc->bpp, too, and fix up the 12bpc check in the
hdmi code. Also fixup the bpp check in intel_dp.c, it'll get reworked
in a later patch though again.
v6: Fix spelling in a comment.
v7: Debug output improvements for the bpp computation.
v8: Fixup 6bpc lvds check - dual-link and 8bpc mode are different
things!
v9: Reinstate the fix to properly ignore the firmware edp bpp ... this
was lost in a rebase.
v10: Both g4x and vlv lack 12bpc pipes, so don't enforce that we have
that. Still unsure whether this is the way to go, but at least 6bpc
for a 8bpc hdmi output seems to work.
v11: And g4x/vlv also lack 12bpc hdmi support, so only support high
depth on DP. Adjust the code.
v12: Rebased.
v13: Split out the introduction of pipe_config->dither|pipe_bpp, as
requested from Jesse Barnes.
v14: Split out the special 6BPC handling for DP, as requested by Jesse
Barnes.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-26 23:44:58 +00:00
|
|
|
BUG();
|
2012-10-15 18:51:30 +00:00
|
|
|
}
|
2012-10-23 20:30:00 +00:00
|
|
|
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
|
2012-10-15 18:51:30 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-05-02 04:02:48 +00:00
|
|
|
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
|
|
|
|
{
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2015-01-15 12:55:25 +00:00
|
|
|
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
|
2014-05-02 04:02:48 +00:00
|
|
|
uint32_t temp;
|
|
|
|
temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
|
|
|
|
if (state == true)
|
|
|
|
temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
|
|
|
|
else
|
|
|
|
temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
|
|
|
|
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
|
|
|
|
}
|
|
|
|
|
2013-03-07 15:30:27 +00:00
|
|
|
void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
|
2012-10-05 15:05:53 +00:00
|
|
|
{
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
|
2013-11-03 04:07:37 +00:00
|
|
|
struct drm_device *dev = crtc->dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2012-10-05 15:05:53 +00:00
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
2015-01-15 12:55:25 +00:00
|
|
|
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
|
2012-10-26 21:05:50 +00:00
|
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
2012-10-15 18:51:29 +00:00
|
|
|
int type = intel_encoder->type;
|
2012-10-05 15:05:53 +00:00
|
|
|
uint32_t temp;
|
|
|
|
|
2012-10-24 18:06:19 +00:00
|
|
|
/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
|
|
|
|
temp = TRANS_DDI_FUNC_ENABLE;
|
2012-10-26 21:05:50 +00:00
|
|
|
temp |= TRANS_DDI_SELECT_PORT(port);
|
2012-08-08 17:15:29 +00:00
|
|
|
|
2015-01-15 12:55:25 +00:00
|
|
|
switch (intel_crtc->config->pipe_bpp) {
|
2012-08-08 17:15:29 +00:00
|
|
|
case 18:
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_BPC_6;
|
2012-08-08 17:15:29 +00:00
|
|
|
break;
|
|
|
|
case 24:
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_BPC_8;
|
2012-08-08 17:15:29 +00:00
|
|
|
break;
|
|
|
|
case 30:
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_BPC_10;
|
2012-08-08 17:15:29 +00:00
|
|
|
break;
|
|
|
|
case 36:
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_BPC_12;
|
2012-08-08 17:15:29 +00:00
|
|
|
break;
|
|
|
|
default:
|
drm/i915: precompute pipe bpp before touching the hw
The procedure has now 3 steps:
1. Compute the bpp that the plane will output, this is done in
pipe_config_set_bpp and stored into pipe_config->pipe_bpp. Also,
this function clamps the pipe_bpp to whatever limit the EDID of any
connected output specifies.
2. Adjust the pipe_bpp in the encoder and crtc functions, according to
whatever constraints there are.
3. Decide whether to use dither by comparing the stored plane bpp with
computed pipe_bpp.
There are a few slight functional changes in this patch:
- LVDS connector are now also going through the EDID clamping. But in
a 2nd change we now unconditionally force the lvds bpc value - this
shouldn't matter in reality when the panel setup is consistent, but
better safe than sorry.
- HDMI now forces the pipe_bpp to the selected value - I think that's
what we actually want, since otherwise at least the pixelclock
computations are wrong (I'm not sure whether the port would accept
e.g. 10 bpc when in 12bpc mode). Contrary to the old code, we pick
the next higher bpc value, since otherwise there's no way to make
use of the 12 bpc mode (since the next patch will remove the 12bpc
plane format, it doesn't exist).
Both of these changes are due to the removal of the
pipe_bpp = min(display_bpp, plane_bpp);
statement.
Another slight change is the reworking of the dp bpc code:
- For the mode_valid callback it's sufficient to only check whether
the mode would fit at the lowest bpc.
- The bandwidth computation code is a bit restructured: It now walks
all available bpp values in an outer loop and the codeblock that
computes derived values (once a good configuration is found) has been
moved out of the for loop maze. This is prep work to allow us to
successively fall back on bpc values, and also correctly support bpc
values != 8 or 6.
v2: Rebased on top of Paulo Zanoni's little refactoring to use more
drm dp helper functions.
v3: Rebased on top of Jani's eDP bpp fix and Ville's limited color
range work.
v4: Remove the INTEL_MODE_DP_FORCE_6BPC #define, no longer needed.
v5: Remove intel_crtc->bpp, too, and fix up the 12bpc check in the
hdmi code. Also fixup the bpp check in intel_dp.c, it'll get reworked
in a later patch though again.
v6: Fix spelling in a comment.
v7: Debug output improvements for the bpp computation.
v8: Fixup 6bpc lvds check - dual-link and 8bpc mode are different
things!
v9: Reinstate the fix to properly ignore the firmware edp bpp ... this
was lost in a rebase.
v10: Both g4x and vlv lack 12bpc pipes, so don't enforce that we have
that. Still unsure whether this is the way to go, but at least 6bpc
for a 8bpc hdmi output seems to work.
v11: And g4x/vlv also lack 12bpc hdmi support, so only support high
depth on DP. Adjust the code.
v12: Rebased.
v13: Split out the introduction of pipe_config->dither|pipe_bpp, as
requested from Jesse Barnes.
v14: Split out the special 6BPC handling for DP, as requested by Jesse
Barnes.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-26 23:44:58 +00:00
|
|
|
BUG();
|
2012-08-08 17:15:29 +00:00
|
|
|
}
|
2012-05-09 18:37:31 +00:00
|
|
|
|
2015-01-15 12:55:25 +00:00
|
|
|
if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_PVSYNC;
|
2015-01-15 12:55:25 +00:00
|
|
|
if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_PHSYNC;
|
2012-08-08 17:15:28 +00:00
|
|
|
|
2012-10-23 20:30:04 +00:00
|
|
|
if (cpu_transcoder == TRANSCODER_EDP) {
|
|
|
|
switch (pipe) {
|
|
|
|
case PIPE_A:
|
2013-11-03 04:07:37 +00:00
|
|
|
/* On Haswell, can only use the always-on power well for
|
|
|
|
* eDP when not using the panel fitter, and when not
|
|
|
|
* using motion blur mitigation (which we don't
|
|
|
|
* support). */
|
2014-05-29 12:10:22 +00:00
|
|
|
if (IS_HASWELL(dev) &&
|
2015-01-15 12:55:25 +00:00
|
|
|
(intel_crtc->config->pch_pfit.enabled ||
|
|
|
|
intel_crtc->config->pch_pfit.force_thru))
|
2013-01-29 18:35:20 +00:00
|
|
|
temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
|
|
|
|
else
|
|
|
|
temp |= TRANS_DDI_EDP_INPUT_A_ON;
|
2012-10-23 20:30:04 +00:00
|
|
|
break;
|
|
|
|
case PIPE_B:
|
|
|
|
temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
|
|
|
|
break;
|
|
|
|
case PIPE_C:
|
|
|
|
temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-15 18:51:29 +00:00
|
|
|
if (type == INTEL_OUTPUT_HDMI) {
|
2015-01-15 12:55:25 +00:00
|
|
|
if (intel_crtc->config->has_hdmi_sink)
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_MODE_SELECT_HDMI;
|
2012-10-05 15:05:53 +00:00
|
|
|
else
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_MODE_SELECT_DVI;
|
2012-10-15 18:51:29 +00:00
|
|
|
} else if (type == INTEL_OUTPUT_ANALOG) {
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_MODE_SELECT_FDI;
|
2015-01-15 12:55:25 +00:00
|
|
|
temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
|
2016-06-22 18:57:06 +00:00
|
|
|
} else if (type == INTEL_OUTPUT_DP ||
|
2012-10-15 18:51:29 +00:00
|
|
|
type == INTEL_OUTPUT_EDP) {
|
2016-07-28 14:50:39 +00:00
|
|
|
temp |= TRANS_DDI_MODE_SELECT_DP_SST;
|
2015-07-06 13:39:15 +00:00
|
|
|
temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
|
2014-05-02 04:02:48 +00:00
|
|
|
} else if (type == INTEL_OUTPUT_DP_MST) {
|
2016-07-28 14:50:39 +00:00
|
|
|
temp |= TRANS_DDI_MODE_SELECT_DP_MST;
|
2015-07-06 13:39:15 +00:00
|
|
|
temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
|
2012-10-05 15:05:53 +00:00
|
|
|
} else {
|
2013-04-17 14:48:49 +00:00
|
|
|
WARN(1, "Invalid encoder type %d for pipe %c\n",
|
|
|
|
intel_encoder->type, pipe_name(pipe));
|
2012-10-05 15:05:53 +00:00
|
|
|
}
|
|
|
|
|
2012-10-24 18:06:19 +00:00
|
|
|
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
|
2012-10-05 15:05:53 +00:00
|
|
|
}
|
2012-05-09 18:37:31 +00:00
|
|
|
|
2012-10-24 18:06:19 +00:00
|
|
|
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
|
|
|
|
enum transcoder cpu_transcoder)
|
2012-10-05 15:05:53 +00:00
|
|
|
{
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
|
2012-10-05 15:05:53 +00:00
|
|
|
uint32_t val = I915_READ(reg);
|
|
|
|
|
2014-05-02 04:02:48 +00:00
|
|
|
val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
|
2012-10-24 18:06:19 +00:00
|
|
|
val |= TRANS_DDI_PORT_NONE;
|
2012-10-05 15:05:53 +00:00
|
|
|
I915_WRITE(reg, val);
|
2012-05-09 18:37:31 +00:00
|
|
|
}
|
|
|
|
|
2012-10-26 21:05:51 +00:00
|
|
|
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = intel_connector->base.dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2012-10-26 21:05:51 +00:00
|
|
|
struct intel_encoder *intel_encoder = intel_connector->encoder;
|
|
|
|
int type = intel_connector->base.connector_type;
|
|
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
|
|
|
enum pipe pipe = 0;
|
|
|
|
enum transcoder cpu_transcoder;
|
2014-04-01 17:55:12 +00:00
|
|
|
enum intel_display_power_domain power_domain;
|
2012-10-26 21:05:51 +00:00
|
|
|
uint32_t tmp;
|
2016-02-12 16:55:16 +00:00
|
|
|
bool ret;
|
2012-10-26 21:05:51 +00:00
|
|
|
|
2014-04-01 17:55:12 +00:00
|
|
|
power_domain = intel_display_port_power_domain(intel_encoder);
|
2016-02-12 16:55:16 +00:00
|
|
|
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
|
2014-04-01 17:55:12 +00:00
|
|
|
return false;
|
|
|
|
|
2016-02-12 16:55:16 +00:00
|
|
|
if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
|
|
|
|
ret = false;
|
|
|
|
goto out;
|
|
|
|
}
|
2012-10-26 21:05:51 +00:00
|
|
|
|
|
|
|
if (port == PORT_A)
|
|
|
|
cpu_transcoder = TRANSCODER_EDP;
|
|
|
|
else
|
2012-11-29 21:18:51 +00:00
|
|
|
cpu_transcoder = (enum transcoder) pipe;
|
2012-10-26 21:05:51 +00:00
|
|
|
|
|
|
|
tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
|
|
|
|
|
|
|
|
switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
|
|
|
|
case TRANS_DDI_MODE_SELECT_HDMI:
|
|
|
|
case TRANS_DDI_MODE_SELECT_DVI:
|
2016-02-12 16:55:16 +00:00
|
|
|
ret = type == DRM_MODE_CONNECTOR_HDMIA;
|
|
|
|
break;
|
2012-10-26 21:05:51 +00:00
|
|
|
|
|
|
|
case TRANS_DDI_MODE_SELECT_DP_SST:
|
2016-02-12 16:55:16 +00:00
|
|
|
ret = type == DRM_MODE_CONNECTOR_eDP ||
|
|
|
|
type == DRM_MODE_CONNECTOR_DisplayPort;
|
|
|
|
break;
|
|
|
|
|
2014-05-02 04:02:48 +00:00
|
|
|
case TRANS_DDI_MODE_SELECT_DP_MST:
|
|
|
|
/* if the transcoder is in MST state then
|
|
|
|
* connector isn't connected */
|
2016-02-12 16:55:16 +00:00
|
|
|
ret = false;
|
|
|
|
break;
|
2012-10-26 21:05:51 +00:00
|
|
|
|
|
|
|
case TRANS_DDI_MODE_SELECT_FDI:
|
2016-02-12 16:55:16 +00:00
|
|
|
ret = type == DRM_MODE_CONNECTOR_VGA;
|
|
|
|
break;
|
2012-10-26 21:05:51 +00:00
|
|
|
|
|
|
|
default:
|
2016-02-12 16:55:16 +00:00
|
|
|
ret = false;
|
|
|
|
break;
|
2012-10-26 21:05:51 +00:00
|
|
|
}
|
2016-02-12 16:55:16 +00:00
|
|
|
|
|
|
|
out:
|
|
|
|
intel_display_power_put(dev_priv, power_domain);
|
|
|
|
|
|
|
|
return ret;
|
2012-10-26 21:05:51 +00:00
|
|
|
}
|
|
|
|
|
2012-07-02 11:27:29 +00:00
|
|
|
bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
|
|
|
|
enum pipe *pipe)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2012-10-15 18:51:39 +00:00
|
|
|
enum port port = intel_ddi_get_encoder_port(encoder);
|
2014-03-05 14:20:54 +00:00
|
|
|
enum intel_display_power_domain power_domain;
|
2012-07-02 11:27:29 +00:00
|
|
|
u32 tmp;
|
|
|
|
int i;
|
2016-02-12 16:55:16 +00:00
|
|
|
bool ret;
|
2012-07-02 11:27:29 +00:00
|
|
|
|
2014-03-05 14:20:54 +00:00
|
|
|
power_domain = intel_display_port_power_domain(encoder);
|
2016-02-12 16:55:16 +00:00
|
|
|
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
|
2014-03-05 14:20:54 +00:00
|
|
|
return false;
|
|
|
|
|
2016-02-12 16:55:16 +00:00
|
|
|
ret = false;
|
|
|
|
|
2012-10-15 18:51:39 +00:00
|
|
|
tmp = I915_READ(DDI_BUF_CTL(port));
|
2012-07-02 11:27:29 +00:00
|
|
|
|
|
|
|
if (!(tmp & DDI_BUF_CTL_ENABLE))
|
2016-02-12 16:55:16 +00:00
|
|
|
goto out;
|
2012-07-02 11:27:29 +00:00
|
|
|
|
2012-10-24 18:06:19 +00:00
|
|
|
if (port == PORT_A) {
|
|
|
|
tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
|
2012-07-02 11:27:29 +00:00
|
|
|
|
2012-10-24 18:06:19 +00:00
|
|
|
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
|
|
|
|
case TRANS_DDI_EDP_INPUT_A_ON:
|
|
|
|
case TRANS_DDI_EDP_INPUT_A_ONOFF:
|
|
|
|
*pipe = PIPE_A;
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_EDP_INPUT_B_ONOFF:
|
|
|
|
*pipe = PIPE_B;
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_EDP_INPUT_C_ONOFF:
|
|
|
|
*pipe = PIPE_C;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-02-12 16:55:16 +00:00
|
|
|
ret = true;
|
2012-10-24 18:06:19 +00:00
|
|
|
|
2016-02-12 16:55:16 +00:00
|
|
|
goto out;
|
|
|
|
}
|
2014-05-02 04:02:48 +00:00
|
|
|
|
2016-02-12 16:55:16 +00:00
|
|
|
for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
|
|
|
|
tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
|
|
|
|
|
|
|
|
if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
|
|
|
|
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
|
|
|
|
TRANS_DDI_MODE_SELECT_DP_MST)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
*pipe = i;
|
|
|
|
ret = true;
|
|
|
|
|
|
|
|
goto out;
|
2012-07-02 11:27:29 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-04-17 14:48:49 +00:00
|
|
|
DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
|
2012-07-02 11:27:29 +00:00
|
|
|
|
2016-02-12 16:55:16 +00:00
|
|
|
out:
|
2016-06-13 13:44:37 +00:00
|
|
|
if (ret && IS_BROXTON(dev_priv)) {
|
|
|
|
tmp = I915_READ(BXT_PHY_CTL(port));
|
|
|
|
if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
|
|
|
|
BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
|
|
|
|
DRM_ERROR("Port %c enabled but PHY powered down? "
|
|
|
|
"(PHY_CTL %08x)\n", port_name(port), tmp);
|
|
|
|
}
|
|
|
|
|
2016-02-12 16:55:16 +00:00
|
|
|
intel_display_power_put(dev_priv, power_domain);
|
|
|
|
|
|
|
|
return ret;
|
2012-07-02 11:27:29 +00:00
|
|
|
}
|
|
|
|
|
2012-10-05 15:05:54 +00:00
|
|
|
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
|
|
|
|
{
|
|
|
|
struct drm_crtc *crtc = &intel_crtc->base;
|
2015-10-01 16:53:49 +00:00
|
|
|
struct drm_device *dev = crtc->dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2012-10-05 15:05:54 +00:00
|
|
|
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
|
|
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
2015-01-15 12:55:25 +00:00
|
|
|
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
|
2012-10-05 15:05:54 +00:00
|
|
|
|
2012-10-23 20:29:56 +00:00
|
|
|
if (cpu_transcoder != TRANSCODER_EDP)
|
|
|
|
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
|
|
|
|
TRANS_CLK_SEL_PORT(port));
|
2012-10-05 15:05:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
|
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
|
2015-01-15 12:55:25 +00:00
|
|
|
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
|
2012-10-05 15:05:54 +00:00
|
|
|
|
2012-10-23 20:29:56 +00:00
|
|
|
if (cpu_transcoder != TRANSCODER_EDP)
|
|
|
|
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
|
|
|
|
TRANS_CLK_SEL_DISABLED);
|
2012-10-05 15:05:54 +00:00
|
|
|
}
|
|
|
|
|
2016-07-12 12:59:28 +00:00
|
|
|
static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port, uint8_t iboost)
|
2015-06-25 08:11:03 +00:00
|
|
|
{
|
2016-07-12 12:59:28 +00:00
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
|
|
|
|
tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
|
|
|
|
if (iboost)
|
|
|
|
tmp |= iboost << BALANCE_LEG_SHIFT(port);
|
|
|
|
else
|
|
|
|
tmp |= BALANCE_LEG_DISABLE(port);
|
|
|
|
I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
|
|
|
|
enum port port = intel_dig_port->port;
|
|
|
|
int type = encoder->type;
|
2015-06-25 08:11:03 +00:00
|
|
|
const struct ddi_buf_trans *ddi_translations;
|
|
|
|
uint8_t iboost;
|
2015-07-10 11:10:55 +00:00
|
|
|
uint8_t dp_iboost, hdmi_iboost;
|
2015-06-25 08:11:03 +00:00
|
|
|
int n_entries;
|
|
|
|
|
2015-07-10 11:10:55 +00:00
|
|
|
/* VBT may override standard boost values */
|
|
|
|
dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
|
|
|
|
hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
|
|
|
|
|
2016-06-22 18:57:06 +00:00
|
|
|
if (type == INTEL_OUTPUT_DP) {
|
2015-07-10 11:10:55 +00:00
|
|
|
if (dp_iboost) {
|
|
|
|
iboost = dp_iboost;
|
|
|
|
} else {
|
2015-12-08 17:59:41 +00:00
|
|
|
ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
|
2015-11-11 13:15:54 +00:00
|
|
|
iboost = ddi_translations[level].i_boost;
|
2015-07-10 11:10:55 +00:00
|
|
|
}
|
2015-06-25 08:11:03 +00:00
|
|
|
} else if (type == INTEL_OUTPUT_EDP) {
|
2015-07-10 11:10:55 +00:00
|
|
|
if (dp_iboost) {
|
|
|
|
iboost = dp_iboost;
|
|
|
|
} else {
|
2015-12-08 17:59:41 +00:00
|
|
|
ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
|
2015-12-08 17:59:43 +00:00
|
|
|
|
|
|
|
if (WARN_ON(port != PORT_A &&
|
|
|
|
port != PORT_E && n_entries > 9))
|
|
|
|
n_entries = 9;
|
|
|
|
|
2015-11-11 13:15:54 +00:00
|
|
|
iboost = ddi_translations[level].i_boost;
|
2015-07-10 11:10:55 +00:00
|
|
|
}
|
2015-06-25 08:11:03 +00:00
|
|
|
} else if (type == INTEL_OUTPUT_HDMI) {
|
2015-07-10 11:10:55 +00:00
|
|
|
if (hdmi_iboost) {
|
|
|
|
iboost = hdmi_iboost;
|
|
|
|
} else {
|
2015-12-08 17:59:41 +00:00
|
|
|
ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
|
2015-11-11 13:15:54 +00:00
|
|
|
iboost = ddi_translations[level].i_boost;
|
2015-07-10 11:10:55 +00:00
|
|
|
}
|
2015-06-25 08:11:03 +00:00
|
|
|
} else {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Make sure that the requested I_boost is valid */
|
|
|
|
if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
|
|
|
|
DRM_ERROR("Invalid I_boost value %u\n", iboost);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-07-12 12:59:28 +00:00
|
|
|
_skl_ddi_set_iboost(dev_priv, port, iboost);
|
2015-06-25 08:11:03 +00:00
|
|
|
|
2016-07-12 12:59:28 +00:00
|
|
|
if (port == PORT_A && intel_dig_port->max_lanes == 4)
|
|
|
|
_skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
|
2015-06-25 08:11:03 +00:00
|
|
|
}
|
|
|
|
|
2015-12-08 17:59:41 +00:00
|
|
|
static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
|
|
|
|
u32 level, enum port port, int type)
|
2014-11-18 10:15:27 +00:00
|
|
|
{
|
|
|
|
const struct bxt_ddi_buf_trans *ddi_translations;
|
|
|
|
u32 n_entries, i;
|
|
|
|
uint32_t val;
|
|
|
|
|
2016-03-24 15:50:21 +00:00
|
|
|
if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
|
2015-09-24 04:54:56 +00:00
|
|
|
n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
|
|
|
|
ddi_translations = bxt_ddi_translations_edp;
|
2016-06-22 18:57:06 +00:00
|
|
|
} else if (type == INTEL_OUTPUT_DP
|
2015-09-24 04:54:56 +00:00
|
|
|
|| type == INTEL_OUTPUT_EDP) {
|
2014-11-18 10:15:27 +00:00
|
|
|
n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
|
|
|
|
ddi_translations = bxt_ddi_translations_dp;
|
|
|
|
} else if (type == INTEL_OUTPUT_HDMI) {
|
|
|
|
n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
|
|
|
|
ddi_translations = bxt_ddi_translations_hdmi;
|
|
|
|
} else {
|
|
|
|
DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
|
|
|
|
type);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check if default value has to be used */
|
|
|
|
if (level >= n_entries ||
|
|
|
|
(type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
|
|
|
|
for (i = 0; i < n_entries; i++) {
|
|
|
|
if (ddi_translations[i].default_index) {
|
|
|
|
level = i;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* While we write to the group register to program all lanes at once we
|
|
|
|
* can read only lane registers and we pick lanes 0/1 for that.
|
|
|
|
*/
|
|
|
|
val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
|
|
|
|
val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
|
|
|
|
I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
|
|
|
|
val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
|
|
|
|
val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
|
|
|
|
ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
|
|
|
|
I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
|
2015-09-24 04:52:54 +00:00
|
|
|
val &= ~SCALE_DCOMP_METHOD;
|
2014-11-18 10:15:27 +00:00
|
|
|
if (ddi_translations[level].enable)
|
2015-09-24 04:52:54 +00:00
|
|
|
val |= SCALE_DCOMP_METHOD;
|
|
|
|
|
|
|
|
if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
|
|
|
|
DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
|
|
|
|
|
2014-11-18 10:15:27 +00:00
|
|
|
I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
|
|
|
|
val &= ~DE_EMPHASIS;
|
|
|
|
val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
|
|
|
|
I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
|
|
|
|
val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
|
|
|
|
I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
|
|
|
|
}
|
|
|
|
|
2015-06-25 08:11:03 +00:00
|
|
|
static uint32_t translate_signal_level(int signal_levels)
|
|
|
|
{
|
|
|
|
uint32_t level;
|
|
|
|
|
|
|
|
switch (signal_levels) {
|
|
|
|
default:
|
|
|
|
DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
|
|
|
|
signal_levels);
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
|
|
|
|
level = 0;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
|
|
|
|
level = 1;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
|
|
|
|
level = 2;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
|
|
|
|
level = 3;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
|
|
|
|
level = 4;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
|
|
|
|
level = 5;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
|
|
|
|
level = 6;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
|
|
|
|
level = 7;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
|
|
|
|
level = 8;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
|
|
|
|
level = 9;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return level;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
|
2015-12-08 17:59:41 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
|
2015-06-25 08:11:03 +00:00
|
|
|
struct intel_encoder *encoder = &dport->base;
|
|
|
|
uint8_t train_set = intel_dp->train_set[0];
|
|
|
|
int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
|
|
|
|
DP_TRAIN_PRE_EMPHASIS_MASK);
|
|
|
|
enum port port = dport->port;
|
|
|
|
uint32_t level;
|
|
|
|
|
|
|
|
level = translate_signal_level(signal_levels);
|
|
|
|
|
2015-12-08 17:59:41 +00:00
|
|
|
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
|
2016-07-12 12:59:28 +00:00
|
|
|
skl_ddi_set_iboost(encoder, level);
|
2015-12-08 17:59:41 +00:00
|
|
|
else if (IS_BROXTON(dev_priv))
|
|
|
|
bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
|
2015-06-25 08:11:03 +00:00
|
|
|
|
|
|
|
return DDI_BUF_TRANS_SELECT(level);
|
|
|
|
}
|
|
|
|
|
2015-08-17 15:46:20 +00:00
|
|
|
void intel_ddi_clk_select(struct intel_encoder *encoder,
|
2016-09-01 22:08:07 +00:00
|
|
|
struct intel_shared_dpll *pll)
|
2012-10-05 15:05:58 +00:00
|
|
|
{
|
2015-08-17 15:46:20 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
enum port port = intel_ddi_get_encoder_port(encoder);
|
2012-10-05 15:05:58 +00:00
|
|
|
|
2016-09-01 22:08:07 +00:00
|
|
|
if (WARN_ON(!pll))
|
|
|
|
return;
|
|
|
|
|
2015-08-17 15:46:20 +00:00
|
|
|
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
|
2014-11-13 14:55:19 +00:00
|
|
|
uint32_t val;
|
|
|
|
|
2014-11-14 17:24:33 +00:00
|
|
|
/* DDI -> PLL mapping */
|
2014-11-13 14:55:19 +00:00
|
|
|
val = I915_READ(DPLL_CTRL2);
|
|
|
|
|
|
|
|
val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
|
|
|
|
DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
|
2016-09-01 22:08:07 +00:00
|
|
|
val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
|
2014-11-13 14:55:19 +00:00
|
|
|
DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
|
|
|
|
|
|
|
|
I915_WRITE(DPLL_CTRL2, val);
|
2014-11-14 17:24:33 +00:00
|
|
|
|
2015-08-17 15:46:20 +00:00
|
|
|
} else if (INTEL_INFO(dev_priv)->gen < 9) {
|
2016-09-01 22:08:07 +00:00
|
|
|
I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
|
2014-11-13 14:55:19 +00:00
|
|
|
}
|
2015-08-17 15:46:20 +00:00
|
|
|
}
|
|
|
|
|
2016-09-01 22:08:08 +00:00
|
|
|
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
|
|
|
|
int link_rate, uint32_t lane_count,
|
|
|
|
struct intel_shared_dpll *pll,
|
|
|
|
bool link_mst)
|
2015-08-17 15:46:20 +00:00
|
|
|
{
|
2016-09-01 22:08:08 +00:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
enum port port = intel_ddi_get_encoder_port(encoder);
|
2016-05-02 19:08:24 +00:00
|
|
|
|
2016-09-01 22:08:08 +00:00
|
|
|
intel_dp_set_link_params(intel_dp, link_rate, lane_count,
|
|
|
|
link_mst);
|
|
|
|
if (encoder->type == INTEL_OUTPUT_EDP)
|
2015-08-17 15:46:20 +00:00
|
|
|
intel_edp_panel_on(intel_dp);
|
2016-07-12 12:59:33 +00:00
|
|
|
|
2016-09-01 22:08:08 +00:00
|
|
|
intel_ddi_clk_select(encoder, pll);
|
|
|
|
intel_prepare_dp_ddi_buffers(encoder);
|
|
|
|
intel_ddi_init_dp_buf_reg(encoder);
|
|
|
|
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
|
|
|
|
intel_dp_start_link_train(intel_dp);
|
|
|
|
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
|
|
|
|
intel_dp_stop_link_train(intel_dp);
|
|
|
|
}
|
2015-08-17 15:05:12 +00:00
|
|
|
|
2016-09-01 22:08:08 +00:00
|
|
|
static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
|
|
|
|
bool has_hdmi_sink,
|
|
|
|
struct drm_display_mode *adjusted_mode,
|
|
|
|
struct intel_shared_dpll *pll)
|
|
|
|
{
|
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
struct drm_encoder *drm_encoder = &encoder->base;
|
|
|
|
enum port port = intel_ddi_get_encoder_port(encoder);
|
|
|
|
int level = intel_ddi_hdmi_level(dev_priv, port);
|
2012-10-15 18:51:41 +00:00
|
|
|
|
2016-09-01 22:08:08 +00:00
|
|
|
intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
|
|
|
|
intel_ddi_clk_select(encoder, pll);
|
|
|
|
intel_prepare_hdmi_ddi_buffers(encoder);
|
|
|
|
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
|
|
|
|
skl_ddi_set_iboost(encoder, level);
|
|
|
|
else if (IS_BROXTON(dev_priv))
|
|
|
|
bxt_ddi_vswing_sequence(dev_priv, level, port,
|
|
|
|
INTEL_OUTPUT_HDMI);
|
2016-07-12 12:59:30 +00:00
|
|
|
|
2016-09-01 22:08:08 +00:00
|
|
|
intel_hdmi->set_infoframes(drm_encoder,
|
|
|
|
has_hdmi_sink,
|
|
|
|
adjusted_mode);
|
|
|
|
}
|
2016-07-12 12:59:33 +00:00
|
|
|
|
2016-09-01 22:08:08 +00:00
|
|
|
static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder,
|
|
|
|
struct intel_crtc_state *pipe_config,
|
|
|
|
struct drm_connector_state *conn_state)
|
|
|
|
{
|
|
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
|
|
|
struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
|
|
|
|
int type = intel_encoder->type;
|
2014-04-24 21:54:58 +00:00
|
|
|
|
2016-09-01 22:08:08 +00:00
|
|
|
if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
|
|
|
|
intel_ddi_pre_enable_dp(intel_encoder,
|
|
|
|
crtc->config->port_clock,
|
|
|
|
crtc->config->lane_count,
|
|
|
|
crtc->config->shared_dpll,
|
|
|
|
intel_crtc_has_type(crtc->config,
|
|
|
|
INTEL_OUTPUT_DP_MST));
|
|
|
|
}
|
|
|
|
if (type == INTEL_OUTPUT_HDMI) {
|
|
|
|
intel_ddi_pre_enable_hdmi(intel_encoder,
|
|
|
|
crtc->config->has_hdmi_sink,
|
|
|
|
&crtc->config->base.adjusted_mode,
|
|
|
|
crtc->config->shared_dpll);
|
2012-10-15 18:51:41 +00:00
|
|
|
}
|
2012-10-05 15:05:58 +00:00
|
|
|
}
|
|
|
|
|
2016-08-09 15:04:04 +00:00
|
|
|
static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
|
|
|
|
struct intel_crtc_state *old_crtc_state,
|
|
|
|
struct drm_connector_state *old_conn_state)
|
2012-10-05 15:05:58 +00:00
|
|
|
{
|
|
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
2014-11-13 14:55:19 +00:00
|
|
|
struct drm_device *dev = encoder->dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2012-10-05 15:05:58 +00:00
|
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
2012-10-23 20:30:07 +00:00
|
|
|
int type = intel_encoder->type;
|
2012-10-05 15:06:00 +00:00
|
|
|
uint32_t val;
|
2012-10-15 18:51:32 +00:00
|
|
|
bool wait = false;
|
2012-10-05 15:06:00 +00:00
|
|
|
|
2016-08-09 15:04:04 +00:00
|
|
|
/* old_crtc_state and old_conn_state are NULL when called from DP_MST */
|
|
|
|
|
2012-10-05 15:06:00 +00:00
|
|
|
val = I915_READ(DDI_BUF_CTL(port));
|
|
|
|
if (val & DDI_BUF_CTL_ENABLE) {
|
|
|
|
val &= ~DDI_BUF_CTL_ENABLE;
|
|
|
|
I915_WRITE(DDI_BUF_CTL(port), val);
|
2012-10-15 18:51:32 +00:00
|
|
|
wait = true;
|
2012-10-05 15:06:00 +00:00
|
|
|
}
|
2012-10-05 15:05:58 +00:00
|
|
|
|
2012-10-15 18:51:32 +00:00
|
|
|
val = I915_READ(DP_TP_CTL(port));
|
|
|
|
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
|
|
|
|
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
|
|
|
|
I915_WRITE(DP_TP_CTL(port), val);
|
|
|
|
|
|
|
|
if (wait)
|
|
|
|
intel_wait_ddi_buf_idle(dev_priv, port);
|
|
|
|
|
2016-06-22 18:57:06 +00:00
|
|
|
if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
|
2012-10-23 20:30:07 +00:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
2013-11-15 13:29:57 +00:00
|
|
|
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
|
2014-03-17 14:43:36 +00:00
|
|
|
intel_edp_panel_vdd_on(intel_dp);
|
2014-01-17 13:39:48 +00:00
|
|
|
intel_edp_panel_off(intel_dp);
|
2012-10-23 20:30:07 +00:00
|
|
|
}
|
|
|
|
|
2015-10-28 11:16:45 +00:00
|
|
|
if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
|
2014-11-13 14:55:19 +00:00
|
|
|
I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
|
|
|
|
DPLL_CTRL2_DDI_CLK_OFF(port)));
|
2014-08-22 04:19:06 +00:00
|
|
|
else if (INTEL_INFO(dev)->gen < 9)
|
2014-11-13 14:55:19 +00:00
|
|
|
I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
|
2016-05-02 19:08:24 +00:00
|
|
|
|
|
|
|
if (type == INTEL_OUTPUT_HDMI) {
|
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
|
|
|
|
|
|
|
intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
|
|
|
|
}
|
2012-10-05 15:05:58 +00:00
|
|
|
}
|
|
|
|
|
2016-08-23 14:18:08 +00:00
|
|
|
void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
|
|
|
|
struct intel_crtc_state *old_crtc_state,
|
|
|
|
struct drm_connector_state *old_conn_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
|
|
|
|
* and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
|
|
|
|
* step 13 is the correct place for it. Step 18 is where it was
|
|
|
|
* originally before the BUN.
|
|
|
|
*/
|
|
|
|
val = I915_READ(FDI_RX_CTL(PIPE_A));
|
|
|
|
val &= ~FDI_RX_ENABLE;
|
|
|
|
I915_WRITE(FDI_RX_CTL(PIPE_A), val);
|
|
|
|
|
|
|
|
intel_ddi_post_disable(intel_encoder, old_crtc_state, old_conn_state);
|
|
|
|
|
|
|
|
val = I915_READ(FDI_RX_MISC(PIPE_A));
|
|
|
|
val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
|
|
|
|
val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
|
|
|
|
I915_WRITE(FDI_RX_MISC(PIPE_A), val);
|
|
|
|
|
|
|
|
val = I915_READ(FDI_RX_CTL(PIPE_A));
|
|
|
|
val &= ~FDI_PCDCLK;
|
|
|
|
I915_WRITE(FDI_RX_CTL(PIPE_A), val);
|
|
|
|
|
|
|
|
val = I915_READ(FDI_RX_CTL(PIPE_A));
|
|
|
|
val &= ~FDI_RX_PLL_ENABLE;
|
|
|
|
I915_WRITE(FDI_RX_CTL(PIPE_A), val);
|
|
|
|
}
|
|
|
|
|
2016-08-09 15:04:04 +00:00
|
|
|
static void intel_enable_ddi(struct intel_encoder *intel_encoder,
|
|
|
|
struct intel_crtc_state *pipe_config,
|
|
|
|
struct drm_connector_state *conn_state)
|
2012-05-09 18:37:31 +00:00
|
|
|
{
|
2012-10-15 18:51:40 +00:00
|
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
2013-01-22 15:25:25 +00:00
|
|
|
struct drm_crtc *crtc = encoder->crtc;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
2012-10-15 18:51:40 +00:00
|
|
|
struct drm_device *dev = encoder->dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2012-10-15 18:51:40 +00:00
|
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
|
|
|
int type = intel_encoder->type;
|
2012-05-09 18:37:31 +00:00
|
|
|
|
2012-10-15 18:51:40 +00:00
|
|
|
if (type == INTEL_OUTPUT_HDMI) {
|
2012-12-11 18:48:30 +00:00
|
|
|
struct intel_digital_port *intel_dig_port =
|
|
|
|
enc_to_dig_port(encoder);
|
|
|
|
|
2012-10-15 18:51:40 +00:00
|
|
|
/* In HDMI/DVI mode, the port width, and swing/emphasis values
|
|
|
|
* are ignored so nothing special needs to be done besides
|
|
|
|
* enabling the port.
|
|
|
|
*/
|
2012-12-11 18:48:30 +00:00
|
|
|
I915_WRITE(DDI_BUF_CTL(port),
|
2013-07-12 20:54:41 +00:00
|
|
|
intel_dig_port->saved_port_bits |
|
|
|
|
DDI_BUF_CTL_ENABLE);
|
2012-10-23 20:30:06 +00:00
|
|
|
} else if (type == INTEL_OUTPUT_EDP) {
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
|
2014-11-13 14:55:22 +00:00
|
|
|
if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
|
2013-05-03 09:57:41 +00:00
|
|
|
intel_dp_stop_link_train(intel_dp);
|
|
|
|
|
2014-01-17 13:39:48 +00:00
|
|
|
intel_edp_backlight_on(intel_dp);
|
2014-11-14 16:52:28 +00:00
|
|
|
intel_psr_enable(intel_dp);
|
2016-08-09 15:04:13 +00:00
|
|
|
intel_edp_drrs_enable(intel_dp, pipe_config);
|
2012-10-15 18:51:40 +00:00
|
|
|
}
|
2013-01-22 15:25:25 +00:00
|
|
|
|
2015-01-15 12:55:25 +00:00
|
|
|
if (intel_crtc->config->has_audio) {
|
2014-05-21 20:29:31 +00:00
|
|
|
intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
|
2014-10-27 14:26:50 +00:00
|
|
|
intel_audio_codec_enable(intel_encoder);
|
2013-01-22 15:25:25 +00:00
|
|
|
}
|
2012-06-30 06:59:56 +00:00
|
|
|
}
|
|
|
|
|
2016-08-09 15:04:04 +00:00
|
|
|
static void intel_disable_ddi(struct intel_encoder *intel_encoder,
|
|
|
|
struct intel_crtc_state *old_crtc_state,
|
|
|
|
struct drm_connector_state *old_conn_state)
|
2012-06-30 06:59:56 +00:00
|
|
|
{
|
2012-10-23 20:30:06 +00:00
|
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
2013-01-22 15:25:25 +00:00
|
|
|
struct drm_crtc *crtc = encoder->crtc;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
2012-10-23 20:30:06 +00:00
|
|
|
int type = intel_encoder->type;
|
2013-01-22 15:25:25 +00:00
|
|
|
struct drm_device *dev = encoder->dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2012-10-23 20:30:06 +00:00
|
|
|
|
2015-01-15 12:55:25 +00:00
|
|
|
if (intel_crtc->config->has_audio) {
|
2014-10-27 14:26:50 +00:00
|
|
|
intel_audio_codec_disable(intel_encoder);
|
2014-05-21 20:29:31 +00:00
|
|
|
intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
|
|
|
|
}
|
2013-03-06 23:03:09 +00:00
|
|
|
|
2012-10-23 20:30:06 +00:00
|
|
|
if (type == INTEL_OUTPUT_EDP) {
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
|
2016-08-09 15:04:13 +00:00
|
|
|
intel_edp_drrs_disable(intel_dp, old_crtc_state);
|
2014-11-14 16:52:28 +00:00
|
|
|
intel_psr_disable(intel_dp);
|
2014-01-17 13:39:48 +00:00
|
|
|
intel_edp_backlight_off(intel_dp);
|
2012-10-23 20:30:06 +00:00
|
|
|
}
|
2012-05-09 18:37:31 +00:00
|
|
|
}
|
2012-10-05 15:05:52 +00:00
|
|
|
|
2016-06-13 13:44:34 +00:00
|
|
|
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
|
|
|
|
enum dpio_phy phy)
|
2016-04-01 13:02:44 +00:00
|
|
|
{
|
2016-06-13 13:44:37 +00:00
|
|
|
enum port port;
|
|
|
|
|
2016-04-01 13:02:44 +00:00
|
|
|
if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
|
|
|
|
(PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
|
|
|
|
DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
|
|
|
|
phy);
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (phy == DPIO_PHY1 &&
|
|
|
|
!(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
|
|
|
|
DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
|
|
|
|
DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
|
|
|
|
phy);
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-06-13 13:44:37 +00:00
|
|
|
for_each_port_masked(port,
|
|
|
|
phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
|
|
|
|
BIT(PORT_A)) {
|
|
|
|
u32 tmp = I915_READ(BXT_PHY_CTL(port));
|
|
|
|
|
|
|
|
if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
|
|
|
|
DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
|
|
|
|
"for port %c powered down "
|
|
|
|
"(PHY_CTL %08x)\n",
|
|
|
|
phy, port_name(port), tmp);
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-04-01 13:02:44 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-06-13 13:44:36 +00:00
|
|
|
static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
|
2016-04-04 14:27:10 +00:00
|
|
|
{
|
|
|
|
u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
|
|
|
|
|
|
|
|
return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
|
|
|
|
}
|
|
|
|
|
2016-06-13 13:44:36 +00:00
|
|
|
static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
|
|
|
|
enum dpio_phy phy)
|
2016-04-21 16:19:21 +00:00
|
|
|
{
|
2016-06-30 14:32:52 +00:00
|
|
|
if (intel_wait_for_register(dev_priv,
|
|
|
|
BXT_PORT_REF_DW3(phy),
|
|
|
|
GRC_DONE, GRC_DONE,
|
|
|
|
10))
|
2016-04-21 16:19:21 +00:00
|
|
|
DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
|
|
|
|
}
|
|
|
|
|
2016-06-13 13:44:34 +00:00
|
|
|
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
|
drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
"DDI PHY programming register defn", "Do ddi_phy_init always",
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-24 08:07:39 +00:00
|
|
|
{
|
2016-06-13 13:44:35 +00:00
|
|
|
u32 val;
|
drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
"DDI PHY programming register defn", "Do ddi_phy_init always",
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-24 08:07:39 +00:00
|
|
|
|
2016-06-13 13:44:34 +00:00
|
|
|
if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
|
2016-04-04 14:27:10 +00:00
|
|
|
/* Still read out the GRC value for state verification */
|
2016-04-20 17:46:04 +00:00
|
|
|
if (phy == DPIO_PHY0)
|
2016-06-13 13:44:36 +00:00
|
|
|
dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
|
2016-04-01 13:02:44 +00:00
|
|
|
|
2016-06-13 13:44:34 +00:00
|
|
|
if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
|
2016-04-20 17:46:06 +00:00
|
|
|
DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
|
|
|
|
"won't reprogram it\n", phy);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
2016-04-01 13:02:44 +00:00
|
|
|
|
2016-04-20 17:46:06 +00:00
|
|
|
DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
|
|
|
|
"force reprogramming it\n", phy);
|
|
|
|
}
|
2016-04-01 13:02:44 +00:00
|
|
|
|
drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
"DDI PHY programming register defn", "Do ddi_phy_init always",
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-24 08:07:39 +00:00
|
|
|
val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
|
|
|
|
val |= GT_DISPLAY_POWER_ON(phy);
|
|
|
|
I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
|
|
|
|
|
2016-03-31 17:45:54 +00:00
|
|
|
/*
|
|
|
|
* The PHY registers start out inaccessible and respond to reads with
|
|
|
|
* all 1s. Eventually they become accessible as they power up, then
|
|
|
|
* the reserved bit will give the default 0. Poll on the reserved bit
|
|
|
|
* becoming 0 to find when the PHY is accessible.
|
|
|
|
* HW team confirmed that the time to reach phypowergood status is
|
|
|
|
* anywhere between 50 us and 100us.
|
|
|
|
*/
|
|
|
|
if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
|
|
|
|
(PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
|
drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
"DDI PHY programming register defn", "Do ddi_phy_init always",
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-24 08:07:39 +00:00
|
|
|
DRM_ERROR("timeout during PHY%d power on\n", phy);
|
2016-03-31 17:45:54 +00:00
|
|
|
}
|
drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
"DDI PHY programming register defn", "Do ddi_phy_init always",
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-24 08:07:39 +00:00
|
|
|
|
|
|
|
/* Program PLL Rcomp code offset */
|
|
|
|
val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
|
|
|
|
val &= ~IREF0RC_OFFSET_MASK;
|
|
|
|
val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
|
|
|
|
I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
|
|
|
|
val &= ~IREF1RC_OFFSET_MASK;
|
|
|
|
val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
|
|
|
|
I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
|
|
|
|
|
|
|
|
/* Program power gating */
|
|
|
|
val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
|
|
|
|
val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
|
|
|
|
SUS_CLK_CONFIG;
|
|
|
|
I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
|
|
|
|
|
|
|
|
if (phy == DPIO_PHY0) {
|
|
|
|
val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
|
|
|
|
val |= DW6_OLDO_DYN_PWR_DOWN_EN;
|
|
|
|
I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
|
|
|
|
val &= ~OCL2_LDOFUSE_PWR_DIS;
|
|
|
|
/*
|
|
|
|
* On PHY1 disable power on the second channel, since no port is
|
|
|
|
* connected there. On PHY0 both channels have a port, so leave it
|
|
|
|
* enabled.
|
|
|
|
* TODO: port C is only connected on BXT-P, so on BXT0/1 we should
|
|
|
|
* power down the second channel on PHY0 as well.
|
2016-04-01 13:02:34 +00:00
|
|
|
*
|
|
|
|
* FIXME: Clarify programming of the following, the register is
|
|
|
|
* read-only with bit 6 fixed at 0 at least in stepping A.
|
drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
"DDI PHY programming register defn", "Do ddi_phy_init always",
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-24 08:07:39 +00:00
|
|
|
*/
|
|
|
|
if (phy == DPIO_PHY1)
|
|
|
|
val |= OCL2_LDOFUSE_PWR_DIS;
|
|
|
|
I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
|
|
|
|
|
|
|
|
if (phy == DPIO_PHY0) {
|
|
|
|
uint32_t grc_code;
|
|
|
|
/*
|
|
|
|
* PHY0 isn't connected to an RCOMP resistor so copy over
|
|
|
|
* the corresponding calibrated value from PHY1, and disable
|
|
|
|
* the automatic calibration on PHY0.
|
|
|
|
*/
|
2016-06-13 13:44:36 +00:00
|
|
|
val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
|
drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
"DDI PHY programming register defn", "Do ddi_phy_init always",
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-24 08:07:39 +00:00
|
|
|
grc_code = val << GRC_CODE_FAST_SHIFT |
|
|
|
|
val << GRC_CODE_SLOW_SHIFT |
|
|
|
|
val;
|
|
|
|
I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
|
|
|
|
val |= GRC_DIS | GRC_RDY_OVRD;
|
|
|
|
I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
|
|
|
|
}
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
|
|
|
|
val |= COMMON_RESET_DIS;
|
|
|
|
I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
|
2016-06-13 13:44:32 +00:00
|
|
|
|
|
|
|
if (phy == DPIO_PHY1)
|
2016-06-13 13:44:36 +00:00
|
|
|
bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
|
drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
"DDI PHY programming register defn", "Do ddi_phy_init always",
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-24 08:07:39 +00:00
|
|
|
}
|
|
|
|
|
2016-06-13 13:44:34 +00:00
|
|
|
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
|
drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
"DDI PHY programming register defn", "Do ddi_phy_init always",
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-24 08:07:39 +00:00
|
|
|
{
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
|
|
|
|
val &= ~COMMON_RESET_DIS;
|
|
|
|
I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
|
2016-04-01 13:02:41 +00:00
|
|
|
|
|
|
|
val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
|
|
|
|
val &= ~GT_DISPLAY_POWER_ON(phy);
|
|
|
|
I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
|
drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
"DDI PHY programming register defn", "Do ddi_phy_init always",
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-24 08:07:39 +00:00
|
|
|
}
|
|
|
|
|
2016-04-04 14:27:10 +00:00
|
|
|
static bool __printf(6, 7)
|
|
|
|
__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
|
|
|
|
i915_reg_t reg, u32 mask, u32 expected,
|
|
|
|
const char *reg_fmt, ...)
|
|
|
|
{
|
|
|
|
struct va_format vaf;
|
|
|
|
va_list args;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = I915_READ(reg);
|
|
|
|
if ((val & mask) == expected)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
va_start(args, reg_fmt);
|
|
|
|
vaf.fmt = reg_fmt;
|
|
|
|
vaf.va = &args;
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
|
|
|
|
"current %08x, expected %08x (mask %08x)\n",
|
|
|
|
phy, &vaf, reg.reg, val, (val & ~mask) | expected,
|
|
|
|
mask);
|
|
|
|
|
|
|
|
va_end(args);
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-06-13 13:44:34 +00:00
|
|
|
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
|
|
|
|
enum dpio_phy phy)
|
2016-04-04 14:27:10 +00:00
|
|
|
{
|
|
|
|
uint32_t mask;
|
|
|
|
bool ok;
|
|
|
|
|
|
|
|
#define _CHK(reg, mask, exp, fmt, ...) \
|
|
|
|
__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
|
|
|
|
## __VA_ARGS__)
|
|
|
|
|
2016-06-13 13:44:34 +00:00
|
|
|
if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
|
2016-04-04 14:27:10 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
ok = true;
|
|
|
|
|
|
|
|
/* PLL Rcomp code offset */
|
|
|
|
ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
|
|
|
|
IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
|
|
|
|
"BXT_PORT_CL1CM_DW9(%d)", phy);
|
|
|
|
ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
|
|
|
|
IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
|
|
|
|
"BXT_PORT_CL1CM_DW10(%d)", phy);
|
|
|
|
|
|
|
|
/* Power gating */
|
|
|
|
mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
|
|
|
|
ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
|
|
|
|
"BXT_PORT_CL1CM_DW28(%d)", phy);
|
|
|
|
|
|
|
|
if (phy == DPIO_PHY0)
|
|
|
|
ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
|
|
|
|
DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
|
|
|
|
"BXT_PORT_CL2CM_DW6_BC");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
|
|
|
|
* at least on stepping A this bit is read-only and fixed at 0.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (phy == DPIO_PHY0) {
|
|
|
|
u32 grc_code = dev_priv->bxt_phy_grc;
|
|
|
|
|
|
|
|
grc_code = grc_code << GRC_CODE_FAST_SHIFT |
|
|
|
|
grc_code << GRC_CODE_SLOW_SHIFT |
|
|
|
|
grc_code;
|
|
|
|
mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
|
|
|
|
GRC_CODE_NOM_MASK;
|
|
|
|
ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
|
|
|
|
"BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
|
|
|
|
|
|
|
|
mask = GRC_DIS | GRC_RDY_OVRD;
|
|
|
|
ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
|
|
|
|
"BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ok;
|
|
|
|
#undef _CHK
|
|
|
|
}
|
|
|
|
|
2016-06-13 13:44:35 +00:00
|
|
|
static uint8_t
|
|
|
|
bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
|
{
|
|
|
|
switch (pipe_config->lane_count) {
|
|
|
|
case 1:
|
|
|
|
return 0;
|
|
|
|
case 2:
|
|
|
|
return BIT(2) | BIT(0);
|
|
|
|
case 4:
|
|
|
|
return BIT(3) | BIT(2) | BIT(0);
|
|
|
|
default:
|
|
|
|
MISSING_CASE(pipe_config->lane_count);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-08-09 15:04:04 +00:00
|
|
|
static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *pipe_config,
|
|
|
|
struct drm_connector_state *conn_state)
|
2016-06-13 13:44:35 +00:00
|
|
|
{
|
|
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
|
|
|
|
enum port port = dport->port;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
|
|
|
|
int lane;
|
|
|
|
|
|
|
|
for (lane = 0; lane < 4; lane++) {
|
|
|
|
u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Note that on CHV this flag is called UPAR, but has
|
|
|
|
* the same function.
|
|
|
|
*/
|
|
|
|
val &= ~LATENCY_OPTIM;
|
|
|
|
if (intel_crtc->config->lane_lat_optim_mask & BIT(lane))
|
|
|
|
val |= LATENCY_OPTIM;
|
|
|
|
|
|
|
|
I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint8_t
|
|
|
|
bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
|
|
|
|
enum port port = dport->port;
|
|
|
|
int lane;
|
|
|
|
uint8_t mask;
|
|
|
|
|
|
|
|
mask = 0;
|
|
|
|
for (lane = 0; lane < 4; lane++) {
|
|
|
|
u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
|
|
|
|
|
|
|
|
if (val & LATENCY_OPTIM)
|
|
|
|
mask |= BIT(lane);
|
|
|
|
}
|
|
|
|
|
|
|
|
return mask;
|
|
|
|
}
|
|
|
|
|
2015-10-23 10:01:49 +00:00
|
|
|
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
|
2012-10-15 18:51:41 +00:00
|
|
|
{
|
2015-10-23 10:01:49 +00:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
to_i915(intel_dig_port->base.base.dev);
|
2012-10-26 21:05:50 +00:00
|
|
|
enum port port = intel_dig_port->port;
|
2012-10-15 18:51:41 +00:00
|
|
|
uint32_t val;
|
2013-02-24 22:35:38 +00:00
|
|
|
bool wait = false;
|
2012-10-15 18:51:41 +00:00
|
|
|
|
|
|
|
if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
|
|
|
|
val = I915_READ(DDI_BUF_CTL(port));
|
|
|
|
if (val & DDI_BUF_CTL_ENABLE) {
|
|
|
|
val &= ~DDI_BUF_CTL_ENABLE;
|
|
|
|
I915_WRITE(DDI_BUF_CTL(port), val);
|
|
|
|
wait = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
val = I915_READ(DP_TP_CTL(port));
|
|
|
|
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
|
|
|
|
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
|
|
|
|
I915_WRITE(DP_TP_CTL(port), val);
|
|
|
|
POSTING_READ(DP_TP_CTL(port));
|
|
|
|
|
|
|
|
if (wait)
|
|
|
|
intel_wait_ddi_buf_idle(dev_priv, port);
|
|
|
|
}
|
|
|
|
|
2014-05-02 04:02:48 +00:00
|
|
|
val = DP_TP_CTL_ENABLE |
|
2012-10-15 18:51:41 +00:00
|
|
|
DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
|
2016-07-28 14:50:39 +00:00
|
|
|
if (intel_dp->link_mst)
|
2014-05-02 04:02:48 +00:00
|
|
|
val |= DP_TP_CTL_MODE_MST;
|
|
|
|
else {
|
|
|
|
val |= DP_TP_CTL_MODE_SST;
|
|
|
|
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
|
|
|
|
val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
|
|
|
|
}
|
2012-10-15 18:51:41 +00:00
|
|
|
I915_WRITE(DP_TP_CTL(port), val);
|
|
|
|
POSTING_READ(DP_TP_CTL(port));
|
|
|
|
|
|
|
|
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
|
|
|
|
I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
|
|
|
|
POSTING_READ(DDI_BUF_CTL(port));
|
|
|
|
|
|
|
|
udelay(600);
|
|
|
|
}
|
2012-10-26 21:05:52 +00:00
|
|
|
|
2013-09-24 11:24:05 +00:00
|
|
|
void intel_ddi_get_config(struct intel_encoder *encoder,
|
2015-01-15 12:55:21 +00:00
|
|
|
struct intel_crtc_state *pipe_config)
|
2013-05-15 00:08:26 +00:00
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2013-05-15 00:08:26 +00:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
|
2015-01-30 10:17:23 +00:00
|
|
|
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
|
2014-11-20 21:33:59 +00:00
|
|
|
struct intel_hdmi *intel_hdmi;
|
2013-05-15 00:08:26 +00:00
|
|
|
u32 temp, flags = 0;
|
|
|
|
|
2016-03-18 15:05:42 +00:00
|
|
|
/* XXX: DSI transcoder paranoia */
|
|
|
|
if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
|
|
|
|
return;
|
|
|
|
|
2013-05-15 00:08:26 +00:00
|
|
|
temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
|
|
|
|
if (temp & TRANS_DDI_PHSYNC)
|
|
|
|
flags |= DRM_MODE_FLAG_PHSYNC;
|
|
|
|
else
|
|
|
|
flags |= DRM_MODE_FLAG_NHSYNC;
|
|
|
|
if (temp & TRANS_DDI_PVSYNC)
|
|
|
|
flags |= DRM_MODE_FLAG_PVSYNC;
|
|
|
|
else
|
|
|
|
flags |= DRM_MODE_FLAG_NVSYNC;
|
|
|
|
|
2015-01-15 12:55:22 +00:00
|
|
|
pipe_config->base.adjusted_mode.flags |= flags;
|
2013-09-06 20:29:00 +00:00
|
|
|
|
|
|
|
switch (temp & TRANS_DDI_BPC_MASK) {
|
|
|
|
case TRANS_DDI_BPC_6:
|
|
|
|
pipe_config->pipe_bpp = 18;
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_BPC_8:
|
|
|
|
pipe_config->pipe_bpp = 24;
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_BPC_10:
|
|
|
|
pipe_config->pipe_bpp = 30;
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_BPC_12:
|
|
|
|
pipe_config->pipe_bpp = 36;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2013-09-10 14:02:54 +00:00
|
|
|
|
|
|
|
switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
|
|
|
|
case TRANS_DDI_MODE_SELECT_HDMI:
|
2014-04-24 21:54:47 +00:00
|
|
|
pipe_config->has_hdmi_sink = true;
|
2014-11-20 21:33:59 +00:00
|
|
|
intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
|
|
|
2015-11-26 16:27:07 +00:00
|
|
|
if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
|
2014-11-20 21:33:59 +00:00
|
|
|
pipe_config->has_infoframe = true;
|
2016-04-27 12:44:16 +00:00
|
|
|
/* fall through */
|
2013-09-10 14:02:54 +00:00
|
|
|
case TRANS_DDI_MODE_SELECT_DVI:
|
2016-04-27 12:44:16 +00:00
|
|
|
pipe_config->lane_count = 4;
|
|
|
|
break;
|
2013-09-10 14:02:54 +00:00
|
|
|
case TRANS_DDI_MODE_SELECT_FDI:
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_MODE_SELECT_DP_SST:
|
|
|
|
case TRANS_DDI_MODE_SELECT_DP_MST:
|
2015-07-06 13:39:15 +00:00
|
|
|
pipe_config->lane_count =
|
|
|
|
((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
|
2013-09-10 14:02:54 +00:00
|
|
|
intel_dp_get_m_n(intel_crtc, pipe_config);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2013-11-18 06:38:16 +00:00
|
|
|
|
2016-05-03 15:01:32 +00:00
|
|
|
if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
|
|
|
|
temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
|
|
|
|
if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
|
|
|
|
pipe_config->has_audio = true;
|
|
|
|
}
|
2014-04-24 21:54:52 +00:00
|
|
|
|
2016-03-24 15:50:20 +00:00
|
|
|
if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
|
|
|
|
pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
|
2013-11-18 06:38:16 +00:00
|
|
|
/*
|
|
|
|
* This is a big fat ugly hack.
|
|
|
|
*
|
|
|
|
* Some machines in UEFI boot mode provide us a VBT that has 18
|
|
|
|
* bpp and 1.62 GHz link bandwidth for eDP, which for reasons
|
|
|
|
* unknown we fail to light up. Yet the same BIOS boots up with
|
|
|
|
* 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
|
|
|
|
* max, not what it tells us to use.
|
|
|
|
*
|
|
|
|
* Note: This will still be broken if the eDP panel is not lit
|
|
|
|
* up by the BIOS, and thus we can't get the mode at module
|
|
|
|
* load.
|
|
|
|
*/
|
|
|
|
DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
|
2016-03-24 15:50:20 +00:00
|
|
|
pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
|
|
|
|
dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
|
2013-11-18 06:38:16 +00:00
|
|
|
}
|
2014-01-21 20:42:10 +00:00
|
|
|
|
2014-12-12 14:26:57 +00:00
|
|
|
intel_ddi_clock_get(encoder, pipe_config);
|
2016-06-13 13:44:35 +00:00
|
|
|
|
|
|
|
if (IS_BROXTON(dev_priv))
|
|
|
|
pipe_config->lane_lat_optim_mask =
|
|
|
|
bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
|
2013-05-15 00:08:26 +00:00
|
|
|
}
|
|
|
|
|
2013-03-26 23:44:55 +00:00
|
|
|
static bool intel_ddi_compute_config(struct intel_encoder *encoder,
|
2016-08-09 15:04:05 +00:00
|
|
|
struct intel_crtc_state *pipe_config,
|
|
|
|
struct drm_connector_state *conn_state)
|
2012-10-26 21:05:52 +00:00
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2013-03-26 23:44:55 +00:00
|
|
|
int type = encoder->type;
|
2013-05-21 22:50:22 +00:00
|
|
|
int port = intel_ddi_get_encoder_port(encoder);
|
2016-06-13 13:44:35 +00:00
|
|
|
int ret;
|
2012-10-26 21:05:52 +00:00
|
|
|
|
2013-03-26 23:44:55 +00:00
|
|
|
WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
|
2012-10-26 21:05:52 +00:00
|
|
|
|
2013-05-21 22:50:22 +00:00
|
|
|
if (port == PORT_A)
|
|
|
|
pipe_config->cpu_transcoder = TRANSCODER_EDP;
|
|
|
|
|
2012-10-26 21:05:52 +00:00
|
|
|
if (type == INTEL_OUTPUT_HDMI)
|
2016-08-09 15:04:05 +00:00
|
|
|
ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
|
2012-10-26 21:05:52 +00:00
|
|
|
else
|
2016-08-09 15:04:05 +00:00
|
|
|
ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
|
2016-06-13 13:44:35 +00:00
|
|
|
|
|
|
|
if (IS_BROXTON(dev_priv) && ret)
|
|
|
|
pipe_config->lane_lat_optim_mask =
|
|
|
|
bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
|
|
|
|
pipe_config);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
2012-10-26 21:05:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct drm_encoder_funcs intel_ddi_funcs = {
|
2016-04-18 07:04:21 +00:00
|
|
|
.reset = intel_dp_encoder_reset,
|
|
|
|
.destroy = intel_dp_encoder_destroy,
|
2012-10-26 21:05:52 +00:00
|
|
|
};
|
|
|
|
|
2013-10-09 16:52:36 +00:00
|
|
|
static struct intel_connector *
|
|
|
|
intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
|
|
|
|
{
|
|
|
|
struct intel_connector *connector;
|
|
|
|
enum port port = intel_dig_port->port;
|
|
|
|
|
2015-04-10 07:59:10 +00:00
|
|
|
connector = intel_connector_alloc();
|
2013-10-09 16:52:36 +00:00
|
|
|
if (!connector)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
|
|
|
|
if (!intel_dp_init_connector(intel_dig_port, connector)) {
|
|
|
|
kfree(connector);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return connector;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct intel_connector *
|
|
|
|
intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
|
|
|
|
{
|
|
|
|
struct intel_connector *connector;
|
|
|
|
enum port port = intel_dig_port->port;
|
|
|
|
|
2015-04-10 07:59:10 +00:00
|
|
|
connector = intel_connector_alloc();
|
2013-10-09 16:52:36 +00:00
|
|
|
if (!connector)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
|
|
|
|
intel_hdmi_init_connector(intel_dig_port, connector);
|
|
|
|
|
|
|
|
return connector;
|
|
|
|
}
|
|
|
|
|
2012-10-26 21:05:52 +00:00
|
|
|
void intel_ddi_init(struct drm_device *dev, enum port port)
|
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2012-10-26 21:05:52 +00:00
|
|
|
struct intel_digital_port *intel_dig_port;
|
|
|
|
struct intel_encoder *intel_encoder;
|
|
|
|
struct drm_encoder *encoder;
|
2013-09-12 20:12:18 +00:00
|
|
|
bool init_hdmi, init_dp;
|
2015-12-08 17:59:37 +00:00
|
|
|
int max_lanes;
|
|
|
|
|
|
|
|
if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
|
|
|
|
switch (port) {
|
|
|
|
case PORT_A:
|
|
|
|
max_lanes = 4;
|
|
|
|
break;
|
|
|
|
case PORT_E:
|
|
|
|
max_lanes = 0;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
max_lanes = 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
switch (port) {
|
|
|
|
case PORT_A:
|
|
|
|
max_lanes = 2;
|
|
|
|
break;
|
|
|
|
case PORT_E:
|
|
|
|
max_lanes = 2;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
max_lanes = 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2013-09-12 20:12:18 +00:00
|
|
|
|
|
|
|
init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
|
|
|
|
dev_priv->vbt.ddi_port_info[port].supports_hdmi);
|
|
|
|
init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
|
|
|
|
if (!init_dp && !init_hdmi) {
|
2015-08-08 00:01:16 +00:00
|
|
|
DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
|
2013-09-12 20:12:18 +00:00
|
|
|
port_name(port));
|
2015-08-08 00:01:16 +00:00
|
|
|
return;
|
2013-09-12 20:12:18 +00:00
|
|
|
}
|
2012-10-26 21:05:52 +00:00
|
|
|
|
2013-09-19 10:18:32 +00:00
|
|
|
intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
|
2012-10-26 21:05:52 +00:00
|
|
|
if (!intel_dig_port)
|
|
|
|
return;
|
|
|
|
|
|
|
|
intel_encoder = &intel_dig_port->base;
|
|
|
|
encoder = &intel_encoder->base;
|
|
|
|
|
|
|
|
drm_encoder_init(dev, encoder, &intel_ddi_funcs,
|
2016-05-27 17:59:24 +00:00
|
|
|
DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
|
2012-10-26 21:05:52 +00:00
|
|
|
|
2013-03-26 23:44:55 +00:00
|
|
|
intel_encoder->compute_config = intel_ddi_compute_config;
|
2012-10-26 21:05:52 +00:00
|
|
|
intel_encoder->enable = intel_enable_ddi;
|
2016-06-13 13:44:35 +00:00
|
|
|
if (IS_BROXTON(dev_priv))
|
|
|
|
intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
|
2012-10-26 21:05:52 +00:00
|
|
|
intel_encoder->pre_enable = intel_ddi_pre_enable;
|
|
|
|
intel_encoder->disable = intel_disable_ddi;
|
|
|
|
intel_encoder->post_disable = intel_ddi_post_disable;
|
|
|
|
intel_encoder->get_hw_state = intel_ddi_get_hw_state;
|
2013-05-15 00:08:26 +00:00
|
|
|
intel_encoder->get_config = intel_ddi_get_config;
|
2016-04-18 07:04:21 +00:00
|
|
|
intel_encoder->suspend = intel_dp_encoder_suspend;
|
2012-10-26 21:05:52 +00:00
|
|
|
|
|
|
|
intel_dig_port->port = port;
|
2013-07-12 20:54:41 +00:00
|
|
|
intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
|
|
|
|
(DDI_BUF_PORT_REVERSAL |
|
|
|
|
DDI_A_4_LANES);
|
2012-10-26 21:05:52 +00:00
|
|
|
|
2015-11-05 22:53:32 +00:00
|
|
|
/*
|
|
|
|
* Bspec says that DDI_A_4_LANES is the only supported configuration
|
|
|
|
* for Broxton. Yet some BIOS fail to set this bit on port A if eDP
|
|
|
|
* wasn't lit up at boot. Force this bit on in our internal
|
|
|
|
* configuration so that we use the proper lane count for our
|
|
|
|
* calculations.
|
|
|
|
*/
|
|
|
|
if (IS_BROXTON(dev) && port == PORT_A) {
|
|
|
|
if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
|
|
|
|
DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
|
|
|
|
intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
|
2016-01-28 23:09:37 +00:00
|
|
|
max_lanes = 4;
|
2015-11-05 22:53:32 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-01-28 23:09:37 +00:00
|
|
|
intel_dig_port->max_lanes = max_lanes;
|
|
|
|
|
2012-10-26 21:05:52 +00:00
|
|
|
intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
|
2014-08-04 06:15:09 +00:00
|
|
|
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
|
2014-03-03 14:15:28 +00:00
|
|
|
intel_encoder->cloneable = 0;
|
2012-10-26 21:05:52 +00:00
|
|
|
|
2014-08-04 06:15:09 +00:00
|
|
|
if (init_dp) {
|
|
|
|
if (!intel_ddi_init_dp_connector(intel_dig_port))
|
|
|
|
goto err;
|
2014-06-18 01:29:35 +00:00
|
|
|
|
2014-08-04 06:15:09 +00:00
|
|
|
intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
|
2015-08-10 05:05:36 +00:00
|
|
|
/*
|
|
|
|
* On BXT A0/A1, sw needs to activate DDIA HPD logic and
|
|
|
|
* interrupts to check the external panel connection.
|
|
|
|
*/
|
2015-10-20 12:22:02 +00:00
|
|
|
if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
|
2015-08-10 05:05:36 +00:00
|
|
|
dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
|
|
|
|
else
|
|
|
|
dev_priv->hotplug.irq_port[port] = intel_dig_port;
|
2014-08-04 06:15:09 +00:00
|
|
|
}
|
2013-04-10 21:28:35 +00:00
|
|
|
|
2013-09-12 20:12:18 +00:00
|
|
|
/* In theory we don't need the encoder->type check, but leave it just in
|
|
|
|
* case we have some really bad VBTs... */
|
2014-08-04 06:15:09 +00:00
|
|
|
if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
|
|
|
|
if (!intel_ddi_init_hdmi_connector(intel_dig_port))
|
|
|
|
goto err;
|
2013-04-10 21:28:35 +00:00
|
|
|
}
|
2014-08-04 06:15:09 +00:00
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
err:
|
|
|
|
drm_encoder_cleanup(encoder);
|
|
|
|
kfree(intel_dig_port);
|
2012-10-26 21:05:52 +00:00
|
|
|
}
|