[ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 20:45:02 +00:00
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/*
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2008-08-05 15:14:15 +00:00
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* arch/arm/mach-loki/include/mach/loki.h
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[ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 20:45:02 +00:00
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*
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* Generic definitions for Marvell Loki (88RC8480) SoC flavors
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_LOKI_H
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#define __ASM_ARCH_LOKI_H
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/*
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* Marvell Loki (88RC8480) address maps.
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*
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* phys
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* d0000000 on-chip peripheral registers
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* e0000000 PCIe 0 Memory space
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* e8000000 PCIe 1 Memory space
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* f0000000 PCIe 0 I/O space
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* f0100000 PCIe 1 I/O space
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*
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* virt phys size
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* fed00000 d0000000 1M on-chip peripheral registers
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* fee00000 f0000000 64K PCIe 0 I/O space
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* fef00000 f0100000 64K PCIe 1 I/O space
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*/
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#define LOKI_REGS_PHYS_BASE 0xd0000000
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#define LOKI_REGS_VIRT_BASE 0xfed00000
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#define LOKI_REGS_SIZE SZ_1M
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#define LOKI_PCIE0_IO_PHYS_BASE 0xf0000000
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#define LOKI_PCIE0_IO_VIRT_BASE 0xfee00000
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#define LOKI_PCIE0_IO_BUS_BASE 0x00000000
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#define LOKI_PCIE0_IO_SIZE SZ_64K
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#define LOKI_PCIE1_IO_PHYS_BASE 0xf0100000
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#define LOKI_PCIE1_IO_VIRT_BASE 0xfef00000
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#define LOKI_PCIE1_IO_BUS_BASE 0x00000000
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#define LOKI_PCIE1_IO_SIZE SZ_64K
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#define LOKI_PCIE0_MEM_PHYS_BASE 0xe0000000
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#define LOKI_PCIE0_MEM_SIZE SZ_128M
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#define LOKI_PCIE1_MEM_PHYS_BASE 0xe8000000
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#define LOKI_PCIE1_MEM_SIZE SZ_128M
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/*
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* Register Map
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*/
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#define DEV_BUS_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x10000)
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#define DEV_BUS_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x10000)
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#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
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#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
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#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
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#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
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#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000)
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#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x))
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
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#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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#define BRIDGE_INT_TIMER1_CLR 0x0004
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
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#define IRQ_CAUSE_OFF 0x0000
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#define IRQ_MASK_OFF 0x0004
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
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#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000)
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#define PCIE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x40000)
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#define SAS0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x80000)
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#define SAS1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x90000)
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#define GE0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xa0000)
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#define GE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xa0000)
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#define GE1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xb0000)
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#define GE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xb0000)
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#define DDR_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xf0000)
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#define DDR_REG(x) (DDR_VIRT_BASE | (x))
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#define GPIO_MAX 8
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#endif
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