leandrof/linux
1
0
Fork 0
forked from Minki/linux
Code Issues Pull Requests Packages Projects Releases Wiki Activity
f5a734827b
linux/drivers/video/fbdev/omap2/dss/dispc.c

4079 lines
99 KiB
C
Raw Normal View History

OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
/*
* linux/drivers/video/omap2/dss/dispc.c
*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
*
* Some code and ideas taken from drivers/video/omap/ driver
* by Imre Deak.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define DSS_SUBSYS_NAME "DISPC"
#include <linux/kernel.h>
#include <linux/dma-mapping.h>
#include <linux/vmalloc.h>
video: Add export.h for THIS_MODULE/EXPORT_SYMBOL to drivers/video With module.h being implicitly everywhere via device.h, the absence of explicitly including something for EXPORT_SYMBOL went unnoticed. Since we are heading to fix things up and clean module.h from the device.h file, we need to explicitly include these files now. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2011-07-10 17:20:26 +00:00
#include <linux/export.h>
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/seq_file.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
OMAP: DSS2: DSI: use BTA to end the frame transfer Previously a work was started on FRAMEDONE interrupt, and this work either sent a BTA synchronously or looped until TE_SIZE was zero, to wait for the end of the transfer. This patch changes a BTA to be sent asynchronously from FRAMEDONE interrupt, and when a BTA interrupt is received, the transfer is finished. This way we do the whole process asynchronously, and also inside interrupt context. This will give us much better latency to handle the end of the frame than with the previous work based solution. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-06-09 12:31:01 +00:00
#include <linux/hardirq.h>
OMAP: DSS2: remove extra includes from include/video/omapdss.h omapdss.h included platform_device.h and atomic.h, neither of which is needed by omapdss.h. Remove those includes from omapdss.h, and fix the affected .c files which did not include platform_device.h even though they should. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-23 08:51:18 +00:00
#include <linux/platform_device.h>
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
#include <linux/pm_runtime.h>
OMAPDSS: add missing sizes.h includes When compiling on x86, we get compilation errors for dss.c and dispc.c: drivers/video/omap2/dss/dispc.c:126:11: error: ‘SZ_4K’ undeclared here (not in a function) include <linux/sizes.h> to fix compilation. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-28 10:54:35 +00:00
#include <linux/sizes.h>
OMAPDSS: DISPC: program dispc polarities to control module On DRA7xx, DISPC needs to write output signal polarities not only to a DISPC register, like for all earlier DSS versions, but to control module's CTRL_CORE_SMA_SW_1 register. This patch adds support to write the polarities to control module. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-09-05 19:15:03 +00:00
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/of.h>
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Move display.h to include/video/ arch/arm/plat-omap/include/plat/display.h is an include for the OMAP DSS driver. A more logical place for it is in include/video. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-11 11:05:07 +00:00
#include <video/omapdss.h>
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
#include "dss.h"
OMAP: DSS2: Use dss_features framework on DSS2 code Calls init functions of dss_features during dss_probe, and the following features are made omapxxxx independent: - number of managers, overlays - supported color modes for each overlay - supported displays for each manager - global aplha, and restriction of global alpha for video1 pipeline - The register field ranges : FIRHINC, FIRVINC, FIFOHIGHTHRESHOLD FIFOLOWTHRESHOLD and FIFOSIZE Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-09-15 13:50:00 +00:00
#include "dss_features.h"
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
#include "dispc.h"
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
/* DISPC */
OMAP: DSS2: Represent DISPC register defines with channel as parameter On OMAP4, we have a new DISPC channel for Overlay Manager LCD2. There is a set of regsiters for LCD2 channel similar to the existing LCD channel, like DISPC_CONTROL2, DISPC_DIVISOR2, DISPC_CONFIG2 and so on. Introduce new enum members for LCD2 Channel and corresponding Overlay Manager in display.h. Represent the following DISPC register defines with channel as a parameter to differentiate between LCD and LCD2 registers (and also DIGIT in some cases): DISPC_DEFAULT_COLOR, DISPC_TRANS_COLOR, DISPC_TIMING_H, DISPC_TIMING_V, DISPC_POL_FREQ, DISPC_DIVISOR, DISPC_SIZE_LCD, DISPC_DATA_CYCLEk, DISPC_CPR_COEF_R, DISPC_CPR_COEF_G and DISPC_CPR_COEF_B This parametrization helps in reducing the number of register defines for DISPC. Replace the existing reads/writes to these registers in this new way. Also, Introduce defines for registers DISPC_CONTROL2 and DISPC_CONFIG2 which are used exclusively for LCD2 channel. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:09 +00:00
#define DISPC_SZ_REGS SZ_4K
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Fix FIFO threshold and burst size for OMAP4 The DMA FIFO threshold registers and burst size registers have changed for OMAP4. The current code only handles OMAP2/3 case, and so the values are a bit off for OMAP4. A summary of the differences between OMAP2/3 and OMAP4: Burst size: OMAP2/3: 4 x 32 bits / 8 x 32 bits / 16 x 32 bits OMAP4: 2 x 128 bits / 4 x 128 bits / 8 x 128 bits Threshold size: OMAP2/3: in bytes (8 bit units) OMAP4: in 128bit units This patch fixes the issue by creating two new helper functions in dss_features: dss_feat_get_buffer_size_unit() and dss_feat_get_burst_size_unit(). These return (in bytes) the unit size for threshold registers and unit size for burst size register, respectively, and are used to calculate correct values. For the threshold size the usage is straightforward. However, the burst size register has different multipliers for OMAP2/3 and OMAP4. This patch solves the problem by defining the multipliers for the burst size as 2x, 4x and 8x, which fit fine for the OMAP4 burst size definition (i.e. burst size unit for OMAP4 is 128bits), but requires a slight twist on OMAP2/3 by defining the burst size unit as 64bit. As the driver in practice always uses the maximum burst size, and no use case currently exists where we would want to use a smaller burst size, this patch changes the driver to hardcode the burst size when initializing DISPC. This makes the threshold configuration code somewhat simpler. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:35:36 +00:00
enum omap_burst_size {
BURST_SIZE_X2 = 0,
BURST_SIZE_X4 = 1,
BURST_SIZE_X8 = 2,
};
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
#define REG_GET(idx, start, end) \
FLD_GET(dispc_read_reg(idx), start, end)
#define REG_FLD_MOD(idx, val, start, end) \
dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
struct dispc_features {
u8 sw_start;
u8 fp_start;
u8 bp_start;
u16 sw_max;
u16 vp_max;
u16 hp_max;
OMAPDSS: Add overlay manager width and height limits as a dispc feature The overlay manager width and height vary in OMAP5 from previous OMAPs in terms of maximum limit and register field positions. Add parameters in dispc_features for these. Also remove params related to manager width and height from dss_features, as we want to maintain a feature list for individual IPs. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-14 08:20:15 +00:00
u8 mgr_width_start;
u8 mgr_height_start;
u16 mgr_width_max;
u16 mgr_height_max;
omapdss: DISPC: add max pixel clock limits for LCD and TV managers Each version of OMAP has a limitation on the maximum pixel clock frequency supported by an overlay manager. This limit isn't checked by omapdss. Add dispc feats for lcd and tv managers and check whether the target timings can be supported or not. The pixel clock limitations are actually more complex. They depend on which OPP OMAP is in, and they also depend on which encoder is the manager connected to. The OPP dependence is ignored as DSS forces the PM framework to be on OPP100 when DSS is enabled, and the encoder dependencies are ignored by DISPC for now. These limits should come from the encoder driver. The OMAP2 TRM doesn't mention the maximum pixel clock limit. This value is left as half of DSS_FCLK, as OMAP2 requires the PCD to be atleast 2. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:22 +00:00
unsigned long max_lcd_pclk;
unsigned long max_tv_pclk;
OMAPDSS: DISPC: pass pclk & lclk to calc_scaling In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes calc_scaling to get pclk and lclk as parameters. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:43:29 +00:00
int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
const struct omap_video_timings *mgr_timings,
u16 width, u16 height, u16 out_width, u16 out_height,
enum omap_color_mode color_mode, bool *five_taps,
int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
OMAPDSS: DISPC: pass pclk to calc_core_clk() In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes calc_core_clk() function to get pclk as a parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:36:11 +00:00
unsigned long (*calc_core_clk) (unsigned long pclk,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
u16 width, u16 height, u16 out_width, u16 out_height,
bool mem_to_mem);
OMAPDSS: Improve fifo management code OMAP4+ allows assigning the overlay FIFOs freely, but that is not supported by omapdss yet. This patch takes a step forward by improving the fifo management to be more flexible. dispc.c is changed to keep track of the sizes of each fifo, and also the overlay using each fifo. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:56:57 +00:00
u8 num_fifos;
OMAPDSS: Use WB fifo for GFX overlay OMAP4's GFX overlay has smaller fifo than the rest of the overlays (including writeback "overlay"). This seems to be the reason for underflows in some more demanding scenarios. We can avoid the problems by using the WB fifo for GFX overlay, and vice versa. WB usage is not supported yet, but when it will, it should perform just fine with smaller fifo as there are no hard realtime constraints with WB. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:57:02 +00:00
/* swap GFX & WB fifos */
bool gfx_fifo_workaround:1;
OMAPDSS: DISPC: add no_framedone_tv feat OMAP2/3 do not have FRAMEDONETV irq, but later omaps do. We currently always return 0 from dispc_mgr_get_framedone_irq() for TV output to be compatible with OMAP2/3. This patch implements "no_framedone_tv" dispc-feature that is used in dispc_mgr_get_framedone_irq to return either 0 for OMAP2/3, or the correct IRQ number for FRAMEDONETV on OMAP4+. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-08 08:01:33 +00:00
/* no DISPC_IRQ_FRAMEDONETV on this SoC */
bool no_framedone_tv:1;
OMAPDSS: DISPC: Revert to older DISPC Smart Standby mechanism for OMAP5 DISPC on OMAP5 has a more optimised mechanism of asserting Mstandby to achieve more power savings when DISPC is configured in Smart Standby mode. This mechanism leads to underflows when multiple DISPC pipes are enabled. There is a register field which can let us revert to the older mechanism of asserting Mstandby. Configure this field to prevent underflows. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:25 +00:00
/* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
bool mstandby_workaround:1;
OMAPDSS: DISPC: Preload more data in pipeline DMAs for OMAP4+ SoCs DISPC pipeline DMAs preload some bytes of pixel data in the vertical blanking region before the start of each frame. The preload ensures the pipeline doesn't underflow when the active region of the display starts. DISPC_GFX/VIDp_PRELOAD registers allow us to program how many bytes of data should be preloaded for each pipeline. Calculating a precise preload value would be a complex function of the pixel clock of the connected display, the vertical blanking duration and the interconnect traffic at that instance. If the register is left untouched, a default value is preloaded. We observe underflows for OMAP4+ SoCs for certain bandwidth intensive use cases with many other initiators active, and in situations where memory access isn't very efficient(like accessing Tiler mapped buffers and EMIF configured in non-interleaved more). The cause of the underflow is because the default preload value isn't sufficient for the DMA to reach a steady state. We configure the PRELOAD register such that the pipelines preload data up to the high threshold of the FIFO. Preloading lot of data for older SoCs can have a negative impact. Due to slower interconnects, it's possible that the DISPC DMA cannot preload up to the high threshold within the vertical blanking region of the panel. We leave the PRELOAD registers to their reset values since we haven't faced underflows with these SoCs because of low value of PRELOAD. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-12-17 11:10:21 +00:00
bool set_max_preload:1;
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
};
OMAPDSS: Improve fifo management code OMAP4+ allows assigning the overlay FIFOs freely, but that is not supported by omapdss yet. This patch takes a step forward by improving the fifo management to be more flexible. dispc.c is changed to keep track of the sizes of each fifo, and also the overlay using each fifo. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:56:57 +00:00
#define DISPC_MAX_NR_FIFOS 5
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
static struct {
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
struct platform_device *pdev;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
void __iomem *base;
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
OMAP: DSS2: Have separate irq handlers for DISPC and DSI Currently, the core DSS platform device requests for an irq line for OMAP2 and OMAP3. Make DISPC and DSI platform devices request for a shared IRQ line. On OMAP3, the logical OR of DSI and DISPC interrupt lines goes to the MPU. There is a register DSS_IRQSTATUS which tells if the interrupt came from DISPC or DSI. On OMAP2, there is no DSI, only DISPC interrupts goto the MPU. There is no DSS_IRQSTATUS register. Hence, it makes more sense to have separate irq handlers corresponding to the DSS sub modules instead of having a common handler. Since on OMAP3 the logical OR of the lines goes to MPU, the irq line is shared among the IRQ handlers. The hwmod irq info has been removed for DSS to DISPC and DSI for OMAP2 and OMAP3 hwmod databases. The Probes of DISPC and DSI now request for irq handlers. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-02-23 08:41:03 +00:00
int irq;
OMAPDSS: fix shared irq handlers DSS uses shared irq handlers for DISPC and DSI, because on OMAP3, the DISPC and DSI share the same irq line. However, the irq handlers presume that the hardware is enabled, which, in theory, may not be the case with shared irq handlers. So if an interrupt happens while the DISPC/DSI is off, the kernel will halt as the irq handler tries to access the DISPC/DSI registers. In practice that should never happen, as both DSI and DISPC are in the same power domain. So if there's an IRQ for one of them, the other is also enabled. However, if CONFIG_DEBUG_SHIRQ is enabled, the kernel will generate a spurious IRQ, which then causes the problem. This patch adds an is_enabled field for both DISPC and DSI, which is used to track if the HW is enabled. For DISPC the code is slightly more complex, as the users of DISPC can register the interrupt handler, and we want to hide the is_enabled handling from the users of DISPC. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-11 10:49:55 +00:00
irq_handler_t user_handler;
void *user_data;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: store core clk rate Store dispc core clock rate so that it's available for calculations even if the HW is disabled. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-06 13:54:11 +00:00
unsigned long core_clk_rate;
OMAPDSS: remove dispc's dependency to VENC/HDMI DISPC needs to know the clock rate for DIGIT (i.e. TV) channel, and this clock is provided by either VENC or HDMI modules. Currently DISPC will call a function in VENC/HDMI, asking what the clock rate is. This means we have a fixed dependency from DISPC to both VENC and HDMI. To have a more generic approach, and in particular to allow adding OMAP5 HDMI driver, we need to remove this dependency. This patch makes VENC/HDMI inform DISPC when the their clock changes, thus reversing the dependency and removing the issue. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-05-16 07:44:13 +00:00
unsigned long tv_pclk_rate;
OMAPDSS: DISPC: store core clk rate Store dispc core clock rate so that it's available for calculations even if the HW is disabled. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-06 13:54:11 +00:00
OMAPDSS: Improve fifo management code OMAP4+ allows assigning the overlay FIFOs freely, but that is not supported by omapdss yet. This patch takes a step forward by improving the fifo management to be more flexible. dispc.c is changed to keep track of the sizes of each fifo, and also the overlay using each fifo. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:56:57 +00:00
u32 fifo_size[DISPC_MAX_NR_FIFOS];
/* maps which plane is using a fifo. fifo-id -> plane-id */
int fifo_assignment[DISPC_MAX_NR_FIFOS];
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: DISPC: Fix context save/restore The current method of saving and restoring the context could cause a restore before saving, effectively "restoring" zero values to registers. Add ctx_valid field to indicate if the saved context is valid and can be restored. Also restructure the code to save the ctx_loss_count in save_context(), which makes more sense than the previous method of storing new ctx_loss_count in dispc_need_ctx_restore. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-01 12:54:06 +00:00
bool ctx_valid;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
OMAP: DSS2: Collect interrupt statistics Collect interrupt statistics, printable via debugfs: debugfs/omapdss/dispc_irq debugfs/omapdss/dsi_irq The counters are reset when printed. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-12-17 12:35:21 +00:00
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
const struct dispc_features *feat;
OMAPDSS: fix shared irq handlers DSS uses shared irq handlers for DISPC and DSI, because on OMAP3, the DISPC and DSI share the same irq line. However, the irq handlers presume that the hardware is enabled, which, in theory, may not be the case with shared irq handlers. So if an interrupt happens while the DISPC/DSI is off, the kernel will halt as the irq handler tries to access the DISPC/DSI registers. In practice that should never happen, as both DSI and DISPC are in the same power domain. So if there's an IRQ for one of them, the other is also enabled. However, if CONFIG_DEBUG_SHIRQ is enabled, the kernel will generate a spurious IRQ, which then causes the problem. This patch adds an is_enabled field for both DISPC and DSI, which is used to track if the HW is enabled. For DISPC the code is slightly more complex, as the users of DISPC can register the interrupt handler, and we want to hide the is_enabled handling from the users of DISPC. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-11 10:49:55 +00:00
bool is_enabled;
OMAPDSS: DISPC: program dispc polarities to control module On DRA7xx, DISPC needs to write output signal polarities not only to a DISPC register, like for all earlier DSS versions, but to control module's CTRL_CORE_SMA_SW_1 register. This patch adds support to write the polarities to control module. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-09-05 19:15:03 +00:00
struct regmap *syscon_pol;
u32 syscon_pol_offset;
OMAPDSS: DISPC: lock access to DISPC_CONTROL & DISPC_CONFIG Dispc driver presumes that the callers handle locking for all normal functions. However, omapdrm doesn't handle this, and presumes that all overlay manager registers are private to that overlay manager, and thus presumes that configurations for overlay managers can be written via different threads freely. For many registers the above is true. The exceptions are DISPC_CONTROL and DISPC_CONFIG registers, which contain bits for both LCD and TV overlay managers. Fixing this properly in omapdrm means a big omapdrm rewrite. So, for now, add locking to dispc for the problematic registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reported-by: Somnath Mukherjee <somnath@ti.com>
2014-11-10 10:23:00 +00:00
/* DISPC_CONTROL & DISPC_CONFIG lock*/
spinlock_t control_lock;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
} dispc;
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
enum omap_color_component {
/* used for all color formats for OMAP3 and earlier
* and for RGB and Y color component on OMAP4
*/
DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
/* used for UV component for
* OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
* color formats on OMAP4
*/
DISPC_COLOR_COMPONENT_UV = 1 << 1,
};
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
enum mgr_reg_fields {
DISPC_MGR_FLD_ENABLE,
DISPC_MGR_FLD_STNTFT,
DISPC_MGR_FLD_GO,
DISPC_MGR_FLD_TFTDATALINES,
DISPC_MGR_FLD_STALLMODE,
DISPC_MGR_FLD_TCKENABLE,
DISPC_MGR_FLD_TCKSELECTION,
DISPC_MGR_FLD_CPR,
DISPC_MGR_FLD_FIFOHANDCHECK,
/* used to maintain a count of the above fields */
DISPC_MGR_FLD_NUM,
};
OMAPDSS: Change struct reg_field to dispc_reg_field Avoid colision with regmap's struct reg_field definition by renaming omapdss's struct reg_field to dispc_reg_field, and moving it inside dispc.c as that's the only place it is used. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-11 13:25:06 +00:00
struct dispc_reg_field {
u16 reg;
u8 high;
u8 low;
};
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
static const struct {
const char *name;
u32 vsync_irq;
u32 framedone_irq;
u32 sync_lost_irq;
OMAPDSS: Change struct reg_field to dispc_reg_field Avoid colision with regmap's struct reg_field definition by renaming omapdss's struct reg_field to dispc_reg_field, and moving it inside dispc.c as that's the only place it is used. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-11 13:25:06 +00:00
struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
} mgr_desc[] = {
[OMAP_DSS_CHANNEL_LCD] = {
.name = "LCD",
.vsync_irq = DISPC_IRQ_VSYNC,
.framedone_irq = DISPC_IRQ_FRAMEDONE,
.sync_lost_irq = DISPC_IRQ_SYNC_LOST,
.reg_desc = {
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
[DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
[DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
[DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
[DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
},
},
[OMAP_DSS_CHANNEL_DIGIT] = {
.name = "DIGIT",
.vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
OMAPDSS: DISPC: add no_framedone_tv feat OMAP2/3 do not have FRAMEDONETV irq, but later omaps do. We currently always return 0 from dispc_mgr_get_framedone_irq() for TV output to be compatible with OMAP2/3. This patch implements "no_framedone_tv" dispc-feature that is used in dispc_mgr_get_framedone_irq to return either 0 for OMAP2/3, or the correct IRQ number for FRAMEDONETV on OMAP4+. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-08 08:01:33 +00:00
.framedone_irq = DISPC_IRQ_FRAMEDONETV,
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
.sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
.reg_desc = {
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
[DISPC_MGR_FLD_STNTFT] = { },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
[DISPC_MGR_FLD_TFTDATALINES] = { },
[DISPC_MGR_FLD_STALLMODE] = { },
[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
[DISPC_MGR_FLD_CPR] = { },
[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
},
},
[OMAP_DSS_CHANNEL_LCD2] = {
.name = "LCD2",
.vsync_irq = DISPC_IRQ_VSYNC2,
.framedone_irq = DISPC_IRQ_FRAMEDONE2,
.sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
.reg_desc = {
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
[DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
[DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
[DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
[DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
},
},
OMAPDSS: Add LCD3 overlay manager and Clock and IRQ support The support for LCD3 manager has been added into the manager module. LCD3 panel has registers as DISPC_CONTROL3 and DISPC_CONFIG3 just like those in LCD and LCD2 panels. These registers control the Display Controller (DISPC) module for LCD3 output. The three LCDs support Display Serial Interface (DSI), Remote Frame Buffer Interface (RFBI) and Parallel CMOS Output Interface (DPI). These LCDs can be connected through parallel output interface using DISPC and RFBI or DPI. For serial interface DSS uses DSI. The LCD3 panel, just like LCD and LCD2 panels, has a clock switch in DSS_CTRL register which has been enabled. The clock switch chooses between DSS_CLK and DPLL_DSI1_C_CLK1 as source for LCD3_CLK. New IRQs as DISPC_IRQ_VSYNC3, DISPC_IRQ_FRAMEDONE3, DISPC_IRQ_ACBIAS_COUNT_STAT3 and DISPC_IRQ_SYNC_LOST3 have been added specific to the new manager. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-29 05:13:13 +00:00
[OMAP_DSS_CHANNEL_LCD3] = {
.name = "LCD3",
.vsync_irq = DISPC_IRQ_VSYNC3,
.framedone_irq = DISPC_IRQ_FRAMEDONE3,
.sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
.reg_desc = {
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
[DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
[DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
[DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
[DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
},
},
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
};
OMAPDSS: DISPC: Configure color conversion coefficients for writeback Writeback pipeline receives RGB data from one of the overlays or one of the overlay managers. If the target color mode is YUV422 or NV12, we need to convert the RGB pixels to YUV. The scaler in WB then converts it to the target color mode. Hence, the color conversion coefficients that need to be programmed are the ones which convert a RGB24 pixel to YUV444. Program these coefficients for writeback pipeline. Rearrange the code a bit to configure different coefficients for overlays and writeback. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-11 06:34:47 +00:00
struct color_conv_coef {
int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
int full_range;
};
OMAPDSS: DISPC: Don't pass channel out when configuring overlays dispc_ovl_setup_common() is to be used by both overlays and writeback. We pass channel out to figure out what manager the overlay is connected to, to determine the pixel clock rate. This is used to decide the scaling limitations for that overlay. writeback doesn't have a channel out, it has a channel in field which tells where writeback gets its input from. These are 2 different fields, and this prevents us reusing the overlay configuration code for writeback. To overcome this, we now pass omap_plane to overlay related functions rather than passing channel out. We create helper functions which can derive pclk/lclk from the omap_plane id. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:28:52 +00:00
static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Remove usage of struct dispc_reg struct dispc_reg was originally used while migrating from old omapfb to catch cases where the arguments to dispc_read_reg/dispc_write_reg were in wrong order, since old omapfb had the arguments in reverse order. Remove this struct and use u16 instead Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:51 +00:00
static inline void dispc_write_reg(const u16 idx, u32 val)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: Remove usage of struct dispc_reg struct dispc_reg was originally used while migrating from old omapfb to catch cases where the arguments to dispc_read_reg/dispc_write_reg were in wrong order, since old omapfb had the arguments in reverse order. Remove this struct and use u16 instead Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:51 +00:00
__raw_writel(val, dispc.base + idx);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: Remove usage of struct dispc_reg struct dispc_reg was originally used while migrating from old omapfb to catch cases where the arguments to dispc_read_reg/dispc_write_reg were in wrong order, since old omapfb had the arguments in reverse order. Remove this struct and use u16 instead Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:51 +00:00
static inline u32 dispc_read_reg(const u16 idx)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: Remove usage of struct dispc_reg struct dispc_reg was originally used while migrating from old omapfb to catch cases where the arguments to dispc_read_reg/dispc_write_reg were in wrong order, since old omapfb had the arguments in reverse order. Remove this struct and use u16 instead Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:51 +00:00
return __raw_readl(dispc.base + idx);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
{
OMAPDSS: Change struct reg_field to dispc_reg_field Avoid colision with regmap's struct reg_field definition by renaming omapdss's struct reg_field to dispc_reg_field, and moving it inside dispc.c as that's the only place it is used. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-11 13:25:06 +00:00
const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
return REG_GET(rfld.reg, rfld.high, rfld.low);
}
static void mgr_fld_write(enum omap_channel channel,
enum mgr_reg_fields regfld, int val) {
OMAPDSS: Change struct reg_field to dispc_reg_field Avoid colision with regmap's struct reg_field definition by renaming omapdss's struct reg_field to dispc_reg_field, and moving it inside dispc.c as that's the only place it is used. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-11 13:25:06 +00:00
const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
OMAPDSS: DISPC: lock access to DISPC_CONTROL & DISPC_CONFIG Dispc driver presumes that the callers handle locking for all normal functions. However, omapdrm doesn't handle this, and presumes that all overlay manager registers are private to that overlay manager, and thus presumes that configurations for overlay managers can be written via different threads freely. For many registers the above is true. The exceptions are DISPC_CONTROL and DISPC_CONFIG registers, which contain bits for both LCD and TV overlay managers. Fixing this properly in omapdrm means a big omapdrm rewrite. So, for now, add locking to dispc for the problematic registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reported-by: Somnath Mukherjee <somnath@ti.com>
2014-11-10 10:23:00 +00:00
const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
unsigned long flags;
if (need_lock)
spin_lock_irqsave(&dispc.control_lock, flags);
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
OMAPDSS: DISPC: lock access to DISPC_CONTROL & DISPC_CONFIG Dispc driver presumes that the callers handle locking for all normal functions. However, omapdrm doesn't handle this, and presumes that all overlay manager registers are private to that overlay manager, and thus presumes that configurations for overlay managers can be written via different threads freely. For many registers the above is true. The exceptions are DISPC_CONTROL and DISPC_CONFIG registers, which contain bits for both LCD and TV overlay managers. Fixing this properly in omapdrm means a big omapdrm rewrite. So, for now, add locking to dispc for the problematic registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reported-by: Somnath Mukherjee <somnath@ti.com>
2014-11-10 10:23:00 +00:00
if (need_lock)
spin_unlock_irqrestore(&dispc.control_lock, flags);
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
#define SR(reg) \
OMAP: DSS2: Remove usage of struct dispc_reg struct dispc_reg was originally used while migrating from old omapfb to catch cases where the arguments to dispc_read_reg/dispc_write_reg were in wrong order, since old omapfb had the arguments in reverse order. Remove this struct and use u16 instead Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:51 +00:00
dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
#define RR(reg) \
OMAP: DSS2: Remove usage of struct dispc_reg struct dispc_reg was originally used while migrating from old omapfb to catch cases where the arguments to dispc_read_reg/dispc_write_reg were in wrong order, since old omapfb had the arguments in reverse order. Remove this struct and use u16 instead Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:51 +00:00
dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
static void dispc_save_context(void)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
int i, j;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
DSSDBG("dispc_save_context\n");
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
SR(IRQENABLE);
SR(CONTROL);
SR(CONFIG);
SR(LINE_NUMBER);
OMAPDSS/OMAP_VOUT: Fix incorrect OMAP3-alpha compatibility setting On OMAP3, in order to enable alpha blending for LCD and TV managers, we needed to set LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits in DISPC_CONFIG. On OMAP4, alpha blending is always enabled by default, if the above bits are set, we switch to an OMAP3 compatibility mode where the zorder values in the pipeline attribute registers are ignored and a fixed priority is configured. Rename the manager_info member "alpha_enabled" to "partial_alpha_enabled" for more clarity. Introduce two dss_features FEAT_ALPHA_FIXED_ZORDER and FEAT_ALPHA_FREE_ZORDER which represent OMAP3-alpha compatibility mode and OMAP4 alpha mode respectively. Introduce an overlay cap for ZORDER. The DSS2 user is expected to check for the ZORDER cap, if an overlay doesn't have this cap, the user is expected to set the parameter partial_alpha_enabled. If the overlay has ZORDER cap, the DSS2 user can assume that alpha blending is already enabled. Don't support OMAP3 compatibility mode for now. Trying to read/write to alpha_blending_enabled sysfs attribute issues a warning for OMAP4 and does not set the LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits. Change alpha_enabled to partial_alpha_enabled in the omap_vout driver. Use overlay cap "OMAP_DSS_OVL_CAP_GLOBAL_ALPHA" to check if overlay supports alpha blending or not. Replace this with checks for VIDEO1 pipeline. Cc: linux-media@vger.kernel.org Cc: Lajos Molnar <molnar@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Acked-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-26 06:17:29 +00:00
if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
OMAP: DSS2: Add new FEAT definitions for features missing from OMAP2 OMAP2 doesn't have CPR, PRELOAD nor FIR_COEF_V registers. Add new feature definitions for those, and check the feature before accessing those registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 11:22:16 +00:00
SR(GLOBAL_ALPHA);
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
if (dss_has_feature(FEAT_MGR_LCD2)) {
SR(CONTROL2);
SR(CONFIG2);
}
OMAPDSS: Add LCD3 overlay manager and Clock and IRQ support The support for LCD3 manager has been added into the manager module. LCD3 panel has registers as DISPC_CONTROL3 and DISPC_CONFIG3 just like those in LCD and LCD2 panels. These registers control the Display Controller (DISPC) module for LCD3 output. The three LCDs support Display Serial Interface (DSI), Remote Frame Buffer Interface (RFBI) and Parallel CMOS Output Interface (DPI). These LCDs can be connected through parallel output interface using DISPC and RFBI or DPI. For serial interface DSS uses DSI. The LCD3 panel, just like LCD and LCD2 panels, has a clock switch in DSS_CTRL register which has been enabled. The clock switch chooses between DSS_CLK and DPLL_DSI1_C_CLK1 as source for LCD3_CLK. New IRQs as DISPC_IRQ_VSYNC3, DISPC_IRQ_FRAMEDONE3, DISPC_IRQ_ACBIAS_COUNT_STAT3 and DISPC_IRQ_SYNC_LOST3 have been added specific to the new manager. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-29 05:13:13 +00:00
if (dss_has_feature(FEAT_MGR_LCD3)) {
SR(CONTROL3);
SR(CONFIG3);
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
SR(DEFAULT_COLOR(i));
SR(TRANS_COLOR(i));
SR(SIZE_MGR(i));
if (i == OMAP_DSS_CHANNEL_DIGIT)
continue;
SR(TIMING_H(i));
SR(TIMING_V(i));
SR(POL_FREQ(i));
SR(DIVISORo(i));
SR(DATA_CYCLE1(i));
SR(DATA_CYCLE2(i));
SR(DATA_CYCLE3(i));
OMAP: DSS2: Add new FEAT definitions for features missing from OMAP2 OMAP2 doesn't have CPR, PRELOAD nor FIR_COEF_V registers. Add new feature definitions for those, and check the feature before accessing those registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 11:22:16 +00:00
if (dss_has_feature(FEAT_CPR)) {
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
SR(CPR_COEF_R(i));
SR(CPR_COEF_G(i));
SR(CPR_COEF_B(i));
OMAP: DSS2: Add new FEAT definitions for features missing from OMAP2 OMAP2 doesn't have CPR, PRELOAD nor FIR_COEF_V registers. Add new feature definitions for those, and check the feature before accessing those registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 11:22:16 +00:00
}
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (i = 0; i < dss_feat_get_num_ovls(); i++) {
SR(OVL_BA0(i));
SR(OVL_BA1(i));
SR(OVL_POSITION(i));
SR(OVL_SIZE(i));
SR(OVL_ATTRIBUTES(i));
SR(OVL_FIFO_THRESHOLD(i));
SR(OVL_ROW_INC(i));
SR(OVL_PIXEL_INC(i));
if (dss_has_feature(FEAT_PRELOAD))
SR(OVL_PRELOAD(i));
if (i == OMAP_DSS_GFX) {
SR(OVL_WINDOW_SKIP(i));
SR(OVL_TABLE_BA(i));
continue;
}
SR(OVL_FIR(i));
SR(OVL_PICTURE_SIZE(i));
SR(OVL_ACCU0(i));
SR(OVL_ACCU1(i));
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (j = 0; j < 8; j++)
SR(OVL_FIR_COEF_H(i, j));
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (j = 0; j < 8; j++)
SR(OVL_FIR_COEF_HV(i, j));
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (j = 0; j < 5; j++)
SR(OVL_CONV_COEF(i, j));
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
if (dss_has_feature(FEAT_FIR_COEF_V)) {
for (j = 0; j < 8; j++)
SR(OVL_FIR_COEF_V(i, j));
}
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
SR(OVL_BA0_UV(i));
SR(OVL_BA1_UV(i));
SR(OVL_FIR2(i));
SR(OVL_ACCU2_0(i));
SR(OVL_ACCU2_1(i));
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (j = 0; j < 8; j++)
SR(OVL_FIR_COEF_H2(i, j));
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (j = 0; j < 8; j++)
SR(OVL_FIR_COEF_HV2(i, j));
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (j = 0; j < 8; j++)
SR(OVL_FIR_COEF_V2(i, j));
}
if (dss_has_feature(FEAT_ATTR2))
SR(OVL_ATTRIBUTES2(i));
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
}
OMAP4: DSS2: Using dss_features to set independent core clock divider Using dss_features to select independent core clock divider and setting it. Added the register used, to DISPC context save and restore group ----------------------------------------------------------------------- In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as: DISPC_CORE_CLK >= max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...) Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the maximum horizontal downscaling done through MANAGERi Based on the usecase, core clk can be increased or decreased at runtime to save power. Such mechanism are not yet implemented. Hence, we set the core clock divisor to 1, to support maximum range of resolutions ------------------------------------------------------------------------ Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-03 15:28:00 +00:00
if (dss_has_feature(FEAT_CORE_CLK_DIV))
SR(DIVISOR);
OMAP: DSS2: DISPC: Fix context save/restore The current method of saving and restoring the context could cause a restore before saving, effectively "restoring" zero values to registers. Add ctx_valid field to indicate if the saved context is valid and can be restored. Also restructure the code to save the ctx_loss_count in save_context(), which makes more sense than the previous method of storing new ctx_loss_count in dispc_need_ctx_restore. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-01 12:54:06 +00:00
dispc.ctx_valid = true;
OMAPDSS: use DISPC register to detect context loss Instead of relying on the OMAP specific omap_pm_get_dev_context_loss_count() to detect register context loss, we can achieve the same in a much simpler way by just observing the DISPC registers. We always set DISPC's load mode to LOAD_FRAME_ONLY, which is not the reset value. Thus we can just observe the load mode to see if we have lost register context. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Archit Taneja <archit@ti.com>
2014-02-14 07:37:09 +00:00
DSSDBG("context saved\n");
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
static void dispc_restore_context(void)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: use DISPC register to detect context loss Instead of relying on the OMAP specific omap_pm_get_dev_context_loss_count() to detect register context loss, we can achieve the same in a much simpler way by just observing the DISPC registers. We always set DISPC's load mode to LOAD_FRAME_ONLY, which is not the reset value. Thus we can just observe the load mode to see if we have lost register context. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Archit Taneja <archit@ti.com>
2014-02-14 07:37:09 +00:00
int i, j;
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
DSSDBG("dispc_restore_context\n");
OMAP: DSS2: DISPC: Fix context save/restore The current method of saving and restoring the context could cause a restore before saving, effectively "restoring" zero values to registers. Add ctx_valid field to indicate if the saved context is valid and can be restored. Also restructure the code to save the ctx_loss_count in save_context(), which makes more sense than the previous method of storing new ctx_loss_count in dispc_need_ctx_restore. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-01 12:54:06 +00:00
if (!dispc.ctx_valid)
return;
OMAP: DSS2: clear spurious SYNC_LOST_DIGIT interrupts When DSS transitions from off mode to on VENC may generate a spurious SYNC_LOST_DIGIT error. Just ack it when restoring the context. Also restore IRQENABLE last to avoid triggering interrupts before the context is fully restored. Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-03-04 23:13:11 +00:00
/*RR(IRQENABLE);*/
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
/*RR(CONTROL);*/
RR(CONFIG);
RR(LINE_NUMBER);
OMAPDSS/OMAP_VOUT: Fix incorrect OMAP3-alpha compatibility setting On OMAP3, in order to enable alpha blending for LCD and TV managers, we needed to set LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits in DISPC_CONFIG. On OMAP4, alpha blending is always enabled by default, if the above bits are set, we switch to an OMAP3 compatibility mode where the zorder values in the pipeline attribute registers are ignored and a fixed priority is configured. Rename the manager_info member "alpha_enabled" to "partial_alpha_enabled" for more clarity. Introduce two dss_features FEAT_ALPHA_FIXED_ZORDER and FEAT_ALPHA_FREE_ZORDER which represent OMAP3-alpha compatibility mode and OMAP4 alpha mode respectively. Introduce an overlay cap for ZORDER. The DSS2 user is expected to check for the ZORDER cap, if an overlay doesn't have this cap, the user is expected to set the parameter partial_alpha_enabled. If the overlay has ZORDER cap, the DSS2 user can assume that alpha blending is already enabled. Don't support OMAP3 compatibility mode for now. Trying to read/write to alpha_blending_enabled sysfs attribute issues a warning for OMAP4 and does not set the LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits. Change alpha_enabled to partial_alpha_enabled in the omap_vout driver. Use overlay cap "OMAP_DSS_OVL_CAP_GLOBAL_ALPHA" to check if overlay supports alpha blending or not. Replace this with checks for VIDEO1 pipeline. Cc: linux-media@vger.kernel.org Cc: Lajos Molnar <molnar@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Acked-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-26 06:17:29 +00:00
if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
OMAP: DSS2: Add new FEAT definitions for features missing from OMAP2 OMAP2 doesn't have CPR, PRELOAD nor FIR_COEF_V registers. Add new feature definitions for those, and check the feature before accessing those registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 11:22:16 +00:00
RR(GLOBAL_ALPHA);
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
if (dss_has_feature(FEAT_MGR_LCD2))
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
RR(CONFIG2);
OMAPDSS: Add LCD3 overlay manager and Clock and IRQ support The support for LCD3 manager has been added into the manager module. LCD3 panel has registers as DISPC_CONTROL3 and DISPC_CONFIG3 just like those in LCD and LCD2 panels. These registers control the Display Controller (DISPC) module for LCD3 output. The three LCDs support Display Serial Interface (DSI), Remote Frame Buffer Interface (RFBI) and Parallel CMOS Output Interface (DPI). These LCDs can be connected through parallel output interface using DISPC and RFBI or DPI. For serial interface DSS uses DSI. The LCD3 panel, just like LCD and LCD2 panels, has a clock switch in DSS_CTRL register which has been enabled. The clock switch chooses between DSS_CLK and DPLL_DSI1_C_CLK1 as source for LCD3_CLK. New IRQs as DISPC_IRQ_VSYNC3, DISPC_IRQ_FRAMEDONE3, DISPC_IRQ_ACBIAS_COUNT_STAT3 and DISPC_IRQ_SYNC_LOST3 have been added specific to the new manager. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-29 05:13:13 +00:00
if (dss_has_feature(FEAT_MGR_LCD3))
RR(CONFIG3);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
RR(DEFAULT_COLOR(i));
RR(TRANS_COLOR(i));
RR(SIZE_MGR(i));
if (i == OMAP_DSS_CHANNEL_DIGIT)
continue;
RR(TIMING_H(i));
RR(TIMING_V(i));
RR(POL_FREQ(i));
RR(DIVISORo(i));
RR(DATA_CYCLE1(i));
RR(DATA_CYCLE2(i));
RR(DATA_CYCLE3(i));
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
OMAP: DSS2: Add new FEAT definitions for features missing from OMAP2 OMAP2 doesn't have CPR, PRELOAD nor FIR_COEF_V registers. Add new feature definitions for those, and check the feature before accessing those registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 11:22:16 +00:00
if (dss_has_feature(FEAT_CPR)) {
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
RR(CPR_COEF_R(i));
RR(CPR_COEF_G(i));
RR(CPR_COEF_B(i));
OMAP: DSS2: Add new FEAT definitions for features missing from OMAP2 OMAP2 doesn't have CPR, PRELOAD nor FIR_COEF_V registers. Add new feature definitions for those, and check the feature before accessing those registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 11:22:16 +00:00
}
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (i = 0; i < dss_feat_get_num_ovls(); i++) {
RR(OVL_BA0(i));
RR(OVL_BA1(i));
RR(OVL_POSITION(i));
RR(OVL_SIZE(i));
RR(OVL_ATTRIBUTES(i));
RR(OVL_FIFO_THRESHOLD(i));
RR(OVL_ROW_INC(i));
RR(OVL_PIXEL_INC(i));
if (dss_has_feature(FEAT_PRELOAD))
RR(OVL_PRELOAD(i));
if (i == OMAP_DSS_GFX) {
RR(OVL_WINDOW_SKIP(i));
RR(OVL_TABLE_BA(i));
continue;
}
RR(OVL_FIR(i));
RR(OVL_PICTURE_SIZE(i));
RR(OVL_ACCU0(i));
RR(OVL_ACCU1(i));
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (j = 0; j < 8; j++)
RR(OVL_FIR_COEF_H(i, j));
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (j = 0; j < 8; j++)
RR(OVL_FIR_COEF_HV(i, j));
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (j = 0; j < 5; j++)
RR(OVL_CONV_COEF(i, j));
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
if (dss_has_feature(FEAT_FIR_COEF_V)) {
for (j = 0; j < 8; j++)
RR(OVL_FIR_COEF_V(i, j));
}
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
RR(OVL_BA0_UV(i));
RR(OVL_BA1_UV(i));
RR(OVL_FIR2(i));
RR(OVL_ACCU2_0(i));
RR(OVL_ACCU2_1(i));
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (j = 0; j < 8; j++)
RR(OVL_FIR_COEF_H2(i, j));
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (j = 0; j < 8; j++)
RR(OVL_FIR_COEF_HV2(i, j));
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
OMAP: DSS2: DISPC: dispc_save_context() and dispc_restore_context() cleanup Iterate over manager and overlay id's to shorten dispc_save_context() and dispc_restore_context(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:02 +00:00
for (j = 0; j < 8; j++)
RR(OVL_FIR_COEF_V2(i, j));
}
if (dss_has_feature(FEAT_ATTR2))
RR(OVL_ATTRIBUTES2(i));
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP4: DSS2: Using dss_features to set independent core clock divider Using dss_features to select independent core clock divider and setting it. Added the register used, to DISPC context save and restore group ----------------------------------------------------------------------- In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as: DISPC_CORE_CLK >= max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...) Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the maximum horizontal downscaling done through MANAGERi Based on the usecase, core clk can be increased or decreased at runtime to save power. Such mechanism are not yet implemented. Hence, we set the core clock divisor to 1, to support maximum range of resolutions ------------------------------------------------------------------------ Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-03 15:28:00 +00:00
if (dss_has_feature(FEAT_CORE_CLK_DIV))
RR(DIVISOR);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
/* enable last, because LCD & DIGIT enable are here */
RR(CONTROL);
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
if (dss_has_feature(FEAT_MGR_LCD2))
RR(CONTROL2);
OMAPDSS: Add LCD3 overlay manager and Clock and IRQ support The support for LCD3 manager has been added into the manager module. LCD3 panel has registers as DISPC_CONTROL3 and DISPC_CONFIG3 just like those in LCD and LCD2 panels. These registers control the Display Controller (DISPC) module for LCD3 output. The three LCDs support Display Serial Interface (DSI), Remote Frame Buffer Interface (RFBI) and Parallel CMOS Output Interface (DPI). These LCDs can be connected through parallel output interface using DISPC and RFBI or DPI. For serial interface DSS uses DSI. The LCD3 panel, just like LCD and LCD2 panels, has a clock switch in DSS_CTRL register which has been enabled. The clock switch chooses between DSS_CLK and DPLL_DSI1_C_CLK1 as source for LCD3_CLK. New IRQs as DISPC_IRQ_VSYNC3, DISPC_IRQ_FRAMEDONE3, DISPC_IRQ_ACBIAS_COUNT_STAT3 and DISPC_IRQ_SYNC_LOST3 have been added specific to the new manager. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-29 05:13:13 +00:00
if (dss_has_feature(FEAT_MGR_LCD3))
RR(CONTROL3);
OMAP: DSS2: clear spurious SYNC_LOST_DIGIT interrupts When DSS transitions from off mode to on VENC may generate a spurious SYNC_LOST_DIGIT error. Just ack it when restoring the context. Also restore IRQENABLE last to avoid triggering interrupts before the context is fully restored. Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-03-04 23:13:11 +00:00
/* clear spurious SYNC_LOST_DIGIT interrupts */
OMAPDSS: DISPC: Add IRQ enable/status helpers DISPC irqs need to be handled from the compat layer and also in the future by the omapdrm. To make this possible, this patchs adds a set of helper functions, so that the irqs can be managed without direct register reads/writes. The following functions are added, and all the current direct reg reads/writes are changed to use these. u32 dispc_read_irqstatus(void); void dispc_clear_irqstatus(u32 mask); u32 dispc_read_irqenable(void); void dispc_write_irqenable(u32 mask); Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 12:13:14 +00:00
dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
OMAP: DSS2: clear spurious SYNC_LOST_DIGIT interrupts When DSS transitions from off mode to on VENC may generate a spurious SYNC_LOST_DIGIT error. Just ack it when restoring the context. Also restore IRQENABLE last to avoid triggering interrupts before the context is fully restored. Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-03-04 23:13:11 +00:00
/*
* enable last so IRQs won't trigger before
* the context is fully restored
*/
RR(IRQENABLE);
OMAP: DSS2: DISPC: Fix context save/restore The current method of saving and restoring the context could cause a restore before saving, effectively "restoring" zero values to registers. Add ctx_valid field to indicate if the saved context is valid and can be restored. Also restructure the code to save the ctx_loss_count in save_context(), which makes more sense than the previous method of storing new ctx_loss_count in dispc_need_ctx_restore. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-01 12:54:06 +00:00
DSSDBG("context restored\n");
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
#undef SR
#undef RR
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
int dispc_runtime_get(void)
{
int r;
DSSDBG("dispc_runtime_get\n");
r = pm_runtime_get_sync(&dispc.pdev->dev);
WARN_ON(r < 0);
return r < 0 ? r : 0;
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_runtime_get);
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
void dispc_runtime_put(void)
{
int r;
DSSDBG("dispc_runtime_put\n");
OMAPDSS: use sync versions of pm_runtime_put omapdss doesn't work properly on system suspend. The problem seems to be the fact that omapdss uses pm_runtime_put() functions when turning off the hardware, and when system suspend is in process only sync versions are allowed. Using non-sync versions normally and sync versions when suspending would need rather ugly hacks to convey the information of suspending/not-suspending to different functions. Optimally the driver wouldn't even need to care about this, and the PM layer would handle syncing when suspend is in process. This patch changes all omapdss's pm_runtime_put calls to pm_runtime_put_sync. This fixes the suspend problem, and probably the performance penalty of always using sync versions is negligible. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Kevin Hilman <khilman@ti.com>
2012-01-23 11:23:08 +00:00
r = pm_runtime_put_sync(&dispc.pdev->dev);
OMAPDSS: fix warnings if CONFIG_PM_RUNTIME=n If runtime PM is not enabled in the kernel config, pm_runtime_get_sync() will always return 1 and pm_runtime_put_sync() will always return -ENOSYS. pm_runtime_get_sync() returning 1 presents no problem to the driver, but -ENOSYS from pm_runtime_put_sync() causes the driver to print a warning. One option would be to ignore errors returned by pm_runtime_put_sync() totally, as they only say that the call was unable to put the hardware into suspend mode. However, I chose to ignore the returned -ENOSYS explicitly, and print a warning for other errors, as I think we should get notified if the HW failed to go to suspend properly. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Jassi Brar <jaswinder.singh@linaro.org> Cc: Grazvydas Ignotas <notasas@gmail.com>
2012-06-27 13:37:18 +00:00
WARN_ON(r < 0 && r != -ENOSYS);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_runtime_put);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Add dispc_mgr_get_vsync_irq() Add dispc_mgr_get_vsync_irq() which returns the irq number for vsync on the given channel. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-07 13:50:09 +00:00
u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
{
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
return mgr_desc[channel].vsync_irq;
OMAPDSS: DISPC: Add dispc_mgr_get_vsync_irq() Add dispc_mgr_get_vsync_irq() which returns the irq number for vsync on the given channel. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-07 13:50:09 +00:00
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
OMAPDSS: DISPC: Add dispc_mgr_get_vsync_irq() Add dispc_mgr_get_vsync_irq() which returns the irq number for vsync on the given channel. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-07 13:50:09 +00:00
OMAPDSS: DISPC: add dispc_mgr_get_framedone_irq Add dispc_mgr_get_framedone_irq() which returns the irq number for FRAMEDONE for the given channel. Note that the function returns always 0 for DIGIT channel, even if OMAP4 does have FRAMEDONE_TV interrupt. The reason for this is that this function is currently used only to track manual updates, and thus FRAMEDONE_TV is not needed. If there's need in the future to also get the FRAMEDONE_TV this needs revisiting. However, as FRAMEDONE_TV doesn't exist on OMAP2/3, the use of this function for that purpose needs some extra code to handle the OMAP2/3 case. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-18 13:39:52 +00:00
u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
{
OMAPDSS: DISPC: add no_framedone_tv feat OMAP2/3 do not have FRAMEDONETV irq, but later omaps do. We currently always return 0 from dispc_mgr_get_framedone_irq() for TV output to be compatible with OMAP2/3. This patch implements "no_framedone_tv" dispc-feature that is used in dispc_mgr_get_framedone_irq to return either 0 for OMAP2/3, or the correct IRQ number for FRAMEDONETV on OMAP4+. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-08 08:01:33 +00:00
if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
return 0;
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
return mgr_desc[channel].framedone_irq;
OMAPDSS: DISPC: add dispc_mgr_get_framedone_irq Add dispc_mgr_get_framedone_irq() which returns the irq number for FRAMEDONE for the given channel. Note that the function returns always 0 for DIGIT channel, even if OMAP4 does have FRAMEDONE_TV interrupt. The reason for this is that this function is currently used only to track manual updates, and thus FRAMEDONE_TV is not needed. If there's need in the future to also get the FRAMEDONE_TV this needs revisiting. However, as FRAMEDONE_TV doesn't exist on OMAP2/3, the use of this function for that purpose needs some extra code to handle the OMAP2/3 case. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-18 13:39:52 +00:00
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
OMAPDSS: DISPC: add dispc_mgr_get_framedone_irq Add dispc_mgr_get_framedone_irq() which returns the irq number for FRAMEDONE for the given channel. Note that the function returns always 0 for DIGIT channel, even if OMAP4 does have FRAMEDONE_TV interrupt. The reason for this is that this function is currently used only to track manual updates, and thus FRAMEDONE_TV is not needed. If there's need in the future to also get the FRAMEDONE_TV this needs revisiting. However, as FRAMEDONE_TV doesn't exist on OMAP2/3, the use of this function for that purpose needs some extra code to handle the OMAP2/3 case. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-18 13:39:52 +00:00
OMAPDSS: DISPC: add dispc_mgr_get_sync_lost_irq() Add function that returns the sync lost irq mask for the given channel. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-17 07:38:52 +00:00
u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
{
return mgr_desc[channel].sync_lost_irq;
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
OMAPDSS: DISPC: add dispc_mgr_get_sync_lost_irq() Add function that returns the sync lost irq mask for the given channel. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-17 07:38:52 +00:00
OMAPDSS: DISPC: Add manager like functions for writeback Add functions to enable writeback, and set/check state of GO bit. These bits are identical in behaviour with the corresponding overlay manager bits. Configure them in a similar way to mgr_enable() and mgr_go_* functions. Add a helper to get the FRAMEDONE irq corresponding to writeback. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-22 07:09:33 +00:00
u32 dispc_wb_get_framedone_irq(void)
{
return DISPC_IRQ_FRAMEDONEWB;
}
OMAP: DSS2: DISPC: rename manager related funcs Rename dispc's manager related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_mgr_* - Remove "channel" from the name, e.g. dispc_enable_channel -> dispc_mgr_enable The idea is to group manager related functions so that it can be deduced from the function name that it writes to manager spesific registers. All dispc_mgr_* functions have enum omap_channel as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:45:15 +00:00
bool dispc_mgr_go_busy(enum omap_channel channel)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_mgr_go_busy);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: DISPC: rename manager related funcs Rename dispc's manager related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_mgr_* - Remove "channel" from the name, e.g. dispc_enable_channel -> dispc_mgr_enable The idea is to group manager related functions so that it can be deduced from the function name that it writes to manager spesific registers. All dispc_mgr_* functions have enum omap_channel as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:45:15 +00:00
void dispc_mgr_go(enum omap_channel channel)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: DISPC: use WARN_ON() in dispc_mgr_go dispc_mgr_go() should never be called with manager output disabled or if the GO bit is already set. Change the current silent returns to WARN_ONs. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:06:07 +00:00
WARN_ON(dispc_mgr_is_enabled(channel) == false);
WARN_ON(dispc_mgr_go_busy(channel));
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
DSSDBG("GO %s\n", mgr_desc[channel].name);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_mgr_go);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Add manager like functions for writeback Add functions to enable writeback, and set/check state of GO bit. These bits are identical in behaviour with the corresponding overlay manager bits. Configure them in a similar way to mgr_enable() and mgr_go_* functions. Add a helper to get the FRAMEDONE irq corresponding to writeback. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-22 07:09:33 +00:00
bool dispc_wb_go_busy(void)
{
return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
}
void dispc_wb_go(void)
{
enum omap_plane plane = OMAP_DSS_WB;
bool enable, go;
enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
if (!enable)
return;
go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
if (go) {
DSSERR("GO bit not down for WB\n");
return;
}
REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
{
BUG_ON(plane == OMAP_DSS_GFX);
dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
u32 value)
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
{
BUG_ON(plane == OMAP_DSS_GFX);
dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
{
BUG_ON(plane == OMAP_DSS_GFX);
dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
}
OMAPDSS: DISPC: Update Fir Coefficients The FIR coefficients present in kernel are being updated to new coefficients consisting of 24 coefficient tables, with 12 each for 3 tap and 5 tap scenario, which are chosen on the basis of DISPC up/downsampling filters M value. M is the inverse of low pass cut off frequency of the sampling filter. For vertical scaling 3 tap or 5 tap tables are used based on the clock rate and width of the line buffer whereas in OMAP2 3 tap is always used. For horizontal scaling however 5 tap tables are always used. New coefficients and the corresponding logic have been tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical scaling worked fine except for some 3 tap vs 5 tap issue during vertical upscaling and clock failing issues which is acknowledged in the next patch. Vertical upscaling was found to perform better under 5 taps. The 24 coefficient tables have been moved to another file dispc_coefs.c for proper maintainance. This code is written based on code written by Lajos Molnar <lajos@ti.com> in Android Kernel for scaling. Lajos Molnar <lajos@ti.com> had fine tuned the FIR coefficient selection process and reduced outliness and blockiness around images when upscaling more than 2 times. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-12-19 08:33:44 +00:00
static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
int fir_vinc, int five_taps,
enum omap_color_component color_comp)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: DISPC: Update Fir Coefficients The FIR coefficients present in kernel are being updated to new coefficients consisting of 24 coefficient tables, with 12 each for 3 tap and 5 tap scenario, which are chosen on the basis of DISPC up/downsampling filters M value. M is the inverse of low pass cut off frequency of the sampling filter. For vertical scaling 3 tap or 5 tap tables are used based on the clock rate and width of the line buffer whereas in OMAP2 3 tap is always used. For horizontal scaling however 5 tap tables are always used. New coefficients and the corresponding logic have been tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical scaling worked fine except for some 3 tap vs 5 tap issue during vertical upscaling and clock failing issues which is acknowledged in the next patch. Vertical upscaling was found to perform better under 5 taps. The 24 coefficient tables have been moved to another file dispc_coefs.c for proper maintainance. This code is written based on code written by Lajos Molnar <lajos@ti.com> in Android Kernel for scaling. Lajos Molnar <lajos@ti.com> had fine tuned the FIR coefficient selection process and reduced outliness and blockiness around images when upscaling more than 2 times. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-12-19 08:33:44 +00:00
const struct dispc_coef *h_coef, *v_coef;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
int i;
OMAPDSS: DISPC: Update Fir Coefficients The FIR coefficients present in kernel are being updated to new coefficients consisting of 24 coefficient tables, with 12 each for 3 tap and 5 tap scenario, which are chosen on the basis of DISPC up/downsampling filters M value. M is the inverse of low pass cut off frequency of the sampling filter. For vertical scaling 3 tap or 5 tap tables are used based on the clock rate and width of the line buffer whereas in OMAP2 3 tap is always used. For horizontal scaling however 5 tap tables are always used. New coefficients and the corresponding logic have been tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical scaling worked fine except for some 3 tap vs 5 tap issue during vertical upscaling and clock failing issues which is acknowledged in the next patch. Vertical upscaling was found to perform better under 5 taps. The 24 coefficient tables have been moved to another file dispc_coefs.c for proper maintainance. This code is written based on code written by Lajos Molnar <lajos@ti.com> in Android Kernel for scaling. Lajos Molnar <lajos@ti.com> had fine tuned the FIR coefficient selection process and reduced outliness and blockiness around images when upscaling more than 2 times. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-12-19 08:33:44 +00:00
h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
for (i = 0; i < 8; i++) {
u32 h, hv;
OMAPDSS: DISPC: Update Fir Coefficients The FIR coefficients present in kernel are being updated to new coefficients consisting of 24 coefficient tables, with 12 each for 3 tap and 5 tap scenario, which are chosen on the basis of DISPC up/downsampling filters M value. M is the inverse of low pass cut off frequency of the sampling filter. For vertical scaling 3 tap or 5 tap tables are used based on the clock rate and width of the line buffer whereas in OMAP2 3 tap is always used. For horizontal scaling however 5 tap tables are always used. New coefficients and the corresponding logic have been tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical scaling worked fine except for some 3 tap vs 5 tap issue during vertical upscaling and clock failing issues which is acknowledged in the next patch. Vertical upscaling was found to perform better under 5 taps. The 24 coefficient tables have been moved to another file dispc_coefs.c for proper maintainance. This code is written based on code written by Lajos Molnar <lajos@ti.com> in Android Kernel for scaling. Lajos Molnar <lajos@ti.com> had fine tuned the FIR coefficient selection process and reduced outliness and blockiness around images when upscaling more than 2 times. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-12-19 08:33:44 +00:00
h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
| FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
| FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
| FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
| FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
| FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
| FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
dispc_ovl_write_firh_reg(plane, i, h);
dispc_ovl_write_firhv_reg(plane, i, hv);
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
} else {
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
dispc_ovl_write_firh2_reg(plane, i, h);
dispc_ovl_write_firhv2_reg(plane, i, hv);
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: make filter coefficient tables human readable Reorganize scaler FIR filter data as FIR value tables from raw register values. This makes them easier to understand and simplifies register programming code. No functional changes. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-08-24 13:18:43 +00:00
if (five_taps) {
for (i = 0; i < 8; i++) {
u32 v;
OMAPDSS: DISPC: Update Fir Coefficients The FIR coefficients present in kernel are being updated to new coefficients consisting of 24 coefficient tables, with 12 each for 3 tap and 5 tap scenario, which are chosen on the basis of DISPC up/downsampling filters M value. M is the inverse of low pass cut off frequency of the sampling filter. For vertical scaling 3 tap or 5 tap tables are used based on the clock rate and width of the line buffer whereas in OMAP2 3 tap is always used. For horizontal scaling however 5 tap tables are always used. New coefficients and the corresponding logic have been tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical scaling worked fine except for some 3 tap vs 5 tap issue during vertical upscaling and clock failing issues which is acknowledged in the next patch. Vertical upscaling was found to perform better under 5 taps. The 24 coefficient tables have been moved to another file dispc_coefs.c for proper maintainance. This code is written based on code written by Lajos Molnar <lajos@ti.com> in Android Kernel for scaling. Lajos Molnar <lajos@ti.com> had fine tuned the FIR coefficient selection process and reduced outliness and blockiness around images when upscaling more than 2 times. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-12-19 08:33:44 +00:00
v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
| FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
dispc_ovl_write_firv_reg(plane, i, v);
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
else
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
dispc_ovl_write_firv2_reg(plane, i, v);
OMAP: DSS2: make filter coefficient tables human readable Reorganize scaler FIR filter data as FIR value tables from raw register values. This makes them easier to understand and simplifies register programming code. No functional changes. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-08-24 13:18:43 +00:00
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
}
OMAPDSS: DISPC: Configure color conversion coefficients for writeback Writeback pipeline receives RGB data from one of the overlays or one of the overlay managers. If the target color mode is YUV422 or NV12, we need to convert the RGB pixels to YUV. The scaler in WB then converts it to the target color mode. Hence, the color conversion coefficients that need to be programmed are the ones which convert a RGB24 pixel to YUV444. Program these coefficients for writeback pipeline. Rearrange the code a bit to configure different coefficients for overlays and writeback. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-11 06:34:47 +00:00
static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
const struct color_conv_coef *ct)
{
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
OMAPDSS: DISPC: Configure color conversion coefficients for writeback Writeback pipeline receives RGB data from one of the overlays or one of the overlay managers. If the target color mode is YUV422 or NV12, we need to convert the RGB pixels to YUV. The scaler in WB then converts it to the target color mode. Hence, the color conversion coefficients that need to be programmed are the ones which convert a RGB24 pixel to YUV444. Program these coefficients for writeback pipeline. Rearrange the code a bit to configure different coefficients for overlays and writeback. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-11 06:34:47 +00:00
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Configure color conversion coefficients for writeback Writeback pipeline receives RGB data from one of the overlays or one of the overlay managers. If the target color mode is YUV422 or NV12, we need to convert the RGB pixels to YUV. The scaler in WB then converts it to the target color mode. Hence, the color conversion coefficients that need to be programmed are the ones which convert a RGB24 pixel to YUV444. Program these coefficients for writeback pipeline. Rearrange the code a bit to configure different coefficients for overlays and writeback. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-11 06:34:47 +00:00
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
#undef CVAL
}
OMAPDSS: DISPC: Configure color conversion coefficients for writeback Writeback pipeline receives RGB data from one of the overlays or one of the overlay managers. If the target color mode is YUV422 or NV12, we need to convert the RGB pixels to YUV. The scaler in WB then converts it to the target color mode. Hence, the color conversion coefficients that need to be programmed are the ones which convert a RGB24 pixel to YUV444. Program these coefficients for writeback pipeline. Rearrange the code a bit to configure different coefficients for overlays and writeback. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-11 06:34:47 +00:00
static void dispc_setup_color_conv_coef(void)
{
int i;
int num_ovl = dss_feat_get_num_ovls();
int num_wb = dss_feat_get_num_wbs();
const struct color_conv_coef ctbl_bt601_5_ovl = {
298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
};
const struct color_conv_coef ctbl_bt601_5_wb = {
66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
};
for (i = 1; i < num_ovl; i++)
dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
for (; i < num_wb; i++)
dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
{
dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
{
dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
}
OMAPDSS: OVERLAY: Add position and replication as overlay caps Add position and replication as overlay caps, and pass overlay caps as an argument to the corresponding functions. Adding position and replication to overlay caps seems a bit unnecessary, but it allows us to use the corresponding functions for writeback too. These caps will be set for all overlays, but not for writeback. This is done so writeback can reuse dispc_ovl_setup() to the maximum. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-22 07:00:17 +00:00
static void dispc_ovl_set_pos(enum omap_plane plane,
enum omap_overlay_caps caps, int x, int y)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: OVERLAY: Add position and replication as overlay caps Add position and replication as overlay caps, and pass overlay caps as an argument to the corresponding functions. Adding position and replication to overlay caps seems a bit unnecessary, but it allows us to use the corresponding functions for writeback too. These caps will be set for all overlays, but not for writeback. This is done so writeback can reuse dispc_ovl_setup() to the maximum. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-22 07:00:17 +00:00
u32 val;
if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
return;
val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_POSITION(plane), val);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: DISPC: Simplify function names for setting pipeline input and output sizes The DISPC pipeline register names in the TRM for setting the buffer size and the output size are a bit misleading, for example, there are different register names for setting the buffer size for VID and GFX pipes. Things get more confusing when considering writeback pipeline. Rename the functions so that they tell whether they are configuring the input to the scalar or the output. These will be extended later to support writeback registers. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-21 09:21:49 +00:00
static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
int height)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
OMAPDSS: DISPC: Configure input and output sizes for writeback Writeback uses the WB_PICTURE_SIZE register to define the size of the content written to memory, this is the output of the scaler. It uses the WB_SIZE register to define the size of the content coming from the overlay/manager to which it is connected, this is the input to the scaler. This naming is different as compared to overlays. Add checks for writeback in dispc_ovl_set_input_size() and dispc_ovl_set_output_size() to write to the correct registers. Signed-off-by: Archit Taneja <archit@ti.com>
2012-07-28 17:29:03 +00:00
if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_SIZE(plane), val);
else
dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: DISPC: Simplify function names for setting pipeline input and output sizes The DISPC pipeline register names in the TRM for setting the buffer size and the output size are a bit misleading, for example, there are different register names for setting the buffer size for VID and GFX pipes. Things get more confusing when considering writeback pipeline. Rename the functions so that they tell whether they are configuring the input to the scalar or the output. These will be extended later to support writeback registers. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-21 09:21:49 +00:00
static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
int height)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
u32 val;
BUG_ON(plane == OMAP_DSS_GFX);
val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
OMAPDSS: DISPC: Configure input and output sizes for writeback Writeback uses the WB_PICTURE_SIZE register to define the size of the content written to memory, this is the output of the scaler. It uses the WB_SIZE register to define the size of the content coming from the overlay/manager to which it is connected, this is the input to the scaler. This naming is different as compared to overlays. Add checks for writeback in dispc_ovl_set_input_size() and dispc_ovl_set_output_size() to write to the correct registers. Signed-off-by: Archit Taneja <archit@ti.com>
2012-07-28 17:29:03 +00:00
if (plane == OMAP_DSS_WB)
dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
else
dispc_write_reg(DISPC_OVL_SIZE(plane), val);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: DISPC: Pass overlay caps as a parameter to dispc plane functions Currently, the functions below take the omap_plane parameter and derive the overlay caps within them. Pass the overlay caps as a parameter to the function to allow these to be used by writeback too. - dispc_ovl_set_zorder() - dispc_ovl_set_pre_mult_alpha() - dispc_ovl_setup_global_alpha() - dispc_ovl_calc_scaling() - dispc_ovl_setup() These functions will be used for writeback later, and the caps will help in deciding if they are to be used for writeback or not. This allows reuse of overlay caps for writeback. Using omap_overlay_caps for writeback seems a bit incorrect, but caps is something already in use by users of OMAPDSS(omapfb/omap_vout), so we use overlay caps for overlay like features of writeback too. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:25:27 +00:00
static void dispc_ovl_set_zorder(enum omap_plane plane,
enum omap_overlay_caps caps, u8 zorder)
OMAPDSS: DISPC: zorder support for DSS overlays Add zorder support on OMAP4, this feature allows deciding the visibility order of the overlays based on the zorder value provided as an overlay info parameter or a sysfs attribute of the overlay object. Use the overlay cap OMAP_DSS_OVL_CAP_ZORDER to determine whether zorder is supported for the overlay or not. Use dss feature FEAT_ALPHA_FREE_ZORDER if the caps are not available. Ensure that all overlays that are enabled and connected to the same manager have different zorders. Swapping zorders of 2 enabled overlays currently requires disabling one of the overlays. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 05:59:17 +00:00
{
OMAPDSS: DISPC: Pass overlay caps as a parameter to dispc plane functions Currently, the functions below take the omap_plane parameter and derive the overlay caps within them. Pass the overlay caps as a parameter to the function to allow these to be used by writeback too. - dispc_ovl_set_zorder() - dispc_ovl_set_pre_mult_alpha() - dispc_ovl_setup_global_alpha() - dispc_ovl_calc_scaling() - dispc_ovl_setup() These functions will be used for writeback later, and the caps will help in deciding if they are to be used for writeback or not. This allows reuse of overlay caps for writeback. Using omap_overlay_caps for writeback seems a bit incorrect, but caps is something already in use by users of OMAPDSS(omapfb/omap_vout), so we use overlay caps for overlay like features of writeback too. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:25:27 +00:00
if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
OMAPDSS: DISPC: zorder support for DSS overlays Add zorder support on OMAP4, this feature allows deciding the visibility order of the overlays based on the zorder value provided as an overlay info parameter or a sysfs attribute of the overlay object. Use the overlay cap OMAP_DSS_OVL_CAP_ZORDER to determine whether zorder is supported for the overlay or not. Use dss feature FEAT_ALPHA_FREE_ZORDER if the caps are not available. Ensure that all overlays that are enabled and connected to the same manager have different zorders. Swapping zorders of 2 enabled overlays currently requires disabling one of the overlays. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 05:59:17 +00:00
return;
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
}
static void dispc_ovl_enable_zorder_planes(void)
{
int i;
if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
return;
for (i = 0; i < dss_feat_get_num_ovls(); i++)
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
}
OMAPDSS: DISPC: Pass overlay caps as a parameter to dispc plane functions Currently, the functions below take the omap_plane parameter and derive the overlay caps within them. Pass the overlay caps as a parameter to the function to allow these to be used by writeback too. - dispc_ovl_set_zorder() - dispc_ovl_set_pre_mult_alpha() - dispc_ovl_setup_global_alpha() - dispc_ovl_calc_scaling() - dispc_ovl_setup() These functions will be used for writeback later, and the caps will help in deciding if they are to be used for writeback or not. This allows reuse of overlay caps for writeback. Using omap_overlay_caps for writeback seems a bit incorrect, but caps is something already in use by users of OMAPDSS(omapfb/omap_vout), so we use overlay caps for overlay like features of writeback too. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:25:27 +00:00
static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
enum omap_overlay_caps caps, bool enable)
OMAP3630: DSS2: Enable Pre-Multiplied Alpha Support Enable dss to process color formats with pre-mulitplied alpha. With this we can have alpha values defined for each pixel and hence can have different blending values for each pixel. sysfs entry has been created for this and pre-multiplied alpha support is turned off by default. Signed-off-by: Sudeep Basavaraj <sudeep.basavaraj@ti.com> Signed-off-by: Rajkumar N <rajkumar.nagarajan@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-11-04 11:28:42 +00:00
{
OMAPDSS: DISPC: Pass overlay caps as a parameter to dispc plane functions Currently, the functions below take the omap_plane parameter and derive the overlay caps within them. Pass the overlay caps as a parameter to the function to allow these to be used by writeback too. - dispc_ovl_set_zorder() - dispc_ovl_set_pre_mult_alpha() - dispc_ovl_setup_global_alpha() - dispc_ovl_calc_scaling() - dispc_ovl_setup() These functions will be used for writeback later, and the caps will help in deciding if they are to be used for writeback or not. This allows reuse of overlay caps for writeback. Using omap_overlay_caps for writeback seems a bit incorrect, but caps is something already in use by users of OMAPDSS(omapfb/omap_vout), so we use overlay caps for overlay like features of writeback too. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:25:27 +00:00
if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
OMAP3630: DSS2: Enable Pre-Multiplied Alpha Support Enable dss to process color formats with pre-mulitplied alpha. With this we can have alpha values defined for each pixel and hence can have different blending values for each pixel. sysfs entry has been created for this and pre-multiplied alpha support is turned off by default. Signed-off-by: Sudeep Basavaraj <sudeep.basavaraj@ti.com> Signed-off-by: Rajkumar N <rajkumar.nagarajan@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-11-04 11:28:42 +00:00
return;
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
OMAP3630: DSS2: Enable Pre-Multiplied Alpha Support Enable dss to process color formats with pre-mulitplied alpha. With this we can have alpha values defined for each pixel and hence can have different blending values for each pixel. sysfs entry has been created for this and pre-multiplied alpha support is turned off by default. Signed-off-by: Sudeep Basavaraj <sudeep.basavaraj@ti.com> Signed-off-by: Rajkumar N <rajkumar.nagarajan@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-11-04 11:28:42 +00:00
}
OMAPDSS: DISPC: Pass overlay caps as a parameter to dispc plane functions Currently, the functions below take the omap_plane parameter and derive the overlay caps within them. Pass the overlay caps as a parameter to the function to allow these to be used by writeback too. - dispc_ovl_set_zorder() - dispc_ovl_set_pre_mult_alpha() - dispc_ovl_setup_global_alpha() - dispc_ovl_calc_scaling() - dispc_ovl_setup() These functions will be used for writeback later, and the caps will help in deciding if they are to be used for writeback or not. This allows reuse of overlay caps for writeback. Using omap_overlay_caps for writeback seems a bit incorrect, but caps is something already in use by users of OMAPDSS(omapfb/omap_vout), so we use overlay caps for overlay like features of writeback too. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:25:27 +00:00
static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
enum omap_overlay_caps caps, u8 global_alpha)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: DISPC: VIDEO3 pipeline support Add support for VIDEO3 pipeline on OMAP4: - Add VIDEO3 pipeline information in dss_features and omapdss.h - Add VIDEO3 pipeline register coefficients in dispc.h - Create a new overlay structure corresponding to VIDEO3. - Make changes in dispc.c for VIDEO3 Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-13 12:50:33 +00:00
static const unsigned shifts[] = { 0, 8, 16, 24, };
OMAP: DSS2: DISPC: use lookup tables for bit shifts Use lookup tables instead of switch/if in some DISPC functions to make the code cleaner. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Archit Taneja <archit@ti.com>
2011-08-15 08:51:50 +00:00
int shift;
OMAPDSS: DISPC: Pass overlay caps as a parameter to dispc plane functions Currently, the functions below take the omap_plane parameter and derive the overlay caps within them. Pass the overlay caps as a parameter to the function to allow these to be used by writeback too. - dispc_ovl_set_zorder() - dispc_ovl_set_pre_mult_alpha() - dispc_ovl_setup_global_alpha() - dispc_ovl_calc_scaling() - dispc_ovl_setup() These functions will be used for writeback later, and the caps will help in deciding if they are to be used for writeback or not. This allows reuse of overlay caps for writeback. Using omap_overlay_caps for writeback seems a bit incorrect, but caps is something already in use by users of OMAPDSS(omapfb/omap_vout), so we use overlay caps for overlay like features of writeback too. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:25:27 +00:00
if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
OMAP3630: DSS2: Enable Pre-Multiplied Alpha Support Enable dss to process color formats with pre-mulitplied alpha. With this we can have alpha values defined for each pixel and hence can have different blending values for each pixel. sysfs entry has been created for this and pre-multiplied alpha support is turned off by default. Signed-off-by: Sudeep Basavaraj <sudeep.basavaraj@ti.com> Signed-off-by: Rajkumar N <rajkumar.nagarajan@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-11-04 11:28:42 +00:00
return;
OMAP: DSS2: Use dss_features framework on DSS2 code Calls init functions of dss_features during dss_probe, and the following features are made omapxxxx independent: - number of managers, overlays - supported color modes for each overlay - supported displays for each manager - global aplha, and restriction of global alpha for video1 pipeline - The register field ranges : FIRHINC, FIRVINC, FIFOHIGHTHRESHOLD FIFOLOWTHRESHOLD and FIFOSIZE Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-09-15 13:50:00 +00:00
OMAP: DSS2: DISPC: use lookup tables for bit shifts Use lookup tables instead of switch/if in some DISPC functions to make the code cleaner. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Archit Taneja <archit@ti.com>
2011-08-15 08:51:50 +00:00
shift = shifts[plane];
REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_color_mode(enum omap_plane plane,
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
enum omap_color_mode color_mode)
{
u32 m = 0;
OMAP: DSS2: Add new color formats for OMAP4 Add new color formats supported by OMAP4: NV12, RGBA16, RGBX16, ARGB16_1555, XRGB16_1555. NV12 color format is defined here, its support in DSS will be added separately. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:50 +00:00
if (plane != OMAP_DSS_GFX) {
switch (color_mode) {
case OMAP_DSS_COLOR_NV12:
m = 0x0; break;
OMAPDSS: DISPC: Fix OMAP4 supported color formats Add missing but supported color formats for GFX pipeline in dss features: RGBX16-4444, RGBA16-4444 and XRGB16-1555. In dispc_ovl_set_color_mode(): - Remove unsupported modes on GFX pipeline: YUV2 and UYVY. Replace these by missing modes supported by GFX pipelines: RGBX16-4444 and RGBA16-4444. - Fix swapped modes on VID pipelines: RGBX16-4444 and XRGB16-4444. Signed-off-by: Lajos Molnar <lajos@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-02-21 14:06:30 +00:00
case OMAP_DSS_COLOR_RGBX16:
OMAP: DSS2: Add new color formats for OMAP4 Add new color formats supported by OMAP4: NV12, RGBA16, RGBX16, ARGB16_1555, XRGB16_1555. NV12 color format is defined here, its support in DSS will be added separately. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:50 +00:00
m = 0x1; break;
case OMAP_DSS_COLOR_RGBA16:
m = 0x2; break;
OMAPDSS: DISPC: Fix OMAP4 supported color formats Add missing but supported color formats for GFX pipeline in dss features: RGBX16-4444, RGBA16-4444 and XRGB16-1555. In dispc_ovl_set_color_mode(): - Remove unsupported modes on GFX pipeline: YUV2 and UYVY. Replace these by missing modes supported by GFX pipelines: RGBX16-4444 and RGBA16-4444. - Fix swapped modes on VID pipelines: RGBX16-4444 and XRGB16-4444. Signed-off-by: Lajos Molnar <lajos@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-02-21 14:06:30 +00:00
case OMAP_DSS_COLOR_RGB12U:
OMAP: DSS2: Add new color formats for OMAP4 Add new color formats supported by OMAP4: NV12, RGBA16, RGBX16, ARGB16_1555, XRGB16_1555. NV12 color format is defined here, its support in DSS will be added separately. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:50 +00:00
m = 0x4; break;
case OMAP_DSS_COLOR_ARGB16:
m = 0x5; break;
case OMAP_DSS_COLOR_RGB16:
m = 0x6; break;
case OMAP_DSS_COLOR_ARGB16_1555:
m = 0x7; break;
case OMAP_DSS_COLOR_RGB24U:
m = 0x8; break;
case OMAP_DSS_COLOR_RGB24P:
m = 0x9; break;
case OMAP_DSS_COLOR_YUV2:
m = 0xa; break;
case OMAP_DSS_COLOR_UYVY:
m = 0xb; break;
case OMAP_DSS_COLOR_ARGB32:
m = 0xc; break;
case OMAP_DSS_COLOR_RGBA32:
m = 0xd; break;
case OMAP_DSS_COLOR_RGBX32:
m = 0xe; break;
case OMAP_DSS_COLOR_XRGB16_1555:
m = 0xf; break;
default:
OMAPDSS: remove compiler warnings when CONFIG_BUG=n If CONFIG_BUG is not enabled, BUG() does not stop the execution. Many places in code expect the execution to stop, and this causes compiler warnings about uninitialized variables and returning from a non-void function without a return value. This patch fixes the warnings by initializing the variables and returning properly after BUG() lines. However, the behaviour is still undefined after the BUG, but this is the choice the user makes when using CONFIG_BUG=n. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 08:47:02 +00:00
BUG(); return;
OMAP: DSS2: Add new color formats for OMAP4 Add new color formats supported by OMAP4: NV12, RGBA16, RGBX16, ARGB16_1555, XRGB16_1555. NV12 color format is defined here, its support in DSS will be added separately. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:50 +00:00
}
} else {
switch (color_mode) {
case OMAP_DSS_COLOR_CLUT1:
m = 0x0; break;
case OMAP_DSS_COLOR_CLUT2:
m = 0x1; break;
case OMAP_DSS_COLOR_CLUT4:
m = 0x2; break;
case OMAP_DSS_COLOR_CLUT8:
m = 0x3; break;
case OMAP_DSS_COLOR_RGB12U:
m = 0x4; break;
case OMAP_DSS_COLOR_ARGB16:
m = 0x5; break;
case OMAP_DSS_COLOR_RGB16:
m = 0x6; break;
case OMAP_DSS_COLOR_ARGB16_1555:
m = 0x7; break;
case OMAP_DSS_COLOR_RGB24U:
m = 0x8; break;
case OMAP_DSS_COLOR_RGB24P:
m = 0x9; break;
OMAPDSS: DISPC: Fix OMAP4 supported color formats Add missing but supported color formats for GFX pipeline in dss features: RGBX16-4444, RGBA16-4444 and XRGB16-1555. In dispc_ovl_set_color_mode(): - Remove unsupported modes on GFX pipeline: YUV2 and UYVY. Replace these by missing modes supported by GFX pipelines: RGBX16-4444 and RGBA16-4444. - Fix swapped modes on VID pipelines: RGBX16-4444 and XRGB16-4444. Signed-off-by: Lajos Molnar <lajos@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-02-21 14:06:30 +00:00
case OMAP_DSS_COLOR_RGBX16:
OMAP: DSS2: Add new color formats for OMAP4 Add new color formats supported by OMAP4: NV12, RGBA16, RGBX16, ARGB16_1555, XRGB16_1555. NV12 color format is defined here, its support in DSS will be added separately. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:50 +00:00
m = 0xa; break;
OMAPDSS: DISPC: Fix OMAP4 supported color formats Add missing but supported color formats for GFX pipeline in dss features: RGBX16-4444, RGBA16-4444 and XRGB16-1555. In dispc_ovl_set_color_mode(): - Remove unsupported modes on GFX pipeline: YUV2 and UYVY. Replace these by missing modes supported by GFX pipelines: RGBX16-4444 and RGBA16-4444. - Fix swapped modes on VID pipelines: RGBX16-4444 and XRGB16-4444. Signed-off-by: Lajos Molnar <lajos@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-02-21 14:06:30 +00:00
case OMAP_DSS_COLOR_RGBA16:
OMAP: DSS2: Add new color formats for OMAP4 Add new color formats supported by OMAP4: NV12, RGBA16, RGBX16, ARGB16_1555, XRGB16_1555. NV12 color format is defined here, its support in DSS will be added separately. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:50 +00:00
m = 0xb; break;
case OMAP_DSS_COLOR_ARGB32:
m = 0xc; break;
case OMAP_DSS_COLOR_RGBA32:
m = 0xd; break;
case OMAP_DSS_COLOR_RGBX32:
m = 0xe; break;
case OMAP_DSS_COLOR_XRGB16_1555:
m = 0xf; break;
default:
OMAPDSS: remove compiler warnings when CONFIG_BUG=n If CONFIG_BUG is not enabled, BUG() does not stop the execution. Many places in code expect the execution to stop, and this causes compiler warnings about uninitialized variables and returning from a non-void function without a return value. This patch fixes the warnings by initializing the variables and returning properly after BUG() lines. However, the behaviour is still undefined after the BUG, but this is the choice the user makes when using CONFIG_BUG=n. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 08:47:02 +00:00
BUG(); return;
OMAP: DSS2: Add new color formats for OMAP4 Add new color formats supported by OMAP4: NV12, RGBA16, RGBX16, ARGB16_1555, XRGB16_1555. NV12 color format is defined here, its support in DSS will be added separately. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:50 +00:00
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: DISPC: Support rotation through TILER TILER is a block in OMAP4's DMM which lets DSS fetch frames in a rotated manner. Physical memory can be mapped to a portion of OMAP's system address space called TILER address space. The TILER address space is split into 8 views. Each view represents a rotated or mirrored form of the mapped physical memory. When a DISPC overlay's base address is programmed to one of these views, the TILER fetches the pixels according to the orientation of the view. A view is further split into 4 containers, each container holds elements of a particular size. Rotation can be achieved at the granularity of elements in the container. For more information on TILER, refer to the Memory Subsytem section in OMAP4 TRM. Rotation type TILER has been added which is used to exploit the capabilities of these 8 views for performing various rotations. When fetching from addresses mapped to TILER space, the DISPC DMA can fetch pixels in either 1D or 2D bursts. The fetch depends on which TILER container we are accessing. Accessing 8, 16 and 32 bit sized containers requires 2D bursts, and page mode sized containers require 1D bursts. The DSS2 user is expected to provide the Tiler address of the view that it is interested in. This is passed to the paddr and p_uv_addr parameters in omap_overlay_info. It is also expected to provide the stride value based on the view's orientation and container type, this should be passed to the screen_width parameter of omap_overlay_info. In calc_tiler_rotation_offset screen_width is used to calculate the required row_inc for DISPC. x_predecim and y_predecim are also used to calculate row_inc and pix_inc thereby adding predecimation support for TILER. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-11 13:49:55 +00:00
static void dispc_ovl_configure_burst_type(enum omap_plane plane,
enum omap_dss_rotation_type rotation_type)
{
if (dss_has_feature(FEAT_BURST_2D) == 0)
return;
if (rotation_type == OMAP_DSS_ROT_TILER)
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
else
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
}
OMAPDSS: DISPC: make dispc_ovl_set_channel_out() public Make dispc_ovl_set_channel_out() public so that later patches can handle changing overlay's manager. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-10-28 12:26:26 +00:00
void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
int shift;
u32 val;
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
int chan = 0, chan2 = 0;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
switch (plane) {
case OMAP_DSS_GFX:
shift = 8;
break;
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
OMAPDSS: DISPC: VIDEO3 pipeline support Add support for VIDEO3 pipeline on OMAP4: - Add VIDEO3 pipeline information in dss_features and omapdss.h - Add VIDEO3 pipeline register coefficients in dispc.h - Create a new overlay structure corresponding to VIDEO3. - Make changes in dispc.c for VIDEO3 Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-13 12:50:33 +00:00
case OMAP_DSS_VIDEO3:
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
shift = 16;
break;
default:
BUG();
return;
}
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
if (dss_has_feature(FEAT_MGR_LCD2)) {
switch (channel) {
case OMAP_DSS_CHANNEL_LCD:
chan = 0;
chan2 = 0;
break;
case OMAP_DSS_CHANNEL_DIGIT:
chan = 1;
chan2 = 0;
break;
case OMAP_DSS_CHANNEL_LCD2:
chan = 0;
chan2 = 1;
break;
OMAPDSS: Add LCD3 overlay manager and Clock and IRQ support The support for LCD3 manager has been added into the manager module. LCD3 panel has registers as DISPC_CONTROL3 and DISPC_CONFIG3 just like those in LCD and LCD2 panels. These registers control the Display Controller (DISPC) module for LCD3 output. The three LCDs support Display Serial Interface (DSI), Remote Frame Buffer Interface (RFBI) and Parallel CMOS Output Interface (DPI). These LCDs can be connected through parallel output interface using DISPC and RFBI or DPI. For serial interface DSS uses DSI. The LCD3 panel, just like LCD and LCD2 panels, has a clock switch in DSS_CTRL register which has been enabled. The clock switch chooses between DSS_CLK and DPLL_DSI1_C_CLK1 as source for LCD3_CLK. New IRQs as DISPC_IRQ_VSYNC3, DISPC_IRQ_FRAMEDONE3, DISPC_IRQ_ACBIAS_COUNT_STAT3 and DISPC_IRQ_SYNC_LOST3 have been added specific to the new manager. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-29 05:13:13 +00:00
case OMAP_DSS_CHANNEL_LCD3:
if (dss_has_feature(FEAT_MGR_LCD3)) {
chan = 0;
chan2 = 2;
} else {
BUG();
return;
}
break;
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
default:
BUG();
OMAPDSS: remove compiler warnings when CONFIG_BUG=n If CONFIG_BUG is not enabled, BUG() does not stop the execution. Many places in code expect the execution to stop, and this causes compiler warnings about uninitialized variables and returning from a non-void function without a return value. This patch fixes the warnings by initializing the variables and returning properly after BUG() lines. However, the behaviour is still undefined after the BUG, but this is the choice the user makes when using CONFIG_BUG=n. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 08:47:02 +00:00
return;
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
}
val = FLD_MOD(val, chan, shift, shift);
val = FLD_MOD(val, chan2, 31, 30);
} else {
val = FLD_MOD(val, channel, shift, shift);
}
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_ovl_set_channel_out);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: separate overlay channel from ovl_setup Overlay channel is configured with ovl_setup, with all the other overlay attriutes. This patch separates overlay channel setup so that we can later configure the channel only when needed. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-03 15:03:44 +00:00
static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
{
int shift;
u32 val;
enum omap_channel channel;
switch (plane) {
case OMAP_DSS_GFX:
shift = 8;
break;
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
case OMAP_DSS_VIDEO3:
shift = 16;
break;
default:
BUG();
OMAPDSS: remove compiler warnings when CONFIG_BUG=n If CONFIG_BUG is not enabled, BUG() does not stop the execution. Many places in code expect the execution to stop, and this causes compiler warnings about uninitialized variables and returning from a non-void function without a return value. This patch fixes the warnings by initializing the variables and returning properly after BUG() lines. However, the behaviour is still undefined after the BUG, but this is the choice the user makes when using CONFIG_BUG=n. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 08:47:02 +00:00
return 0;
OMAPDSS: separate overlay channel from ovl_setup Overlay channel is configured with ovl_setup, with all the other overlay attriutes. This patch separates overlay channel setup so that we can later configure the channel only when needed. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-03 15:03:44 +00:00
}
val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
OMAPDSS: Add LCD3 overlay manager and Clock and IRQ support The support for LCD3 manager has been added into the manager module. LCD3 panel has registers as DISPC_CONTROL3 and DISPC_CONFIG3 just like those in LCD and LCD2 panels. These registers control the Display Controller (DISPC) module for LCD3 output. The three LCDs support Display Serial Interface (DSI), Remote Frame Buffer Interface (RFBI) and Parallel CMOS Output Interface (DPI). These LCDs can be connected through parallel output interface using DISPC and RFBI or DPI. For serial interface DSS uses DSI. The LCD3 panel, just like LCD and LCD2 panels, has a clock switch in DSS_CTRL register which has been enabled. The clock switch chooses between DSS_CLK and DPLL_DSI1_C_CLK1 as source for LCD3_CLK. New IRQs as DISPC_IRQ_VSYNC3, DISPC_IRQ_FRAMEDONE3, DISPC_IRQ_ACBIAS_COUNT_STAT3 and DISPC_IRQ_SYNC_LOST3 have been added specific to the new manager. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-29 05:13:13 +00:00
if (dss_has_feature(FEAT_MGR_LCD3)) {
if (FLD_GET(val, 31, 30) == 0)
channel = FLD_GET(val, shift, shift);
else if (FLD_GET(val, 31, 30) == 1)
channel = OMAP_DSS_CHANNEL_LCD2;
else
channel = OMAP_DSS_CHANNEL_LCD3;
} else if (dss_has_feature(FEAT_MGR_LCD2)) {
OMAPDSS: separate overlay channel from ovl_setup Overlay channel is configured with ovl_setup, with all the other overlay attriutes. This patch separates overlay channel setup so that we can later configure the channel only when needed. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-03 15:03:44 +00:00
if (FLD_GET(val, 31, 30) == 0)
channel = FLD_GET(val, shift, shift);
else
channel = OMAP_DSS_CHANNEL_LCD2;
} else {
channel = FLD_GET(val, shift, shift);
}
return channel;
}
OMAPDSS: DISPC: Add function to set channel in for writeback Writeback can take input from either one of the overlays, or one of the overlay managers. Add an enum which represents the channel_in for writeback, and maps to the register field programming. Add a function to configure channel in for writeback. This will be used later in APPLY. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-22 07:08:19 +00:00
void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
{
enum omap_plane plane = OMAP_DSS_WB;
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_burst_size(enum omap_plane plane,
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
enum omap_burst_size burst_size)
{
OMAPDSS: DISPC: Configure writeback FIFOs Extend the DISPC fifo functions to also configure the writeback FIFO thresholds. The most optimal configuration for writeback is to push out data to the interconnect the moment writeback pushes enough pixels in the FIFO to form a burst. This reduces the chance of writeback overflowing it's FIFO. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-10 12:01:39 +00:00
static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
int shift;
OMAP: DSS2: DISPC: use lookup tables for bit shifts Use lookup tables instead of switch/if in some DISPC functions to make the code cleaner. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Archit Taneja <archit@ti.com>
2011-08-15 08:51:50 +00:00
shift = shifts[plane];
OMAP: DSS2: Fix FIFO threshold and burst size for OMAP4 The DMA FIFO threshold registers and burst size registers have changed for OMAP4. The current code only handles OMAP2/3 case, and so the values are a bit off for OMAP4. A summary of the differences between OMAP2/3 and OMAP4: Burst size: OMAP2/3: 4 x 32 bits / 8 x 32 bits / 16 x 32 bits OMAP4: 2 x 128 bits / 4 x 128 bits / 8 x 128 bits Threshold size: OMAP2/3: in bytes (8 bit units) OMAP4: in 128bit units This patch fixes the issue by creating two new helper functions in dss_features: dss_feat_get_buffer_size_unit() and dss_feat_get_burst_size_unit(). These return (in bytes) the unit size for threshold registers and unit size for burst size register, respectively, and are used to calculate correct values. For the threshold size the usage is straightforward. However, the burst size register has different multipliers for OMAP2/3 and OMAP4. This patch solves the problem by defining the multipliers for the burst size as 2x, 4x and 8x, which fit fine for the OMAP4 burst size definition (i.e. burst size unit for OMAP4 is 128bits), but requires a slight twist on OMAP2/3 by defining the burst size unit as 64bit. As the driver in practice always uses the maximum burst size, and no use case currently exists where we would want to use a smaller burst size, this patch changes the driver to hardcode the burst size when initializing DISPC. This makes the threshold configuration code somewhat simpler. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:35:36 +00:00
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: Fix FIFO threshold and burst size for OMAP4 The DMA FIFO threshold registers and burst size registers have changed for OMAP4. The current code only handles OMAP2/3 case, and so the values are a bit off for OMAP4. A summary of the differences between OMAP2/3 and OMAP4: Burst size: OMAP2/3: 4 x 32 bits / 8 x 32 bits / 16 x 32 bits OMAP4: 2 x 128 bits / 4 x 128 bits / 8 x 128 bits Threshold size: OMAP2/3: in bytes (8 bit units) OMAP4: in 128bit units This patch fixes the issue by creating two new helper functions in dss_features: dss_feat_get_buffer_size_unit() and dss_feat_get_burst_size_unit(). These return (in bytes) the unit size for threshold registers and unit size for burst size register, respectively, and are used to calculate correct values. For the threshold size the usage is straightforward. However, the burst size register has different multipliers for OMAP2/3 and OMAP4. This patch solves the problem by defining the multipliers for the burst size as 2x, 4x and 8x, which fit fine for the OMAP4 burst size definition (i.e. burst size unit for OMAP4 is 128bits), but requires a slight twist on OMAP2/3 by defining the burst size unit as 64bit. As the driver in practice always uses the maximum burst size, and no use case currently exists where we would want to use a smaller burst size, this patch changes the driver to hardcode the burst size when initializing DISPC. This makes the threshold configuration code somewhat simpler. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:35:36 +00:00
static void dispc_configure_burst_sizes(void)
{
int i;
const int burst_size = BURST_SIZE_X8;
/* Configure burst size always to maximum size */
OMAPDSS: DISPC: use dss_feat_get_num_ovls() Use dss_feat_get_num_ovls() in dispc.c instead of omap_dss_get_num_overlays() to remove the dependency to overlay.c. Note that we still have uses of omap_dss_get_num_overlays() in dispc.c, but these will be moved out in the future patches. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-15 12:37:22 +00:00
for (i = 0; i < dss_feat_get_num_ovls(); ++i)
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
dispc_ovl_set_burst_size(i, burst_size);
OMAP: DSS2: Fix FIFO threshold and burst size for OMAP4 The DMA FIFO threshold registers and burst size registers have changed for OMAP4. The current code only handles OMAP2/3 case, and so the values are a bit off for OMAP4. A summary of the differences between OMAP2/3 and OMAP4: Burst size: OMAP2/3: 4 x 32 bits / 8 x 32 bits / 16 x 32 bits OMAP4: 2 x 128 bits / 4 x 128 bits / 8 x 128 bits Threshold size: OMAP2/3: in bytes (8 bit units) OMAP4: in 128bit units This patch fixes the issue by creating two new helper functions in dss_features: dss_feat_get_buffer_size_unit() and dss_feat_get_burst_size_unit(). These return (in bytes) the unit size for threshold registers and unit size for burst size register, respectively, and are used to calculate correct values. For the threshold size the usage is straightforward. However, the burst size register has different multipliers for OMAP2/3 and OMAP4. This patch solves the problem by defining the multipliers for the burst size as 2x, 4x and 8x, which fit fine for the OMAP4 burst size definition (i.e. burst size unit for OMAP4 is 128bits), but requires a slight twist on OMAP2/3 by defining the burst size unit as 64bit. As the driver in practice always uses the maximum burst size, and no use case currently exists where we would want to use a smaller burst size, this patch changes the driver to hardcode the burst size when initializing DISPC. This makes the threshold configuration code somewhat simpler. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:35:36 +00:00
}
OMAPDSS: DISPC: move fifo threhold calc to dispc.c Move fifo threshold calculation into dispc.c, as the thresholds are really dispc internal thing. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:17:01 +00:00
static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
OMAP: DSS2: Fix FIFO threshold and burst size for OMAP4 The DMA FIFO threshold registers and burst size registers have changed for OMAP4. The current code only handles OMAP2/3 case, and so the values are a bit off for OMAP4. A summary of the differences between OMAP2/3 and OMAP4: Burst size: OMAP2/3: 4 x 32 bits / 8 x 32 bits / 16 x 32 bits OMAP4: 2 x 128 bits / 4 x 128 bits / 8 x 128 bits Threshold size: OMAP2/3: in bytes (8 bit units) OMAP4: in 128bit units This patch fixes the issue by creating two new helper functions in dss_features: dss_feat_get_buffer_size_unit() and dss_feat_get_burst_size_unit(). These return (in bytes) the unit size for threshold registers and unit size for burst size register, respectively, and are used to calculate correct values. For the threshold size the usage is straightforward. However, the burst size register has different multipliers for OMAP2/3 and OMAP4. This patch solves the problem by defining the multipliers for the burst size as 2x, 4x and 8x, which fit fine for the OMAP4 burst size definition (i.e. burst size unit for OMAP4 is 128bits), but requires a slight twist on OMAP2/3 by defining the burst size unit as 64bit. As the driver in practice always uses the maximum burst size, and no use case currently exists where we would want to use a smaller burst size, this patch changes the driver to hardcode the burst size when initializing DISPC. This makes the threshold configuration code somewhat simpler. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:35:36 +00:00
{
unsigned unit = dss_feat_get_burst_size_unit();
/* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
return unit * 8;
}
OMAP4: DSS2: HDMI: Dispc gamma enable set/reset function for TV. Adding function to reset/set gamma table bit for TV interface, currently only support for disabled is added. Signed-off-by: Mythri P K <mythripk@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-11 12:32:49 +00:00
void dispc_enable_gamma_table(bool enable)
{
/*
* This is partially implemented to support only disabling of
* the gamma table.
*/
if (enable) {
DSSWARN("Gamma table enabling for TV not yet supported");
return;
}
REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
}
OMAPDSS: setup manager with dispc_mgr_setup() Change manager configuration to be similar to overlay configuration by creating dispc_mgr_setup() which takes omap_overlay_manager_info as parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-04 16:14:20 +00:00
static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
OMAP: DSS2: Add Color Phase Rotation support Add Color Phase Rotation (CPR) support and sysfs files to enable CPR and to set the CPR coefficient matrix. CPR is enabled via manager?/cpr_enable file, and the coefficient matrix is set via manager?/cpr_coef file. The values in cpr_coef are in the following order: RR RG RB GR GG GB BR BG BB Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:34:30 +00:00
{
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
if (channel == OMAP_DSS_CHANNEL_DIGIT)
OMAP: DSS2: Add Color Phase Rotation support Add Color Phase Rotation (CPR) support and sysfs files to enable CPR and to set the CPR coefficient matrix. CPR is enabled via manager?/cpr_enable file, and the coefficient matrix is set via manager?/cpr_coef file. The values in cpr_coef are in the following order: RR RG RB GR GG GB BR BG BB Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:34:30 +00:00
return;
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
OMAP: DSS2: Add Color Phase Rotation support Add Color Phase Rotation (CPR) support and sysfs files to enable CPR and to set the CPR coefficient matrix. CPR is enabled via manager?/cpr_enable file, and the coefficient matrix is set via manager?/cpr_coef file. The values in cpr_coef are in the following order: RR RG RB GR GG GB BR BG BB Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:34:30 +00:00
}
OMAPDSS: setup manager with dispc_mgr_setup() Change manager configuration to be similar to overlay configuration by creating dispc_mgr_setup() which takes omap_overlay_manager_info as parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-04 16:14:20 +00:00
static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
OMAPDSS: DISPC: constify function parameters Add consts to dispc function parameters which do not modify the passed structs. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-03 07:09:11 +00:00
const struct omap_dss_cpr_coefs *coefs)
OMAP: DSS2: Add Color Phase Rotation support Add Color Phase Rotation (CPR) support and sysfs files to enable CPR and to set the CPR coefficient matrix. CPR is enabled via manager?/cpr_enable file, and the coefficient matrix is set via manager?/cpr_coef file. The values in cpr_coef are in the following order: RR RG RB GR GG GB BR BG BB Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:34:30 +00:00
{
u32 coef_r, coef_g, coef_b;
OMAPDSS: DISPC: Remove a redundant function dss_mgr_is_lcd() available in dss.h does the same thing as dispc_mgr_is_lcd() in dispc.c. Remove the function from dispc.c and replace it with the one in dss.h. Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-29 09:11:30 +00:00
if (!dss_mgr_is_lcd(channel))
OMAP: DSS2: Add Color Phase Rotation support Add Color Phase Rotation (CPR) support and sysfs files to enable CPR and to set the CPR coefficient matrix. CPR is enabled via manager?/cpr_enable file, and the coefficient matrix is set via manager?/cpr_coef file. The values in cpr_coef are in the following order: RR RG RB GR GG GB BR BG BB Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:34:30 +00:00
return;
coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
FLD_VAL(coefs->rb, 9, 0);
coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
FLD_VAL(coefs->gb, 9, 0);
coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
FLD_VAL(coefs->bb, 9, 0);
dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
u32 val;
BUG_ON(plane == OMAP_DSS_GFX);
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
val = FLD_MOD(val, enable, 9, 9);
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: OVERLAY: Add position and replication as overlay caps Add position and replication as overlay caps, and pass overlay caps as an argument to the corresponding functions. Adding position and replication to overlay caps seems a bit unnecessary, but it allows us to use the corresponding functions for writeback too. These caps will be set for all overlays, but not for writeback. This is done so writeback can reuse dispc_ovl_setup() to the maximum. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-22 07:00:17 +00:00
static void dispc_ovl_enable_replication(enum omap_plane plane,
enum omap_overlay_caps caps, bool enable)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: DISPC: VIDEO3 pipeline support Add support for VIDEO3 pipeline on OMAP4: - Add VIDEO3 pipeline information in dss_features and omapdss.h - Add VIDEO3 pipeline register coefficients in dispc.h - Create a new overlay structure corresponding to VIDEO3. - Make changes in dispc.c for VIDEO3 Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-13 12:50:33 +00:00
static const unsigned shifts[] = { 5, 10, 10, 10 };
OMAP: DSS2: DISPC: use lookup tables for bit shifts Use lookup tables instead of switch/if in some DISPC functions to make the code cleaner. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Archit Taneja <archit@ti.com>
2011-08-15 08:51:50 +00:00
int shift;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: OVERLAY: Add position and replication as overlay caps Add position and replication as overlay caps, and pass overlay caps as an argument to the corresponding functions. Adding position and replication to overlay caps seems a bit unnecessary, but it allows us to use the corresponding functions for writeback too. These caps will be set for all overlays, but not for writeback. This is done so writeback can reuse dispc_ovl_setup() to the maximum. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-22 07:00:17 +00:00
if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
return;
OMAP: DSS2: DISPC: use lookup tables for bit shifts Use lookup tables instead of switch/if in some DISPC functions to make the code cleaner. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Archit Taneja <archit@ti.com>
2011-08-15 08:51:50 +00:00
shift = shifts[plane];
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: DISPC: Clean up manager timing/size functions Clean up the DISPC manager timings related function by: - Create a common function to set size for LCD and TV. - Create a common function to check timings for LCD and TV. - Add dss params to get the range of manager size. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:44 +00:00
static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
OMAPDSS: DISPC/RFBI: Use dispc_mgr_set_lcd_timings() for setting lcd size The RFBI driver uses dispc_mgr_set_lcd_size() to set the width and height of the LCD manager. Replace this to use dispc_mgr_set_lcd_timings(), pass dummy blanking parameters like done in the DSI driver. This prevents the need to export dispc_mgr_set_lcd_size(), and use a common function to set lcd timings. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:42 +00:00
u16 height)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
u32 val;
OMAPDSS: Add overlay manager width and height limits as a dispc feature The overlay manager width and height vary in OMAP5 from previous OMAPs in terms of maximum limit and register field positions. Add parameters in dispc_features for these. Also remove params related to manager width and height from dss_features, as we want to maintain a feature list for individual IPs. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-14 08:20:15 +00:00
val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
OMAPDSS: DISPC: Clean up manager timing/size functions Clean up the DISPC manager timings related function by: - Create a common function to set size for LCD and TV. - Create a common function to check timings for LCD and TV. - Add dss params to get the range of manager size. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:44 +00:00
dispc_write_reg(DISPC_SIZE_MGR(channel), val);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: Improve fifo management code OMAP4+ allows assigning the overlay FIFOs freely, but that is not supported by omapdss yet. This patch takes a step forward by improving the fifo management to be more flexible. dispc.c is changed to keep track of the sizes of each fifo, and also the overlay using each fifo. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:56:57 +00:00
static void dispc_init_fifos(void)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
u32 size;
OMAPDSS: Improve fifo management code OMAP4+ allows assigning the overlay FIFOs freely, but that is not supported by omapdss yet. This patch takes a step forward by improving the fifo management to be more flexible. dispc.c is changed to keep track of the sizes of each fifo, and also the overlay using each fifo. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:56:57 +00:00
int fifo;
OMAP: DSS2: Use dss_features framework on DSS2 code Calls init functions of dss_features during dss_probe, and the following features are made omapxxxx independent: - number of managers, overlays - supported color modes for each overlay - supported displays for each manager - global aplha, and restriction of global alpha for video1 pipeline - The register field ranges : FIRHINC, FIRVINC, FIFOHIGHTHRESHOLD FIFOLOWTHRESHOLD and FIFOSIZE Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-09-15 13:50:00 +00:00
u8 start, end;
OMAP: DSS2: Fix FIFO threshold and burst size for OMAP4 The DMA FIFO threshold registers and burst size registers have changed for OMAP4. The current code only handles OMAP2/3 case, and so the values are a bit off for OMAP4. A summary of the differences between OMAP2/3 and OMAP4: Burst size: OMAP2/3: 4 x 32 bits / 8 x 32 bits / 16 x 32 bits OMAP4: 2 x 128 bits / 4 x 128 bits / 8 x 128 bits Threshold size: OMAP2/3: in bytes (8 bit units) OMAP4: in 128bit units This patch fixes the issue by creating two new helper functions in dss_features: dss_feat_get_buffer_size_unit() and dss_feat_get_burst_size_unit(). These return (in bytes) the unit size for threshold registers and unit size for burst size register, respectively, and are used to calculate correct values. For the threshold size the usage is straightforward. However, the burst size register has different multipliers for OMAP2/3 and OMAP4. This patch solves the problem by defining the multipliers for the burst size as 2x, 4x and 8x, which fit fine for the OMAP4 burst size definition (i.e. burst size unit for OMAP4 is 128bits), but requires a slight twist on OMAP2/3 by defining the burst size unit as 64bit. As the driver in practice always uses the maximum burst size, and no use case currently exists where we would want to use a smaller burst size, this patch changes the driver to hardcode the burst size when initializing DISPC. This makes the threshold configuration code somewhat simpler. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:35:36 +00:00
u32 unit;
OMAPDSS: setup default fifo thresholds At the moment we don't setup FIFO thresholds by default in omapdss. It's supposed to be done by the user of omapdss. And that is missing from omapdrm, causing unoptimal thresholds to be used when using omapdrm. While I believe it's in theory better to allow the user of omapdss to setup the fifo thresholds, in practice we always use the same values, and we could as well setup the thresholds in omapdss. Furthermore, in omapdss init we always swap the FIFO used for GFX and WB overlays, but we don't swap the FIFO thresholds for those overlays (which is the reason for omapdrm using unoptimal HW reset values). So it would make sense to setup the thresholds to account for the swapping of the FIFOs. So, this patch adds code to setup default FIFO tresholds at omapdss init. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-09-29 20:46:17 +00:00
int i;
OMAP: DSS2: Fix FIFO threshold and burst size for OMAP4 The DMA FIFO threshold registers and burst size registers have changed for OMAP4. The current code only handles OMAP2/3 case, and so the values are a bit off for OMAP4. A summary of the differences between OMAP2/3 and OMAP4: Burst size: OMAP2/3: 4 x 32 bits / 8 x 32 bits / 16 x 32 bits OMAP4: 2 x 128 bits / 4 x 128 bits / 8 x 128 bits Threshold size: OMAP2/3: in bytes (8 bit units) OMAP4: in 128bit units This patch fixes the issue by creating two new helper functions in dss_features: dss_feat_get_buffer_size_unit() and dss_feat_get_burst_size_unit(). These return (in bytes) the unit size for threshold registers and unit size for burst size register, respectively, and are used to calculate correct values. For the threshold size the usage is straightforward. However, the burst size register has different multipliers for OMAP2/3 and OMAP4. This patch solves the problem by defining the multipliers for the burst size as 2x, 4x and 8x, which fit fine for the OMAP4 burst size definition (i.e. burst size unit for OMAP4 is 128bits), but requires a slight twist on OMAP2/3 by defining the burst size unit as 64bit. As the driver in practice always uses the maximum burst size, and no use case currently exists where we would want to use a smaller burst size, this patch changes the driver to hardcode the burst size when initializing DISPC. This makes the threshold configuration code somewhat simpler. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:35:36 +00:00
unit = dss_feat_get_buffer_size_unit();
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Use dss_features framework on DSS2 code Calls init functions of dss_features during dss_probe, and the following features are made omapxxxx independent: - number of managers, overlays - supported color modes for each overlay - supported displays for each manager - global aplha, and restriction of global alpha for video1 pipeline - The register field ranges : FIRHINC, FIRVINC, FIFOHIGHTHRESHOLD FIFOLOWTHRESHOLD and FIFOSIZE Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-09-15 13:50:00 +00:00
dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: Improve fifo management code OMAP4+ allows assigning the overlay FIFOs freely, but that is not supported by omapdss yet. This patch takes a step forward by improving the fifo management to be more flexible. dispc.c is changed to keep track of the sizes of each fifo, and also the overlay using each fifo. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:56:57 +00:00
for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
OMAP: DSS2: Fix FIFO threshold and burst size for OMAP4 The DMA FIFO threshold registers and burst size registers have changed for OMAP4. The current code only handles OMAP2/3 case, and so the values are a bit off for OMAP4. A summary of the differences between OMAP2/3 and OMAP4: Burst size: OMAP2/3: 4 x 32 bits / 8 x 32 bits / 16 x 32 bits OMAP4: 2 x 128 bits / 4 x 128 bits / 8 x 128 bits Threshold size: OMAP2/3: in bytes (8 bit units) OMAP4: in 128bit units This patch fixes the issue by creating two new helper functions in dss_features: dss_feat_get_buffer_size_unit() and dss_feat_get_burst_size_unit(). These return (in bytes) the unit size for threshold registers and unit size for burst size register, respectively, and are used to calculate correct values. For the threshold size the usage is straightforward. However, the burst size register has different multipliers for OMAP2/3 and OMAP4. This patch solves the problem by defining the multipliers for the burst size as 2x, 4x and 8x, which fit fine for the OMAP4 burst size definition (i.e. burst size unit for OMAP4 is 128bits), but requires a slight twist on OMAP2/3 by defining the burst size unit as 64bit. As the driver in practice always uses the maximum burst size, and no use case currently exists where we would want to use a smaller burst size, this patch changes the driver to hardcode the burst size when initializing DISPC. This makes the threshold configuration code somewhat simpler. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:35:36 +00:00
size *= unit;
OMAPDSS: Improve fifo management code OMAP4+ allows assigning the overlay FIFOs freely, but that is not supported by omapdss yet. This patch takes a step forward by improving the fifo management to be more flexible. dispc.c is changed to keep track of the sizes of each fifo, and also the overlay using each fifo. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:56:57 +00:00
dispc.fifo_size[fifo] = size;
/*
* By default fifos are mapped directly to overlays, fifo 0 to
* ovl 0, fifo 1 to ovl 1, etc.
*/
dispc.fifo_assignment[fifo] = fifo;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: Use WB fifo for GFX overlay OMAP4's GFX overlay has smaller fifo than the rest of the overlays (including writeback "overlay"). This seems to be the reason for underflows in some more demanding scenarios. We can avoid the problems by using the WB fifo for GFX overlay, and vice versa. WB usage is not supported yet, but when it will, it should perform just fine with smaller fifo as there are no hard realtime constraints with WB. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:57:02 +00:00
/*
* The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
* causes problems with certain use cases, like using the tiler in 2D
* mode. The below hack swaps the fifos of GFX and WB planes, thus
* giving GFX plane a larger fifo. WB but should work fine with a
* smaller fifo.
*/
if (dispc.feat->gfx_fifo_workaround) {
u32 v;
v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
}
OMAPDSS: setup default fifo thresholds At the moment we don't setup FIFO thresholds by default in omapdss. It's supposed to be done by the user of omapdss. And that is missing from omapdrm, causing unoptimal thresholds to be used when using omapdrm. While I believe it's in theory better to allow the user of omapdss to setup the fifo thresholds, in practice we always use the same values, and we could as well setup the thresholds in omapdss. Furthermore, in omapdss init we always swap the FIFO used for GFX and WB overlays, but we don't swap the FIFO thresholds for those overlays (which is the reason for omapdrm using unoptimal HW reset values). So it would make sense to setup the thresholds to account for the swapping of the FIFOs. So, this patch adds code to setup default FIFO tresholds at omapdss init. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-09-29 20:46:17 +00:00
/*
* Setup default fifo thresholds.
*/
for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
u32 low, high;
const bool use_fifomerge = false;
const bool manual_update = false;
dispc_ovl_compute_fifo_thresholds(i, &low, &high,
use_fifomerge, manual_update);
dispc_ovl_set_fifo_threshold(i, low, high);
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: DISPC: move fifo threhold calc to dispc.c Move fifo threshold calculation into dispc.c, as the thresholds are really dispc internal thing. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:17:01 +00:00
static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: Improve fifo management code OMAP4+ allows assigning the overlay FIFOs freely, but that is not supported by omapdss yet. This patch takes a step forward by improving the fifo management to be more flexible. dispc.c is changed to keep track of the sizes of each fifo, and also the overlay using each fifo. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:56:57 +00:00
int fifo;
u32 size = 0;
for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
if (dispc.fifo_assignment[fifo] == plane)
size += dispc.fifo_size[fifo];
}
return size;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: DISPC: make dispc_ovl_set_fifo_threshold() public Make dispc_ovl_set_fifo_threshold() public so that later patches can handle overlay fifo configuration. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-10-31 06:58:52 +00:00
void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: Use dss_features framework on DSS2 code Calls init functions of dss_features during dss_probe, and the following features are made omapxxxx independent: - number of managers, overlays - supported color modes for each overlay - supported displays for each manager - global aplha, and restriction of global alpha for video1 pipeline - The register field ranges : FIRHINC, FIRVINC, FIFOHIGHTHRESHOLD FIFOLOWTHRESHOLD and FIFOSIZE Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-09-15 13:50:00 +00:00
u8 hi_start, hi_end, lo_start, lo_end;
OMAP: DSS2: Fix FIFO threshold and burst size for OMAP4 The DMA FIFO threshold registers and burst size registers have changed for OMAP4. The current code only handles OMAP2/3 case, and so the values are a bit off for OMAP4. A summary of the differences between OMAP2/3 and OMAP4: Burst size: OMAP2/3: 4 x 32 bits / 8 x 32 bits / 16 x 32 bits OMAP4: 2 x 128 bits / 4 x 128 bits / 8 x 128 bits Threshold size: OMAP2/3: in bytes (8 bit units) OMAP4: in 128bit units This patch fixes the issue by creating two new helper functions in dss_features: dss_feat_get_buffer_size_unit() and dss_feat_get_burst_size_unit(). These return (in bytes) the unit size for threshold registers and unit size for burst size register, respectively, and are used to calculate correct values. For the threshold size the usage is straightforward. However, the burst size register has different multipliers for OMAP2/3 and OMAP4. This patch solves the problem by defining the multipliers for the burst size as 2x, 4x and 8x, which fit fine for the OMAP4 burst size definition (i.e. burst size unit for OMAP4 is 128bits), but requires a slight twist on OMAP2/3 by defining the burst size unit as 64bit. As the driver in practice always uses the maximum burst size, and no use case currently exists where we would want to use a smaller burst size, this patch changes the driver to hardcode the burst size when initializing DISPC. This makes the threshold configuration code somewhat simpler. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:35:36 +00:00
u32 unit;
unit = dss_feat_get_buffer_size_unit();
WARN_ON(low % unit != 0);
WARN_ON(high % unit != 0);
low /= unit;
high /= unit;
OMAP: DSS2: Use dss_features framework on DSS2 code Calls init functions of dss_features during dss_probe, and the following features are made omapxxxx independent: - number of managers, overlays - supported color modes for each overlay - supported displays for each manager - global aplha, and restriction of global alpha for video1 pipeline - The register field ranges : FIRHINC, FIRVINC, FIFOHIGHTHRESHOLD FIFOLOWTHRESHOLD and FIFOSIZE Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-09-15 13:50:00 +00:00
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
OMAPDSS: DISPC: print fifo threshold values in bytes Fifo thresholds are calculated using bytes, but the debug print prints values in buffer units. Change the prints to use bytes to be in line with the calculations, and also to print in the same units on all OMAPs. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:14:57 +00:00
DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
plane,
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
OMAPDSS: DISPC: print fifo threshold values in bytes Fifo thresholds are calculated using bytes, but the debug print prints values in buffer units. Change the prints to use bytes to be in line with the calculations, and also to print in the same units on all OMAPs. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:14:57 +00:00
lo_start, lo_end) * unit,
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
OMAPDSS: DISPC: print fifo threshold values in bytes Fifo thresholds are calculated using bytes, but the debug print prints values in buffer units. Change the prints to use bytes to be in line with the calculations, and also to print in the same units on all OMAPs. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:14:57 +00:00
hi_start, hi_end) * unit,
low * unit, high * unit);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
OMAP: DSS2: Use dss_features framework on DSS2 code Calls init functions of dss_features during dss_probe, and the following features are made omapxxxx independent: - number of managers, overlays - supported color modes for each overlay - supported displays for each manager - global aplha, and restriction of global alpha for video1 pipeline - The register field ranges : FIRHINC, FIRVINC, FIFOHIGHTHRESHOLD FIFOLOWTHRESHOLD and FIFOSIZE Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-09-15 13:50:00 +00:00
FLD_VAL(high, hi_start, hi_end) |
FLD_VAL(low, lo_start, lo_end));
OMAPDSS: DISPC: Preload more data in pipeline DMAs for OMAP4+ SoCs DISPC pipeline DMAs preload some bytes of pixel data in the vertical blanking region before the start of each frame. The preload ensures the pipeline doesn't underflow when the active region of the display starts. DISPC_GFX/VIDp_PRELOAD registers allow us to program how many bytes of data should be preloaded for each pipeline. Calculating a precise preload value would be a complex function of the pixel clock of the connected display, the vertical blanking duration and the interconnect traffic at that instance. If the register is left untouched, a default value is preloaded. We observe underflows for OMAP4+ SoCs for certain bandwidth intensive use cases with many other initiators active, and in situations where memory access isn't very efficient(like accessing Tiler mapped buffers and EMIF configured in non-interleaved more). The cause of the underflow is because the default preload value isn't sufficient for the DMA to reach a steady state. We configure the PRELOAD register such that the pipelines preload data up to the high threshold of the FIFO. Preloading lot of data for older SoCs can have a negative impact. Due to slower interconnects, it's possible that the DISPC DMA cannot preload up to the high threshold within the vertical blanking region of the panel. We leave the PRELOAD registers to their reset values since we haven't faced underflows with these SoCs because of low value of PRELOAD. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-12-17 11:10:21 +00:00
/*
* configure the preload to the pipeline's high threhold, if HT it's too
* large for the preload field, set the threshold to the maximum value
* that can be held by the preload register
*/
if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
plane != OMAP_DSS_WB)
dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: fix missing EXPORT_SYMBOL()s Functions dispc_ovl_set_fifo_threshold and dispc_ovl_compute_fifo_thresholds need to be exported. Add the EXPORT_SYMBOLs. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-11-08 08:07:20 +00:00
EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
void dispc_enable_fifomerge(bool enable)
{
OMAPDSS: FEAT: Add FIFO_MERGE feature Add feature flag for fifo merge. OMAP2 doesn't contain fifo merge, later OMAPs do. dispc_enable_fifomerge() checks for the flag when called, and gives a WARN if fifo merge is being enabled when it is not supported. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:24:04 +00:00
if (!dss_has_feature(FEAT_FIFO_MERGE)) {
WARN_ON(enable);
return;
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
}
OMAPDSS: DISPC: move fifo threhold calc to dispc.c Move fifo threshold calculation into dispc.c, as the thresholds are really dispc internal thing. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:17:01 +00:00
void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
OMAPDSS: use DSI_FIFO_BUG workaround only for manual update displays There is a problem related to DSS FIFO thresholds and power management on OMAP3. It seems that when the full PM hits in, we get underflows. The core reason is unknown, but after experiments it looks like only particular FIFO thresholds work correctly. This bug is related to an earlier patch, which added special FIFO threshold configuration for OMAP3, because DSI command mode output didn't work with the normal threshold configuration. However, as the above work-around worked fine for other output types also, we currently always configure thresholds in this special way on OMAP3. In theory there should be negligible difference with this special way and the standard way. The first paragraph explains what happens in practice. This patch changes the driver to use the special threshold configuration only when the output is a manual update display on OMAP3. This does include RFBI displays also, and although it hasn't been tested (no boards using RFBI) I suspect the similar behaviour is present there also, as the DISPC side should work similarly for DSI command mode and RFBI. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Joe Woodward <jw@terrafix.co.uk>
2012-05-15 12:31:01 +00:00
u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
bool manual_update)
OMAPDSS: DISPC: move fifo threhold calc to dispc.c Move fifo threshold calculation into dispc.c, as the thresholds are really dispc internal thing. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:17:01 +00:00
{
/*
* All sizes are in bytes. Both the buffer and burst are made of
* buffer_units, and the fifo thresholds must be buffer_unit aligned.
*/
unsigned buf_unit = dss_feat_get_buffer_size_unit();
OMAPDSS: DISPC: Add naive threshold calc for fifomerge Take fifo merge into use by implementing a rather naive fifo merge threshold calculation: keep the low threshold always the same, but increase the high threshold when fifo merge is used. This should greatly increase the time between pixel data fetches from SDRAM, as the usable fifo size is much larger. However, it probably won't help for fifo underflows, as the low threshols is kept the same. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:18:11 +00:00
unsigned ovl_fifo_size, total_fifo_size, burst_size;
int i;
OMAPDSS: DISPC: move fifo threhold calc to dispc.c Move fifo threshold calculation into dispc.c, as the thresholds are really dispc internal thing. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:17:01 +00:00
burst_size = dispc_ovl_get_burst_size(plane);
OMAPDSS: DISPC: Add naive threshold calc for fifomerge Take fifo merge into use by implementing a rather naive fifo merge threshold calculation: keep the low threshold always the same, but increase the high threshold when fifo merge is used. This should greatly increase the time between pixel data fetches from SDRAM, as the usable fifo size is much larger. However, it probably won't help for fifo underflows, as the low threshols is kept the same. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:18:11 +00:00
ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
OMAPDSS: DISPC: move fifo threhold calc to dispc.c Move fifo threshold calculation into dispc.c, as the thresholds are really dispc internal thing. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:17:01 +00:00
OMAPDSS: DISPC: Add naive threshold calc for fifomerge Take fifo merge into use by implementing a rather naive fifo merge threshold calculation: keep the low threshold always the same, but increase the high threshold when fifo merge is used. This should greatly increase the time between pixel data fetches from SDRAM, as the usable fifo size is much larger. However, it probably won't help for fifo underflows, as the low threshols is kept the same. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:18:11 +00:00
if (use_fifomerge) {
total_fifo_size = 0;
OMAPDSS: DISPC: use dss_feat_get_num_ovls() Use dss_feat_get_num_ovls() in dispc.c instead of omap_dss_get_num_overlays() to remove the dependency to overlay.c. Note that we still have uses of omap_dss_get_num_overlays() in dispc.c, but these will be moved out in the future patches. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-15 12:37:22 +00:00
for (i = 0; i < dss_feat_get_num_ovls(); ++i)
OMAPDSS: DISPC: Add naive threshold calc for fifomerge Take fifo merge into use by implementing a rather naive fifo merge threshold calculation: keep the low threshold always the same, but increase the high threshold when fifo merge is used. This should greatly increase the time between pixel data fetches from SDRAM, as the usable fifo size is much larger. However, it probably won't help for fifo underflows, as the low threshols is kept the same. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:18:11 +00:00
total_fifo_size += dispc_ovl_get_fifo_size(i);
} else {
total_fifo_size = ovl_fifo_size;
}
/*
* We use the same low threshold for both fifomerge and non-fifomerge
* cases, but for fifomerge we calculate the high threshold using the
* combined fifo size
*/
OMAPDSS: use DSI_FIFO_BUG workaround only for manual update displays There is a problem related to DSS FIFO thresholds and power management on OMAP3. It seems that when the full PM hits in, we get underflows. The core reason is unknown, but after experiments it looks like only particular FIFO thresholds work correctly. This bug is related to an earlier patch, which added special FIFO threshold configuration for OMAP3, because DSI command mode output didn't work with the normal threshold configuration. However, as the above work-around worked fine for other output types also, we currently always configure thresholds in this special way on OMAP3. In theory there should be negligible difference with this special way and the standard way. The first paragraph explains what happens in practice. This patch changes the driver to use the special threshold configuration only when the output is a manual update display on OMAP3. This does include RFBI displays also, and although it hasn't been tested (no boards using RFBI) I suspect the similar behaviour is present there also, as the DISPC side should work similarly for DSI command mode and RFBI. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Joe Woodward <jw@terrafix.co.uk>
2012-05-15 12:31:01 +00:00
if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
OMAPDSS: DISPC: Add naive threshold calc for fifomerge Take fifo merge into use by implementing a rather naive fifo merge threshold calculation: keep the low threshold always the same, but increase the high threshold when fifo merge is used. This should greatly increase the time between pixel data fetches from SDRAM, as the usable fifo size is much larger. However, it probably won't help for fifo underflows, as the low threshols is kept the same. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:18:11 +00:00
*fifo_low = ovl_fifo_size - burst_size * 2;
*fifo_high = total_fifo_size - burst_size;
OMAPDSS: DISPC: Configure writeback FIFOs Extend the DISPC fifo functions to also configure the writeback FIFO thresholds. The most optimal configuration for writeback is to push out data to the interconnect the moment writeback pushes enough pixels in the FIFO to form a burst. This reduces the chance of writeback overflowing it's FIFO. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-10 12:01:39 +00:00
} else if (plane == OMAP_DSS_WB) {
/*
* Most optimal configuration for writeback is to push out data
* to the interconnect the moment writeback pushes enough pixels
* in the FIFO to form a burst
*/
*fifo_low = 0;
*fifo_high = burst_size;
OMAPDSS: DISPC: Add naive threshold calc for fifomerge Take fifo merge into use by implementing a rather naive fifo merge threshold calculation: keep the low threshold always the same, but increase the high threshold when fifo merge is used. This should greatly increase the time between pixel data fetches from SDRAM, as the usable fifo size is much larger. However, it probably won't help for fifo underflows, as the low threshols is kept the same. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:18:11 +00:00
} else {
*fifo_low = ovl_fifo_size - burst_size;
*fifo_high = total_fifo_size - buf_unit;
}
OMAPDSS: DISPC: move fifo threhold calc to dispc.c Move fifo threshold calculation into dispc.c, as the thresholds are really dispc internal thing. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:17:01 +00:00
}
OMAPDSS: fix missing EXPORT_SYMBOL()s Functions dispc_ovl_set_fifo_threshold and dispc_ovl_compute_fifo_thresholds need to be exported. Add the EXPORT_SYMBOLs. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-11-08 08:07:20 +00:00
EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
OMAPDSS: DISPC: move fifo threhold calc to dispc.c Move fifo threshold calculation into dispc.c, as the thresholds are really dispc internal thing. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-13 11:17:01 +00:00
OMAPDSS: Add support for MFLAG OMAP5 has support for MFLAG feature, which allows DSS to dynamically increase the priority of DISPC's DMA traffic. At the moment we don't have support for it. It was noticed that on DRA7 with high bandwidth use cases we see FIFO underflows. Implementing MFLAG support removed those underflows. Interestingly, on OMAP5 uEVM no such overflows were seen. This patch adds a simple MFLAG implementation, where we use a fixed MFLAG threshold value based on the FIFO size. The thresholds are set to 4/8 of fifo size for low threshold, and 5/8 of fifo size for high threshold. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-09-29 20:46:18 +00:00
static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
{
int bit;
if (plane == OMAP_DSS_GFX)
bit = 14;
else
bit = 23;
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
}
static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
int low, int high)
{
dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
}
static void dispc_init_mflag(void)
{
int i;
OMAPDSS: workaround for MFLAG + NV12 issue It was found that having two displays enabled and having an NV12 overlay on one of the displays will cause underflows/synclosts. Debugging this pointed to some issue with MFLAG. It is unclear why this issue is happening, but it looks like there is a HW bug related to MFLAG and FIFO management. Disabling MFLAG makes this issue go away, but then we lose the benefit of MFLAG. Also forcing MFLAG always on makes the issue go away. Also, using certain values for MFLAG_START, MFLAG thresholds and PRELOAD makes the issue go away, but there was no obvious logic to which values work and which don't. As a workaround until more information about this is found, force MFLAG always on to make NV12 usable. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-11-19 10:50:16 +00:00
/*
* HACK: NV12 color format and MFLAG seem to have problems working
* together: using two displays, and having an NV12 overlay on one of
* the displays will cause underflows/synclosts when MFLAG_CTRL=2.
* Changing MFLAG thresholds and PRELOAD to certain values seem to
* remove the errors, but there doesn't seem to be a clear logic on
* which values work and which not.
*
* As a work-around, set force MFLAG to always on.
*/
OMAPDSS: Add support for MFLAG OMAP5 has support for MFLAG feature, which allows DSS to dynamically increase the priority of DISPC's DMA traffic. At the moment we don't have support for it. It was noticed that on DRA7 with high bandwidth use cases we see FIFO underflows. Implementing MFLAG support removed those underflows. Interestingly, on OMAP5 uEVM no such overflows were seen. This patch adds a simple MFLAG implementation, where we use a fixed MFLAG threshold value based on the FIFO size. The thresholds are set to 4/8 of fifo size for low threshold, and 5/8 of fifo size for high threshold. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-09-29 20:46:18 +00:00
dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
OMAPDSS: workaround for MFLAG + NV12 issue It was found that having two displays enabled and having an NV12 overlay on one of the displays will cause underflows/synclosts. Debugging this pointed to some issue with MFLAG. It is unclear why this issue is happening, but it looks like there is a HW bug related to MFLAG and FIFO management. Disabling MFLAG makes this issue go away, but then we lose the benefit of MFLAG. Also forcing MFLAG always on makes the issue go away. Also, using certain values for MFLAG_START, MFLAG thresholds and PRELOAD makes the issue go away, but there was no obvious logic to which values work and which don't. As a workaround until more information about this is found, force MFLAG always on to make NV12 usable. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-11-19 10:50:16 +00:00
(1 << 0) | /* MFLAG_CTRL = force always on */
OMAPDSS: Add support for MFLAG OMAP5 has support for MFLAG feature, which allows DSS to dynamically increase the priority of DISPC's DMA traffic. At the moment we don't have support for it. It was noticed that on DRA7 with high bandwidth use cases we see FIFO underflows. Implementing MFLAG support removed those underflows. Interestingly, on OMAP5 uEVM no such overflows were seen. This patch adds a simple MFLAG implementation, where we use a fixed MFLAG threshold value based on the FIFO size. The thresholds are set to 4/8 of fifo size for low threshold, and 5/8 of fifo size for high threshold. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-09-29 20:46:18 +00:00
(0 << 2)); /* MFLAG_START = disable */
for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
u32 size = dispc_ovl_get_fifo_size(i);
u32 unit = dss_feat_get_buffer_size_unit();
u32 low, high;
dispc_ovl_set_mflag(i, true);
/*
* Simulation team suggests below thesholds:
* HT = fifosize * 5 / 8;
* LT = fifosize * 4 / 8;
*/
low = size * 4 / 8 / unit;
high = size * 5 / 8 / unit;
dispc_ovl_set_mflag_threshold(i, low, high);
}
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_fir(enum omap_plane plane,
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
int hinc, int vinc,
enum omap_color_component color_comp)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
u32 val;
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
u8 hinc_start, hinc_end, vinc_start, vinc_end;
OMAP: DSS2: Use dss_features framework on DSS2 code Calls init functions of dss_features during dss_probe, and the following features are made omapxxxx independent: - number of managers, overlays - supported color modes for each overlay - supported displays for each manager - global aplha, and restriction of global alpha for video1 pipeline - The register field ranges : FIRHINC, FIRVINC, FIFOHIGHTHRESHOLD FIFOLOWTHRESHOLD and FIFOSIZE Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-09-15 13:50:00 +00:00
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
dss_feat_get_reg_field(FEAT_REG_FIRHINC,
&hinc_start, &hinc_end);
dss_feat_get_reg_field(FEAT_REG_FIRVINC,
&vinc_start, &vinc_end);
val = FLD_VAL(vinc, vinc_start, vinc_end) |
FLD_VAL(hinc, hinc_start, hinc_end);
OMAP: DSS2: Use dss_features framework on DSS2 code Calls init functions of dss_features during dss_probe, and the following features are made omapxxxx independent: - number of managers, overlays - supported color modes for each overlay - supported displays for each manager - global aplha, and restriction of global alpha for video1 pipeline - The register field ranges : FIRHINC, FIRVINC, FIFOHIGHTHRESHOLD FIFOLOWTHRESHOLD and FIFOSIZE Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-09-15 13:50:00 +00:00
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
dispc_write_reg(DISPC_OVL_FIR(plane), val);
} else {
val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
dispc_write_reg(DISPC_OVL_FIR2(plane), val);
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
u32 val;
OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 05:49:50 +00:00
u8 hor_start, hor_end, vert_start, vert_end;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 05:49:50 +00:00
dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
val = FLD_VAL(vaccu, vert_start, vert_end) |
FLD_VAL(haccu, hor_start, hor_end);
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
u32 val;
OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 05:49:50 +00:00
u8 hor_start, hor_end, vert_start, vert_end;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 05:49:50 +00:00
dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
val = FLD_VAL(vaccu, vert_start, vert_end) |
FLD_VAL(haccu, hor_start, hor_end);
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
int vaccu)
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
{
u32 val;
val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
int vaccu)
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
{
u32 val;
val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_scale_param(enum omap_plane plane,
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
u16 orig_width, u16 orig_height,
u16 out_width, u16 out_height,
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
bool five_taps, u8 rotation,
enum omap_color_component color_comp)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
int fir_hinc, fir_vinc;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Ensure non-zero FIR values are configured FIR values can never be zero as per TRM, and the current code writes zero when scaling is not used. It was not causing any problem as scaling was disabled when zero was written. Its still safer to not write zero to it in any case. Now we configure correct FIR values even when scaling is not used (i.e. set FIR to 1024 when scaling is not used), but the scaling enable bits are still kept off if the scaling is not needed. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:51 +00:00
fir_hinc = 1024 * orig_width / out_width;
fir_vinc = 1024 * orig_height / out_height;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Update Fir Coefficients The FIR coefficients present in kernel are being updated to new coefficients consisting of 24 coefficient tables, with 12 each for 3 tap and 5 tap scenario, which are chosen on the basis of DISPC up/downsampling filters M value. M is the inverse of low pass cut off frequency of the sampling filter. For vertical scaling 3 tap or 5 tap tables are used based on the clock rate and width of the line buffer whereas in OMAP2 3 tap is always used. For horizontal scaling however 5 tap tables are always used. New coefficients and the corresponding logic have been tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical scaling worked fine except for some 3 tap vs 5 tap issue during vertical upscaling and clock failing issues which is acknowledged in the next patch. Vertical upscaling was found to perform better under 5 taps. The 24 coefficient tables have been moved to another file dispc_coefs.c for proper maintainance. This code is written based on code written by Lajos Molnar <lajos@ti.com> in Android Kernel for scaling. Lajos Molnar <lajos@ti.com> had fine tuned the FIR coefficient selection process and reduced outliness and blockiness around images when upscaling more than 2 times. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-12-19 08:33:44 +00:00
dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
color_comp);
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
}
OMAPDSS: DISPC: Update Accumulator configuration for chroma plane DISPC has two accumulator registers DISPC_VIDp_ACCU_0 and DISPC_VIDp_ACCU_1 each with horizontal and vertical bit fields. The bit fields can take values in the range of -1024 to 1023. Based on bit field values DISPC decides on which one out of 8 phases the filtering starts. DISPC_VIDp_ACCU_0 is used for progressive output and for interlaced output both DISPC_VIDp_ACCU_0 and DISPC_VIDp_ACCU_1 are used. The current accumulator values in DISPC scaling logic for chroma plane takes default values for all color modes and rotation types. So, the horizontal and vertical up and downsampling accumulator bit field values have been updated for better performance. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-15 06:52:34 +00:00
static void dispc_ovl_set_accu_uv(enum omap_plane plane,
u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
bool ilace, enum omap_color_mode color_mode, u8 rotation)
{
int h_accu2_0, h_accu2_1;
int v_accu2_0, v_accu2_1;
int chroma_hinc, chroma_vinc;
int idx;
struct accu {
s8 h0_m, h0_n;
s8 h1_m, h1_n;
s8 v0_m, v0_n;
s8 v1_m, v1_n;
};
const struct accu *accu_table;
const struct accu *accu_val;
static const struct accu accu_nv12[4] = {
{ 0, 1, 0, 1 , -1, 2, 0, 1 },
{ 1, 2, -3, 4 , 0, 1, 0, 1 },
{ -1, 1, 0, 1 , -1, 2, 0, 1 },
{ -1, 2, -1, 2 , -1, 1, 0, 1 },
};
static const struct accu accu_nv12_ilace[4] = {
{ 0, 1, 0, 1 , -3, 4, -1, 4 },
{ -1, 4, -3, 4 , 0, 1, 0, 1 },
{ -1, 1, 0, 1 , -1, 4, -3, 4 },
{ -3, 4, -3, 4 , -1, 1, 0, 1 },
};
static const struct accu accu_yuv[4] = {
{ 0, 1, 0, 1, 0, 1, 0, 1 },
{ 0, 1, 0, 1, 0, 1, 0, 1 },
{ -1, 1, 0, 1, 0, 1, 0, 1 },
{ 0, 1, 0, 1, -1, 1, 0, 1 },
};
switch (rotation) {
case OMAP_DSS_ROT_0:
idx = 0;
break;
case OMAP_DSS_ROT_90:
idx = 1;
break;
case OMAP_DSS_ROT_180:
idx = 2;
break;
case OMAP_DSS_ROT_270:
idx = 3;
break;
default:
BUG();
OMAPDSS: remove compiler warnings when CONFIG_BUG=n If CONFIG_BUG is not enabled, BUG() does not stop the execution. Many places in code expect the execution to stop, and this causes compiler warnings about uninitialized variables and returning from a non-void function without a return value. This patch fixes the warnings by initializing the variables and returning properly after BUG() lines. However, the behaviour is still undefined after the BUG, but this is the choice the user makes when using CONFIG_BUG=n. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 08:47:02 +00:00
return;
OMAPDSS: DISPC: Update Accumulator configuration for chroma plane DISPC has two accumulator registers DISPC_VIDp_ACCU_0 and DISPC_VIDp_ACCU_1 each with horizontal and vertical bit fields. The bit fields can take values in the range of -1024 to 1023. Based on bit field values DISPC decides on which one out of 8 phases the filtering starts. DISPC_VIDp_ACCU_0 is used for progressive output and for interlaced output both DISPC_VIDp_ACCU_0 and DISPC_VIDp_ACCU_1 are used. The current accumulator values in DISPC scaling logic for chroma plane takes default values for all color modes and rotation types. So, the horizontal and vertical up and downsampling accumulator bit field values have been updated for better performance. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-15 06:52:34 +00:00
}
switch (color_mode) {
case OMAP_DSS_COLOR_NV12:
if (ilace)
accu_table = accu_nv12_ilace;
else
accu_table = accu_nv12;
break;
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
accu_table = accu_yuv;
break;
default:
BUG();
OMAPDSS: remove compiler warnings when CONFIG_BUG=n If CONFIG_BUG is not enabled, BUG() does not stop the execution. Many places in code expect the execution to stop, and this causes compiler warnings about uninitialized variables and returning from a non-void function without a return value. This patch fixes the warnings by initializing the variables and returning properly after BUG() lines. However, the behaviour is still undefined after the BUG, but this is the choice the user makes when using CONFIG_BUG=n. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 08:47:02 +00:00
return;
OMAPDSS: DISPC: Update Accumulator configuration for chroma plane DISPC has two accumulator registers DISPC_VIDp_ACCU_0 and DISPC_VIDp_ACCU_1 each with horizontal and vertical bit fields. The bit fields can take values in the range of -1024 to 1023. Based on bit field values DISPC decides on which one out of 8 phases the filtering starts. DISPC_VIDp_ACCU_0 is used for progressive output and for interlaced output both DISPC_VIDp_ACCU_0 and DISPC_VIDp_ACCU_1 are used. The current accumulator values in DISPC scaling logic for chroma plane takes default values for all color modes and rotation types. So, the horizontal and vertical up and downsampling accumulator bit field values have been updated for better performance. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-15 06:52:34 +00:00
}
accu_val = &accu_table[idx];
chroma_hinc = 1024 * orig_width / out_width;
chroma_vinc = 1024 * orig_height / out_height;
h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_scaling_common(enum omap_plane plane,
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
u16 orig_width, u16 orig_height,
u16 out_width, u16 out_height,
bool ilace, bool five_taps,
bool fieldmode, enum omap_color_mode color_mode,
u8 rotation)
{
int accu0 = 0;
int accu1 = 0;
u32 l;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
dispc_ovl_set_scale_param(plane, orig_width, orig_height,
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
out_width, out_height, five_taps,
rotation, DISPC_COLOR_COMPONENT_RGB_Y);
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 05:49:50 +00:00
/* RESIZEENABLE and VERTICALTAPS */
l &= ~((0x3 << 5) | (0x1 << 21));
OMAP: DSS2: Ensure non-zero FIR values are configured FIR values can never be zero as per TRM, and the current code writes zero when scaling is not used. It was not causing any problem as scaling was disabled when zero was written. Its still safer to not write zero to it in any case. Now we configure correct FIR values even when scaling is not used (i.e. set FIR to 1024 when scaling is not used), but the scaling enable bits are still kept off if the scaling is not needed. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:51 +00:00
l |= (orig_width != out_width) ? (1 << 5) : 0;
l |= (orig_height != out_height) ? (1 << 6) : 0;
OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 05:49:50 +00:00
l |= five_taps ? (1 << 21) : 0;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 05:49:50 +00:00
/* VRESIZECONF and HRESIZECONF */
if (dss_has_feature(FEAT_RESIZECONF)) {
l &= ~(0x3 << 7);
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
l |= (orig_width <= out_width) ? 0 : (1 << 7);
l |= (orig_height <= out_height) ? 0 : (1 << 8);
OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 05:49:50 +00:00
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 05:49:50 +00:00
/* LINEBUFFERSPLIT */
if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
l &= ~(0x1 << 22);
l |= five_taps ? (1 << 22) : 0;
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
/*
* field 0 = even field = bottom field
* field 1 = odd field = top field
*/
if (ilace && !fieldmode) {
accu1 = 0;
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
if (accu0 >= 1024/2) {
accu1 = 1024/2;
accu0 -= accu1;
}
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
dispc_ovl_set_vid_accu0(plane, 0, accu0);
dispc_ovl_set_vid_accu1(plane, 0, accu1);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
u16 orig_width, u16 orig_height,
u16 out_width, u16 out_height,
bool ilace, bool five_taps,
bool fieldmode, enum omap_color_mode color_mode,
u8 rotation)
{
int scale_x = out_width != orig_width;
int scale_y = out_height != orig_height;
OMAPDSS: DISPC: Downscale chroma if plane is writeback When converting YUYV444 content to YUV422 or NV12 formats through writeback pipeline, the scaler needs to downscale the chroma plane. Ensure that chroma is downscaled when the pipeline is writeback. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-24 05:41:14 +00:00
bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
return;
if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
color_mode != OMAP_DSS_COLOR_UYVY &&
color_mode != OMAP_DSS_COLOR_NV12)) {
/* reset chroma resampling for RGB formats */
OMAPDSS: DISPC: Don't set chroma resampling bit for writeback The bit YUVCHROMARESAMPLING isn't there for writeback in DISPC_WB_ATTRIBUTES2. It isn't there because we don't upsample chroma like for video pipelines, we downsample chroma in writeback to get YUV422 or NV12 formats from the YUV444 input. Ignore this bit in dispc_ovl_set_scaling_uv() if the plane is OMAP_DSS_WB. Signed-off-by: Archit Taneja <archit@ti.com>
2012-07-16 11:07:45 +00:00
if (plane != OMAP_DSS_WB)
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
return;
}
OMAPDSS: DISPC: fix usage of dispc_ovl_set_accu_uv Commit 05dd0f5308213e169b02458a7f3a61362e581e14 ("OMAPDSS: DISPC: Update Accumulator configuration for chroma plane") adds dispc_ovl_set_accu_uv() function that sets the accu, but the function only handles YUV and NV12 modes, and BUGs otherwise. The patch also adds a call to the function, but unfortunately the place of call was such that the mode could be other than YUV or NV12, thus crashing the driver. This patchs moves the call to a slightly later spot, at which point only YUV and NV12 modes are handled. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Chandrabhanu Mahapatra <cmahapatra@ti.com>
2012-05-15 12:54:15 +00:00
dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
out_height, ilace, color_mode, rotation);
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
switch (color_mode) {
case OMAP_DSS_COLOR_NV12:
OMAPDSS: DISPC: Allow both upscaling and downscaling of chroma In the function dispc_plane_set_scaling_uv(), create a parameter which tells if we want to upscale or downscale the chroma plane. Downscaling of chroma is required by writeback pipeline for converting the input YUV444 color format to YUV422 or NV12. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-22 11:34:48 +00:00
if (chroma_upscale) {
/* UV is subsampled by 2 horizontally and vertically */
orig_height >>= 1;
orig_width >>= 1;
} else {
/* UV is downsampled by 2 horizontally and vertically */
orig_height <<= 1;
orig_width <<= 1;
}
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
break;
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
OMAPDSS: DISPC: Allow both upscaling and downscaling of chroma In the function dispc_plane_set_scaling_uv(), create a parameter which tells if we want to upscale or downscale the chroma plane. Downscaling of chroma is required by writeback pipeline for converting the input YUV444 color format to YUV422 or NV12. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-22 11:34:48 +00:00
/* For YUV422 with 90/270 rotation, we don't upsample chroma */
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
if (rotation == OMAP_DSS_ROT_0 ||
OMAPDSS: DISPC: Allow both upscaling and downscaling of chroma In the function dispc_plane_set_scaling_uv(), create a parameter which tells if we want to upscale or downscale the chroma plane. Downscaling of chroma is required by writeback pipeline for converting the input YUV444 color format to YUV422 or NV12. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-22 11:34:48 +00:00
rotation == OMAP_DSS_ROT_180) {
if (chroma_upscale)
/* UV is subsampled by 2 horizontally */
orig_width >>= 1;
else
/* UV is downsampled by 2 horizontally */
orig_width <<= 1;
}
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
/* must use FIR for YUV422 if rotated */
if (rotation != OMAP_DSS_ROT_0)
scale_x = scale_y = true;
OMAPDSS: DISPC: Allow both upscaling and downscaling of chroma In the function dispc_plane_set_scaling_uv(), create a parameter which tells if we want to upscale or downscale the chroma plane. Downscaling of chroma is required by writeback pipeline for converting the input YUV444 color format to YUV422 or NV12. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-22 11:34:48 +00:00
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
break;
default:
BUG();
OMAPDSS: remove compiler warnings when CONFIG_BUG=n If CONFIG_BUG is not enabled, BUG() does not stop the execution. Many places in code expect the execution to stop, and this causes compiler warnings about uninitialized variables and returning from a non-void function without a return value. This patch fixes the warnings by initializing the variables and returning properly after BUG() lines. However, the behaviour is still undefined after the BUG, but this is the choice the user makes when using CONFIG_BUG=n. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 08:47:02 +00:00
return;
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
}
if (out_width != orig_width)
scale_x = true;
if (out_height != orig_height)
scale_y = true;
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
dispc_ovl_set_scale_param(plane, orig_width, orig_height,
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
out_width, out_height, five_taps,
rotation, DISPC_COLOR_COMPONENT_UV);
OMAPDSS: DISPC: Don't set chroma resampling bit for writeback The bit YUVCHROMARESAMPLING isn't there for writeback in DISPC_WB_ATTRIBUTES2. It isn't there because we don't upsample chroma like for video pipelines, we downsample chroma in writeback to get YUV422 or NV12 formats from the YUV444 input. Ignore this bit in dispc_ovl_set_scaling_uv() if the plane is OMAP_DSS_WB. Signed-off-by: Archit Taneja <archit@ti.com>
2012-07-16 11:07:45 +00:00
if (plane != OMAP_DSS_WB)
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
(scale_x || scale_y) ? 1 : 0, 8, 8);
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
/* set H scaling */
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
/* set V scaling */
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_scaling(enum omap_plane plane,
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
u16 orig_width, u16 orig_height,
u16 out_width, u16 out_height,
bool ilace, bool five_taps,
bool fieldmode, enum omap_color_mode color_mode,
u8 rotation)
{
BUG_ON(plane == OMAP_DSS_GFX);
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
dispc_ovl_set_scaling_common(plane,
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
orig_width, orig_height,
out_width, out_height,
ilace, five_taps,
fieldmode, color_mode,
rotation);
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
dispc_ovl_set_scaling_uv(plane,
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
orig_width, orig_height,
out_width, out_height,
ilace, five_taps,
fieldmode, color_mode,
rotation);
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
OMAPDSS: DISPC: Configure doublestride for NV12 when using 2D Tiler buffers When using a DISPC video pipeline to a fetch a NV12 buffer in a 2D container, we need to set set a doublestride bit in the video pipe's ATTRIBUTES register. This is needed because the stride for the UV plane(using a 16 bit Tiler container) is double the stride for the Y plane(using a 8 bit Tiler container) for the 0 or 180 degree views. The ROW_INC register is meant for the Y plane, and the HW will calculate the row increment needed for the UV plane by using double the stride value based on whether this bit is set or not. Set the bit when we are using a 2D Tiler buffer and when rotation is 0 or 180 degrees. The stride value is the same for 90 and 270 degree Tiler views, hence the bit shouldn't be set. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:24 +00:00
enum omap_dss_rotation_type rotation_type,
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
bool mirroring, enum omap_color_mode color_mode)
{
OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 05:49:50 +00:00
bool row_repeat = false;
int vidrot = 0;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY) {
if (mirroring) {
switch (rotation) {
case OMAP_DSS_ROT_0:
vidrot = 2;
break;
case OMAP_DSS_ROT_90:
vidrot = 1;
break;
case OMAP_DSS_ROT_180:
vidrot = 0;
break;
case OMAP_DSS_ROT_270:
vidrot = 3;
break;
}
} else {
switch (rotation) {
case OMAP_DSS_ROT_0:
vidrot = 0;
break;
case OMAP_DSS_ROT_90:
vidrot = 1;
break;
case OMAP_DSS_ROT_180:
vidrot = 2;
break;
case OMAP_DSS_ROT_270:
vidrot = 3;
break;
}
}
if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 05:49:50 +00:00
row_repeat = true;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
else
OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 05:49:50 +00:00
row_repeat = false;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 05:49:50 +00:00
OMAPDSS: DISPC: work-around for errata i631 Errata i631 description: "When in YUV4:2:0 format in 1D burst, the DISPC DMA skips lines when fetching Chroma sampling." Workaround: "If YUV4:2:0-1D burst is required: Set DISPC_VIDp_ATTRIBUTES[22]DOUBLESTRIDE to 0x0 and DISPC_VIDp_ATTRIBUTES[13:12]ROTATION to 0x1 or 0x3" The description is somewhat confusing, but testing has shown that DSS fetches extra rows from memory when using NV12 format in 1D mode. If the memory after the framebuffer is inaccessible, this leads to OCP errors. The driver always uses DOUBLESTRIDE=0 when using 1D mode, so we only need to handle the ROTATION part. The issue exist on all OMAP4 and OMAP5 based DSS IPs. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2015-04-09 10:51:30 +00:00
/*
* OMAP4/5 Errata i631:
* NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
* rows beyond the framebuffer, which may cause OCP error.
*/
if (color_mode == OMAP_DSS_COLOR_NV12 &&
rotation_type != OMAP_DSS_ROT_TILER)
vidrot = 1;
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
OMAP2PLUS: DSS2: FEATURES: DISPC overlay code cleanup Add dss_features and register fields to incorporate changes in DISPC pipelines between OMAP3 and OMAP4. Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF _dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 05:49:50 +00:00
if (dss_has_feature(FEAT_ROWREPEATENABLE))
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
row_repeat ? 1 : 0, 18, 18);
OMAPDSS: DISPC: Configure doublestride for NV12 when using 2D Tiler buffers When using a DISPC video pipeline to a fetch a NV12 buffer in a 2D container, we need to set set a doublestride bit in the video pipe's ATTRIBUTES register. This is needed because the stride for the UV plane(using a 16 bit Tiler container) is double the stride for the Y plane(using a 8 bit Tiler container) for the 0 or 180 degree views. The ROW_INC register is meant for the Y plane, and the HW will calculate the row increment needed for the UV plane by using double the stride value based on whether this bit is set or not. Set the bit when we are using a 2D Tiler buffer and when rotation is 0 or 180 degrees. The stride value is the same for 90 and 270 degree Tiler views, hence the bit shouldn't be set. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:24 +00:00
if (color_mode == OMAP_DSS_COLOR_NV12) {
bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
(rotation == OMAP_DSS_ROT_0 ||
rotation == OMAP_DSS_ROT_180);
/* DOUBLESTRIDE */
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
static int color_mode_to_bpp(enum omap_color_mode color_mode)
{
switch (color_mode) {
case OMAP_DSS_COLOR_CLUT1:
return 1;
case OMAP_DSS_COLOR_CLUT2:
return 2;
case OMAP_DSS_COLOR_CLUT4:
return 4;
case OMAP_DSS_COLOR_CLUT8:
OMAP: DSS2: Add new color formats for OMAP4 Add new color formats supported by OMAP4: NV12, RGBA16, RGBX16, ARGB16_1555, XRGB16_1555. NV12 color format is defined here, its support in DSS will be added separately. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:50 +00:00
case OMAP_DSS_COLOR_NV12:
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
return 8;
case OMAP_DSS_COLOR_RGB12U:
case OMAP_DSS_COLOR_RGB16:
case OMAP_DSS_COLOR_ARGB16:
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
OMAP: DSS2: Add new color formats for OMAP4 Add new color formats supported by OMAP4: NV12, RGBA16, RGBX16, ARGB16_1555, XRGB16_1555. NV12 color format is defined here, its support in DSS will be added separately. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:50 +00:00
case OMAP_DSS_COLOR_RGBA16:
case OMAP_DSS_COLOR_RGBX16:
case OMAP_DSS_COLOR_ARGB16_1555:
case OMAP_DSS_COLOR_XRGB16_1555:
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
return 16;
case OMAP_DSS_COLOR_RGB24P:
return 24;
case OMAP_DSS_COLOR_RGB24U:
case OMAP_DSS_COLOR_ARGB32:
case OMAP_DSS_COLOR_RGBA32:
case OMAP_DSS_COLOR_RGBX32:
return 32;
default:
BUG();
OMAPDSS: remove compiler warnings when CONFIG_BUG=n If CONFIG_BUG is not enabled, BUG() does not stop the execution. Many places in code expect the execution to stop, and this causes compiler warnings about uninitialized variables and returning from a non-void function without a return value. This patch fixes the warnings by initializing the variables and returning properly after BUG() lines. However, the behaviour is still undefined after the BUG, but this is the choice the user makes when using CONFIG_BUG=n. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 08:47:02 +00:00
return 0;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
}
static s32 pixinc(int pixels, u8 ps)
{
if (pixels == 1)
return 1;
else if (pixels > 1)
return 1 + (pixels - 1) * ps;
else if (pixels < 0)
return 1 - (-pixels + 1) * ps;
else
BUG();
OMAPDSS: remove compiler warnings when CONFIG_BUG=n If CONFIG_BUG is not enabled, BUG() does not stop the execution. Many places in code expect the execution to stop, and this causes compiler warnings about uninitialized variables and returning from a non-void function without a return value. This patch fixes the warnings by initializing the variables and returning properly after BUG() lines. However, the behaviour is still undefined after the BUG, but this is the choice the user makes when using CONFIG_BUG=n. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 08:47:02 +00:00
return 0;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
u16 screen_width,
u16 width, u16 height,
enum omap_color_mode color_mode, bool fieldmode,
unsigned int field_offset,
unsigned *offset0, unsigned *offset1,
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
u8 ps;
/* FIXME CLUT formats */
switch (color_mode) {
case OMAP_DSS_COLOR_CLUT1:
case OMAP_DSS_COLOR_CLUT2:
case OMAP_DSS_COLOR_CLUT4:
case OMAP_DSS_COLOR_CLUT8:
BUG();
return;
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
ps = 4;
break;
default:
ps = color_mode_to_bpp(color_mode) / 8;
break;
}
DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
width, height);
/*
* field 0 = even field = bottom field
* field 1 = odd field = top field
*/
switch (rotation + mirror * 4) {
case OMAP_DSS_ROT_0:
case OMAP_DSS_ROT_180:
/*
* If the pixel format is YUV or UYVY divide the width
* of the image by 2 for 0 and 180 degree rotation.
*/
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY)
width = width >> 1;
case OMAP_DSS_ROT_90:
case OMAP_DSS_ROT_270:
*offset1 = 0;
if (field_offset)
*offset0 = field_offset * screen_width * ps;
else
*offset0 = 0;
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
*row_inc = pixinc(1 +
(y_predecim * screen_width - x_predecim * width) +
(fieldmode ? screen_width : 0), ps);
*pix_inc = pixinc(x_predecim, ps);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
break;
case OMAP_DSS_ROT_0 + 4:
case OMAP_DSS_ROT_180 + 4:
/* If the pixel format is YUV or UYVY divide the width
* of the image by 2 for 0 degree and 180 degree
*/
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY)
width = width >> 1;
case OMAP_DSS_ROT_90 + 4:
case OMAP_DSS_ROT_270 + 4:
*offset1 = 0;
if (field_offset)
*offset0 = field_offset * screen_width * ps;
else
*offset0 = 0;
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
*row_inc = pixinc(1 -
(y_predecim * screen_width + x_predecim * width) -
(fieldmode ? screen_width : 0), ps);
*pix_inc = pixinc(x_predecim, ps);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
break;
default:
BUG();
OMAPDSS: remove compiler warnings when CONFIG_BUG=n If CONFIG_BUG is not enabled, BUG() does not stop the execution. Many places in code expect the execution to stop, and this causes compiler warnings about uninitialized variables and returning from a non-void function without a return value. This patch fixes the warnings by initializing the variables and returning properly after BUG() lines. However, the behaviour is still undefined after the BUG, but this is the choice the user makes when using CONFIG_BUG=n. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 08:47:02 +00:00
return;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
}
static void calc_dma_rotation_offset(u8 rotation, bool mirror,
u16 screen_width,
u16 width, u16 height,
enum omap_color_mode color_mode, bool fieldmode,
unsigned int field_offset,
unsigned *offset0, unsigned *offset1,
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
u8 ps;
u16 fbw, fbh;
/* FIXME CLUT formats */
switch (color_mode) {
case OMAP_DSS_COLOR_CLUT1:
case OMAP_DSS_COLOR_CLUT2:
case OMAP_DSS_COLOR_CLUT4:
case OMAP_DSS_COLOR_CLUT8:
BUG();
return;
default:
ps = color_mode_to_bpp(color_mode) / 8;
break;
}
DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
width, height);
/* width & height are overlay sizes, convert to fb sizes */
if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
fbw = width;
fbh = height;
} else {
fbw = height;
fbh = width;
}
/*
* field 0 = even field = bottom field
* field 1 = odd field = top field
*/
switch (rotation + mirror * 4) {
case OMAP_DSS_ROT_0:
*offset1 = 0;
if (field_offset)
*offset0 = *offset1 + field_offset * screen_width * ps;
else
*offset0 = *offset1;
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
*row_inc = pixinc(1 +
(y_predecim * screen_width - fbw * x_predecim) +
(fieldmode ? screen_width : 0), ps);
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY)
*pix_inc = pixinc(x_predecim, 2 * ps);
else
*pix_inc = pixinc(x_predecim, ps);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
break;
case OMAP_DSS_ROT_90:
*offset1 = screen_width * (fbh - 1) * ps;
if (field_offset)
*offset0 = *offset1 + field_offset * ps;
else
*offset0 = *offset1;
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
*row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
y_predecim + (fieldmode ? 1 : 0), ps);
*pix_inc = pixinc(-x_predecim * screen_width, ps);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
break;
case OMAP_DSS_ROT_180:
*offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
if (field_offset)
*offset0 = *offset1 - field_offset * screen_width * ps;
else
*offset0 = *offset1;
*row_inc = pixinc(-1 -
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
(y_predecim * screen_width - fbw * x_predecim) -
(fieldmode ? screen_width : 0), ps);
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY)
*pix_inc = pixinc(-x_predecim, 2 * ps);
else
*pix_inc = pixinc(-x_predecim, ps);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
break;
case OMAP_DSS_ROT_270:
*offset1 = (fbw - 1) * ps;
if (field_offset)
*offset0 = *offset1 - field_offset * ps;
else
*offset0 = *offset1;
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
*row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
y_predecim - (fieldmode ? 1 : 0), ps);
*pix_inc = pixinc(x_predecim * screen_width, ps);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
break;
/* mirroring */
case OMAP_DSS_ROT_0 + 4:
*offset1 = (fbw - 1) * ps;
if (field_offset)
*offset0 = *offset1 + field_offset * screen_width * ps;
else
*offset0 = *offset1;
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
*row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
(fieldmode ? screen_width : 0),
ps);
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY)
*pix_inc = pixinc(-x_predecim, 2 * ps);
else
*pix_inc = pixinc(-x_predecim, ps);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
break;
case OMAP_DSS_ROT_90 + 4:
*offset1 = 0;
if (field_offset)
*offset0 = *offset1 + field_offset * ps;
else
*offset0 = *offset1;
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
*row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
y_predecim + (fieldmode ? 1 : 0),
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
ps);
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
*pix_inc = pixinc(x_predecim * screen_width, ps);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
break;
case OMAP_DSS_ROT_180 + 4:
*offset1 = screen_width * (fbh - 1) * ps;
if (field_offset)
*offset0 = *offset1 - field_offset * screen_width * ps;
else
*offset0 = *offset1;
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
*row_inc = pixinc(1 - y_predecim * screen_width * 2 -
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
(fieldmode ? screen_width : 0),
ps);
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY)
*pix_inc = pixinc(x_predecim, 2 * ps);
else
*pix_inc = pixinc(x_predecim, ps);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
break;
case OMAP_DSS_ROT_270 + 4:
*offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
if (field_offset)
*offset0 = *offset1 - field_offset * ps;
else
*offset0 = *offset1;
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
*row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
y_predecim - (fieldmode ? 1 : 0),
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
ps);
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
*pix_inc = pixinc(-x_predecim * screen_width, ps);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
break;
default:
BUG();
OMAPDSS: remove compiler warnings when CONFIG_BUG=n If CONFIG_BUG is not enabled, BUG() does not stop the execution. Many places in code expect the execution to stop, and this causes compiler warnings about uninitialized variables and returning from a non-void function without a return value. This patch fixes the warnings by initializing the variables and returning properly after BUG() lines. However, the behaviour is still undefined after the BUG, but this is the choice the user makes when using CONFIG_BUG=n. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 08:47:02 +00:00
return;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
}
OMAPDSS: DISPC: Support rotation through TILER TILER is a block in OMAP4's DMM which lets DSS fetch frames in a rotated manner. Physical memory can be mapped to a portion of OMAP's system address space called TILER address space. The TILER address space is split into 8 views. Each view represents a rotated or mirrored form of the mapped physical memory. When a DISPC overlay's base address is programmed to one of these views, the TILER fetches the pixels according to the orientation of the view. A view is further split into 4 containers, each container holds elements of a particular size. Rotation can be achieved at the granularity of elements in the container. For more information on TILER, refer to the Memory Subsytem section in OMAP4 TRM. Rotation type TILER has been added which is used to exploit the capabilities of these 8 views for performing various rotations. When fetching from addresses mapped to TILER space, the DISPC DMA can fetch pixels in either 1D or 2D bursts. The fetch depends on which TILER container we are accessing. Accessing 8, 16 and 32 bit sized containers requires 2D bursts, and page mode sized containers require 1D bursts. The DSS2 user is expected to provide the Tiler address of the view that it is interested in. This is passed to the paddr and p_uv_addr parameters in omap_overlay_info. It is also expected to provide the stride value based on the view's orientation and container type, this should be passed to the screen_width parameter of omap_overlay_info. In calc_tiler_rotation_offset screen_width is used to calculate the required row_inc for DISPC. x_predecim and y_predecim are also used to calculate row_inc and pix_inc thereby adding predecimation support for TILER. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-11 13:49:55 +00:00
static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
enum omap_color_mode color_mode, bool fieldmode,
unsigned int field_offset, unsigned *offset0, unsigned *offset1,
s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
{
u8 ps;
switch (color_mode) {
case OMAP_DSS_COLOR_CLUT1:
case OMAP_DSS_COLOR_CLUT2:
case OMAP_DSS_COLOR_CLUT4:
case OMAP_DSS_COLOR_CLUT8:
BUG();
return;
default:
ps = color_mode_to_bpp(color_mode) / 8;
break;
}
DSSDBG("scrw %d, width %d\n", screen_width, width);
/*
* field 0 = even field = bottom field
* field 1 = odd field = top field
*/
*offset1 = 0;
if (field_offset)
*offset0 = *offset1 + field_offset * screen_width * ps;
else
*offset0 = *offset1;
*row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
(fieldmode ? screen_width : 0), ps);
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY)
*pix_inc = pixinc(x_predecim, 2 * ps);
else
*pix_inc = pixinc(x_predecim, ps);
}
OMAPDSS: DISPC: Handle synclost errors in OMAP3 In OMAP3 DISPC video overlays suffer from some undocumented horizontal position and timing related limitations leading to SYNCLOST errors. Whenever the image window is moved towards the right of the screen SYNCLOST errors become frequent. Checks have been implemented to see that DISPC driver rejects configuration exceeding above limitations. This code was successfully tested on OMAP3. This code is written based on code written by Ville Syrjälä <ville.syrjala@nokia.com> in Linux OMAP kernel. Ville Syrjälä <ville.syrjala@nokia.com> had added checks for video overlay horizontal timing and DISPC horizontal blanking length limitations. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:17 +00:00
/*
* This function is used to avoid synclosts in OMAP3, because of some
* undocumented horizontal position and timing related limitations.
*/
OMAPDSS: DISPC: pass pclk & lclk to check_horiz_timing_omap3 In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes check_horiz_timing_omap3() to get pclk and lclk as parameters. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:40:24 +00:00
static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
OMAPDSS: DISPC: Remove usage of dispc_mgr_get_device() The functions calc_fclk_five_taps() and check_horiz_timing_omap3() use the function dispc_mgr_get_device() to get the omap_dss_device pointer to which the manager is connected, the width of the panel is derived from that. The manager's timing is stored in it's private data in APPLY. This contains the latest timings applied to the manager. Pass these timings to dispc_ovl_setup() and use them in the above functions. Remove the function dispc_mgr_get_device() as it isn't used any more. Signed-off-by: Archit Taneja <archit@ti.com>
2012-05-08 10:23:20 +00:00
const struct omap_video_timings *t, u16 pos_x,
OMAPDSS: DISPC: Fix 34xx overlay scaling calculation commit 7faa92339bbb1e6b9a80983b206642517327eb75 OMAPDSS: DISPC: Handle synclost errors in OMAP3 introduces limits check to prevent SYNCLOST errors on OMAP3. However, it misses the logic found in Nokia kernels that is needed to correctly calculate whether 3 tap or 5 tap rescaler to be used as well as the logic to fallback to 3 taps if 5 taps clock results in too tight horizontal timings. Without that patch "horizontal timing too tight" errors are seen when a video with resolution above 640x350 is tried to be played. The patch is a forward-ported logic found in Nokia N900 and N9/50 kernels. Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-01-13 16:33:02 +00:00
u16 width, u16 height, u16 out_width, u16 out_height,
bool five_taps)
OMAPDSS: DISPC: Handle synclost errors in OMAP3 In OMAP3 DISPC video overlays suffer from some undocumented horizontal position and timing related limitations leading to SYNCLOST errors. Whenever the image window is moved towards the right of the screen SYNCLOST errors become frequent. Checks have been implemented to see that DISPC driver rejects configuration exceeding above limitations. This code was successfully tested on OMAP3. This code is written based on code written by Ville Syrjälä <ville.syrjala@nokia.com> in Linux OMAP kernel. Ville Syrjälä <ville.syrjala@nokia.com> had added checks for video overlay horizontal timing and DISPC horizontal blanking length limitations. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:17 +00:00
{
OMAPDSS: DISPC: fix DS variable name check_horiz_timing_omap3() has a variable named 'DS'. i386 uses DS name for something else, causing a compilation error. As 'DS' is not a very good local variable name in the first place, let's change it to 'ds', fixing the issue. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-05 12:40:19 +00:00
const int ds = DIV_ROUND_UP(height, out_height);
OMAPDSS: DISPC: Don't pass channel out when configuring overlays dispc_ovl_setup_common() is to be used by both overlays and writeback. We pass channel out to figure out what manager the overlay is connected to, to determine the pixel clock rate. This is used to decide the scaling limitations for that overlay. writeback doesn't have a channel out, it has a channel in field which tells where writeback gets its input from. These are 2 different fields, and this prevents us reusing the overlay configuration code for writeback. To overcome this, we now pass omap_plane to overlay related functions rather than passing channel out. We create helper functions which can derive pclk/lclk from the omap_plane id. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:28:52 +00:00
unsigned long nonactive;
OMAPDSS: DISPC: Handle synclost errors in OMAP3 In OMAP3 DISPC video overlays suffer from some undocumented horizontal position and timing related limitations leading to SYNCLOST errors. Whenever the image window is moved towards the right of the screen SYNCLOST errors become frequent. Checks have been implemented to see that DISPC driver rejects configuration exceeding above limitations. This code was successfully tested on OMAP3. This code is written based on code written by Ville Syrjälä <ville.syrjala@nokia.com> in Linux OMAP kernel. Ville Syrjälä <ville.syrjala@nokia.com> had added checks for video overlay horizontal timing and DISPC horizontal blanking length limitations. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:17 +00:00
static const u8 limits[3] = { 8, 10, 20 };
u64 val, blank;
int i;
OMAPDSS: DISPC: Remove usage of dispc_mgr_get_device() The functions calc_fclk_five_taps() and check_horiz_timing_omap3() use the function dispc_mgr_get_device() to get the omap_dss_device pointer to which the manager is connected, the width of the panel is derived from that. The manager's timing is stored in it's private data in APPLY. This contains the latest timings applied to the manager. Pass these timings to dispc_ovl_setup() and use them in the above functions. Remove the function dispc_mgr_get_device() as it isn't used any more. Signed-off-by: Archit Taneja <archit@ti.com>
2012-05-08 10:23:20 +00:00
nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
OMAPDSS: DISPC: Handle synclost errors in OMAP3 In OMAP3 DISPC video overlays suffer from some undocumented horizontal position and timing related limitations leading to SYNCLOST errors. Whenever the image window is moved towards the right of the screen SYNCLOST errors become frequent. Checks have been implemented to see that DISPC driver rejects configuration exceeding above limitations. This code was successfully tested on OMAP3. This code is written based on code written by Ville Syrjälä <ville.syrjala@nokia.com> in Linux OMAP kernel. Ville Syrjälä <ville.syrjala@nokia.com> had added checks for video overlay horizontal timing and DISPC horizontal blanking length limitations. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:17 +00:00
i = 0;
if (out_height < height)
i++;
if (out_width < width)
i++;
OMAPDSS: DISPC: Remove usage of dispc_mgr_get_device() The functions calc_fclk_five_taps() and check_horiz_timing_omap3() use the function dispc_mgr_get_device() to get the omap_dss_device pointer to which the manager is connected, the width of the panel is derived from that. The manager's timing is stored in it's private data in APPLY. This contains the latest timings applied to the manager. Pass these timings to dispc_ovl_setup() and use them in the above functions. Remove the function dispc_mgr_get_device() as it isn't used any more. Signed-off-by: Archit Taneja <archit@ti.com>
2012-05-08 10:23:20 +00:00
blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
OMAPDSS: DISPC: Handle synclost errors in OMAP3 In OMAP3 DISPC video overlays suffer from some undocumented horizontal position and timing related limitations leading to SYNCLOST errors. Whenever the image window is moved towards the right of the screen SYNCLOST errors become frequent. Checks have been implemented to see that DISPC driver rejects configuration exceeding above limitations. This code was successfully tested on OMAP3. This code is written based on code written by Ville Syrjälä <ville.syrjala@nokia.com> in Linux OMAP kernel. Ville Syrjälä <ville.syrjala@nokia.com> had added checks for video overlay horizontal timing and DISPC horizontal blanking length limitations. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:17 +00:00
DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
if (blank <= limits[i])
return -EINVAL;
OMAPDSS: DISPC: Fix 34xx overlay scaling calculation commit 7faa92339bbb1e6b9a80983b206642517327eb75 OMAPDSS: DISPC: Handle synclost errors in OMAP3 introduces limits check to prevent SYNCLOST errors on OMAP3. However, it misses the logic found in Nokia kernels that is needed to correctly calculate whether 3 tap or 5 tap rescaler to be used as well as the logic to fallback to 3 taps if 5 taps clock results in too tight horizontal timings. Without that patch "horizontal timing too tight" errors are seen when a video with resolution above 640x350 is tried to be played. The patch is a forward-ported logic found in Nokia N900 and N9/50 kernels. Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-01-13 16:33:02 +00:00
/* FIXME add checks for 3-tap filter once the limitations are known */
if (!five_taps)
return 0;
OMAPDSS: DISPC: Handle synclost errors in OMAP3 In OMAP3 DISPC video overlays suffer from some undocumented horizontal position and timing related limitations leading to SYNCLOST errors. Whenever the image window is moved towards the right of the screen SYNCLOST errors become frequent. Checks have been implemented to see that DISPC driver rejects configuration exceeding above limitations. This code was successfully tested on OMAP3. This code is written based on code written by Ville Syrjälä <ville.syrjala@nokia.com> in Linux OMAP kernel. Ville Syrjälä <ville.syrjala@nokia.com> had added checks for video overlay horizontal timing and DISPC horizontal blanking length limitations. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:17 +00:00
/*
* Pixel data should be prepared before visible display point starts.
* So, atleast DS-2 lines must have already been fetched by DISPC
* during nonactive - pos_x period.
*/
val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
OMAPDSS: DISPC: fix DS variable name check_horiz_timing_omap3() has a variable named 'DS'. i386 uses DS name for something else, causing a compilation error. As 'DS' is not a very good local variable name in the first place, let's change it to 'ds', fixing the issue. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-05 12:40:19 +00:00
val, max(0, ds - 2) * width);
if (val < max(0, ds - 2) * width)
OMAPDSS: DISPC: Handle synclost errors in OMAP3 In OMAP3 DISPC video overlays suffer from some undocumented horizontal position and timing related limitations leading to SYNCLOST errors. Whenever the image window is moved towards the right of the screen SYNCLOST errors become frequent. Checks have been implemented to see that DISPC driver rejects configuration exceeding above limitations. This code was successfully tested on OMAP3. This code is written based on code written by Ville Syrjälä <ville.syrjala@nokia.com> in Linux OMAP kernel. Ville Syrjälä <ville.syrjala@nokia.com> had added checks for video overlay horizontal timing and DISPC horizontal blanking length limitations. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:17 +00:00
return -EINVAL;
/*
* All lines need to be refilled during the nonactive period of which
* only one line can be loaded during the active period. So, atleast
* DS - 1 lines should be loaded during nonactive period.
*/
val = div_u64((u64)nonactive * lclk, pclk);
DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
OMAPDSS: DISPC: fix DS variable name check_horiz_timing_omap3() has a variable named 'DS'. i386 uses DS name for something else, causing a compilation error. As 'DS' is not a very good local variable name in the first place, let's change it to 'ds', fixing the issue. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-05 12:40:19 +00:00
val, max(0, ds - 1) * width);
if (val < max(0, ds - 1) * width)
OMAPDSS: DISPC: Handle synclost errors in OMAP3 In OMAP3 DISPC video overlays suffer from some undocumented horizontal position and timing related limitations leading to SYNCLOST errors. Whenever the image window is moved towards the right of the screen SYNCLOST errors become frequent. Checks have been implemented to see that DISPC driver rejects configuration exceeding above limitations. This code was successfully tested on OMAP3. This code is written based on code written by Ville Syrjälä <ville.syrjala@nokia.com> in Linux OMAP kernel. Ville Syrjälä <ville.syrjala@nokia.com> had added checks for video overlay horizontal timing and DISPC horizontal blanking length limitations. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:17 +00:00
return -EINVAL;
return 0;
}
OMAPDSS: DISPC: pass pclk to calc_core_clk() In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes calc_core_clk() function to get pclk as a parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:36:11 +00:00
static unsigned long calc_core_clk_five_taps(unsigned long pclk,
OMAPDSS: DISPC: Remove usage of dispc_mgr_get_device() The functions calc_fclk_five_taps() and check_horiz_timing_omap3() use the function dispc_mgr_get_device() to get the omap_dss_device pointer to which the manager is connected, the width of the panel is derived from that. The manager's timing is stored in it's private data in APPLY. This contains the latest timings applied to the manager. Pass these timings to dispc_ovl_setup() and use them in the above functions. Remove the function dispc_mgr_get_device() as it isn't used any more. Signed-off-by: Archit Taneja <archit@ti.com>
2012-05-08 10:23:20 +00:00
const struct omap_video_timings *mgr_timings, u16 width,
u16 height, u16 out_width, u16 out_height,
OMAP: DSS2: Change remaining DISPC functions for new omap_channel argument The following dispc functions are also changed to incorporate channel as an argument: -dispc_lclk_rate() -dispc_pclk_rate() -dispc_set_pol_freq() -dispc_set_clock_div() -dispc_get_clock_div() Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> [tomi.valkeinen@nokia.com: fixed trivial compile error] Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:11 +00:00
enum omap_color_mode color_mode)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: DISPC: Correct DISPC functional clock usage DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC. DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC divisor LCD. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-23 06:46:50 +00:00
u32 core_clk = 0;
OMAPDSS: DISPC: Don't pass channel out when configuring overlays dispc_ovl_setup_common() is to be used by both overlays and writeback. We pass channel out to figure out what manager the overlay is connected to, to determine the pixel clock rate. This is used to decide the scaling limitations for that overlay. writeback doesn't have a channel out, it has a channel in field which tells where writeback gets its input from. These are 2 different fields, and this prevents us reusing the overlay configuration code for writeback. To overcome this, we now pass omap_plane to overlay related functions rather than passing channel out. We create helper functions which can derive pclk/lclk from the omap_plane id. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:28:52 +00:00
u64 tmp;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Update Scaling Clock Logic Clock requirements for scaling in OMAP2, OMAP3 and OMAP4 are different. In OMAP2 and OMAP3 the required clock rate is a function of pixel clock, vertical downscale ratio and horizontal downscale ratio whereas in OMAP4 it is a function of pixel clock and horizontal downscale ratio only. Selection of 3-tap vs 5-tap coefficients depends on clock rate line buffer width in OMAP3 whereas in OMAP4 it is independent of clock rate and line buffer width. In OMAP2 3-tap for vertical and 5-tap for horizontal scaling is used. In OMAP4 5-tap is used both for horizontal and vertical scaling for better performance. Also, the number and width of line buffers differs in OMAP3 and OMAP4. So, clock functions have been fined tuned for OMAP3 and support has been added added for OMAP4. This code has been tested on OMAP2, OMAP3 and OMAP4, and scaling issues due to clock errors have been resolved. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-12-19 08:33:56 +00:00
if (height <= out_height && width <= out_width)
return (unsigned long) pclk;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
if (height > out_height) {
OMAPDSS: DISPC: Remove usage of dispc_mgr_get_device() The functions calc_fclk_five_taps() and check_horiz_timing_omap3() use the function dispc_mgr_get_device() to get the omap_dss_device pointer to which the manager is connected, the width of the panel is derived from that. The manager's timing is stored in it's private data in APPLY. This contains the latest timings applied to the manager. Pass these timings to dispc_ovl_setup() and use them in the above functions. Remove the function dispc_mgr_get_device() as it isn't used any more. Signed-off-by: Archit Taneja <archit@ti.com>
2012-05-08 10:23:20 +00:00
unsigned int ppl = mgr_timings->x_res;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
tmp = pclk * height * out_width;
do_div(tmp, 2 * out_height * ppl);
OMAPDSS: DISPC: Correct DISPC functional clock usage DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC. DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC divisor LCD. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-23 06:46:50 +00:00
core_clk = tmp;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Reject scaling settings when they cannot be supported If the scaling ratio is below 0.5 video output width can't be identical to the display width. Reject such settings. Signed-off-by: Ville Syrjälä <ville.syrjala@nokia.com> Acked-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-01-08 09:56:41 +00:00
if (height > 2 * out_height) {
if (ppl == out_width)
return 0;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
tmp = pclk * (height - 2 * out_height) * out_width;
do_div(tmp, 2 * out_height * (ppl - out_width));
OMAPDSS: DISPC: Correct DISPC functional clock usage DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC. DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC divisor LCD. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-23 06:46:50 +00:00
core_clk = max_t(u32, core_clk, tmp);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
}
if (width > out_width) {
tmp = pclk * width;
do_div(tmp, out_width);
OMAPDSS: DISPC: Correct DISPC functional clock usage DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC. DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC divisor LCD. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-23 06:46:50 +00:00
core_clk = max_t(u32, core_clk, tmp);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
if (color_mode == OMAP_DSS_COLOR_RGB24U)
OMAPDSS: DISPC: Correct DISPC functional clock usage DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC. DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC divisor LCD. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-23 06:46:50 +00:00
core_clk <<= 1;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: DISPC: Correct DISPC functional clock usage DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC. DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC divisor LCD. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-23 06:46:50 +00:00
return core_clk;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: DISPC: pass pclk to calc_core_clk() In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes calc_core_clk() function to get pclk as a parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:36:11 +00:00
static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
{
if (height > out_height && width > out_width)
return pclk * 4;
else
return pclk * 2;
}
OMAPDSS: DISPC: pass pclk to calc_core_clk() In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes calc_core_clk() function to get pclk as a parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:36:11 +00:00
static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
unsigned int hf, vf;
/*
* FIXME how to determine the 'A' factor
* for the no downscaling case ?
*/
if (width > 3 * out_width)
hf = 4;
else if (width > 2 * out_width)
hf = 3;
else if (width > out_width)
hf = 2;
else
hf = 1;
if (height > out_height)
vf = 2;
else
vf = 1;
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
return pclk * vf * hf;
}
OMAPDSS: DISPC: pass pclk to calc_core_clk() In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes calc_core_clk() function to get pclk as a parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:36:11 +00:00
static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
{
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
/*
* If the overlay/writeback is in mem to mem mode, there are no
* downscaling limitations with respect to pixel clock, return 1 as
* required core clock to represent that we have sufficient enough
* core clock to do maximum downscaling
*/
if (mem_to_mem)
return 1;
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
if (width > out_width)
return DIV_ROUND_UP(pclk, out_width) * width;
else
return pclk;
}
OMAPDSS: DISPC: pass pclk & lclk to calc_scaling In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes calc_scaling to get pclk and lclk as parameters. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:43:29 +00:00
static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
const struct omap_video_timings *mgr_timings,
u16 width, u16 height, u16 out_width, u16 out_height,
enum omap_color_mode color_mode, bool *five_taps,
int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
{
int error;
u16 in_width, in_height;
int min_factor = min(*decim_x, *decim_y);
const int maxsinglelinewidth =
dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
OMAPDSS: DISPC: Don't pass channel out when configuring overlays dispc_ovl_setup_common() is to be used by both overlays and writeback. We pass channel out to figure out what manager the overlay is connected to, to determine the pixel clock rate. This is used to decide the scaling limitations for that overlay. writeback doesn't have a channel out, it has a channel in field which tells where writeback gets its input from. These are 2 different fields, and this prevents us reusing the overlay configuration code for writeback. To overcome this, we now pass omap_plane to overlay related functions rather than passing channel out. We create helper functions which can derive pclk/lclk from the omap_plane id. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:28:52 +00:00
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
*five_taps = false;
do {
OMAPDSS: DISPC: decimation rounding fix The driver uses DIV_ROUND_UP when calculating decimated width & height. For example, when decimating with 3, the width is calculated as: width = DIV_ROUND_UP(width, decim_x); This yields bad results for some values. For example, 800/3=266.666..., which is rounded to 267. When the input width is set to 267, and pixel increment is set to 3, this causes the dispc to read a line of 801 pixels, i.e. it reads a wrong pixel at the end of the line. Even more pressing, the above rounding causes a BUG() in pixinc(), as the value of 801 is used to calculate row increment, leading to a bad value being passed to pixinc(). This patch fixes the decimation by removing the DIV_ROUND_UP()s when calculating width and height for decimation. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-01-27 09:29:53 +00:00
in_height = height / *decim_y;
in_width = width / *decim_x;
OMAPDSS: DISPC: pass pclk to calc_core_clk() In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes calc_core_clk() function to get pclk as a parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:36:11 +00:00
*core_clk = dispc.feat->calc_core_clk(pclk, in_width,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
in_height, out_width, out_height, mem_to_mem);
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
error = (in_width > maxsinglelinewidth || !*core_clk ||
*core_clk > dispc_core_clk_rate());
if (error) {
if (*decim_x == *decim_y) {
*decim_x = min_factor;
++*decim_y;
} else {
swap(*decim_x, *decim_y);
if (*decim_x < *decim_y)
++*decim_x;
}
}
} while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
if (in_width > maxsinglelinewidth) {
DSSERR("Cannot scale max input width exceeded");
return -EINVAL;
}
return 0;
}
OMAPDSS: DISPC: pass pclk & lclk to calc_scaling In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes calc_scaling to get pclk and lclk as parameters. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:43:29 +00:00
static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
const struct omap_video_timings *mgr_timings,
u16 width, u16 height, u16 out_width, u16 out_height,
enum omap_color_mode color_mode, bool *five_taps,
int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
{
int error;
u16 in_width, in_height;
int min_factor = min(*decim_x, *decim_y);
const int maxsinglelinewidth =
dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
do {
OMAPDSS: DISPC: decimation rounding fix The driver uses DIV_ROUND_UP when calculating decimated width & height. For example, when decimating with 3, the width is calculated as: width = DIV_ROUND_UP(width, decim_x); This yields bad results for some values. For example, 800/3=266.666..., which is rounded to 267. When the input width is set to 267, and pixel increment is set to 3, this causes the dispc to read a line of 801 pixels, i.e. it reads a wrong pixel at the end of the line. Even more pressing, the above rounding causes a BUG() in pixinc(), as the value of 801 is used to calculate row increment, leading to a bad value being passed to pixinc(). This patch fixes the decimation by removing the DIV_ROUND_UP()s when calculating width and height for decimation. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-01-27 09:29:53 +00:00
in_height = height / *decim_y;
in_width = width / *decim_x;
OMAPDSS: DISPC: Fix 34xx overlay scaling calculation commit 7faa92339bbb1e6b9a80983b206642517327eb75 OMAPDSS: DISPC: Handle synclost errors in OMAP3 introduces limits check to prevent SYNCLOST errors on OMAP3. However, it misses the logic found in Nokia kernels that is needed to correctly calculate whether 3 tap or 5 tap rescaler to be used as well as the logic to fallback to 3 taps if 5 taps clock results in too tight horizontal timings. Without that patch "horizontal timing too tight" errors are seen when a video with resolution above 640x350 is tried to be played. The patch is a forward-ported logic found in Nokia N900 and N9/50 kernels. Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-01-13 16:33:02 +00:00
*five_taps = in_height > out_height;
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
if (in_width > maxsinglelinewidth)
if (in_height > out_height &&
in_height < out_height * 2)
*five_taps = false;
OMAPDSS: DISPC: Fix 34xx overlay scaling calculation commit 7faa92339bbb1e6b9a80983b206642517327eb75 OMAPDSS: DISPC: Handle synclost errors in OMAP3 introduces limits check to prevent SYNCLOST errors on OMAP3. However, it misses the logic found in Nokia kernels that is needed to correctly calculate whether 3 tap or 5 tap rescaler to be used as well as the logic to fallback to 3 taps if 5 taps clock results in too tight horizontal timings. Without that patch "horizontal timing too tight" errors are seen when a video with resolution above 640x350 is tried to be played. The patch is a forward-ported logic found in Nokia N900 and N9/50 kernels. Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-01-13 16:33:02 +00:00
again:
if (*five_taps)
*core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
in_width, in_height, out_width,
out_height, color_mode);
else
OMAPDSS: DISPC: pass pclk to calc_core_clk() In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes calc_core_clk() function to get pclk as a parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:36:11 +00:00
*core_clk = dispc.feat->calc_core_clk(pclk, in_width,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
in_height, out_width, out_height,
mem_to_mem);
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
OMAPDSS: DISPC: Fix 34xx overlay scaling calculation commit 7faa92339bbb1e6b9a80983b206642517327eb75 OMAPDSS: DISPC: Handle synclost errors in OMAP3 introduces limits check to prevent SYNCLOST errors on OMAP3. However, it misses the logic found in Nokia kernels that is needed to correctly calculate whether 3 tap or 5 tap rescaler to be used as well as the logic to fallback to 3 taps if 5 taps clock results in too tight horizontal timings. Without that patch "horizontal timing too tight" errors are seen when a video with resolution above 640x350 is tried to be played. The patch is a forward-ported logic found in Nokia N900 and N9/50 kernels. Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-01-13 16:33:02 +00:00
error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
pos_x, in_width, in_height, out_width,
out_height, *five_taps);
if (error && *five_taps) {
*five_taps = false;
goto again;
}
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
error = (error || in_width > maxsinglelinewidth * 2 ||
(in_width > maxsinglelinewidth && *five_taps) ||
!*core_clk || *core_clk > dispc_core_clk_rate());
if (error) {
if (*decim_x == *decim_y) {
*decim_x = min_factor;
++*decim_y;
} else {
swap(*decim_x, *decim_y);
if (*decim_x < *decim_y)
++*decim_x;
}
}
} while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
OMAPDSS: DISPC: fix check_horiz_timing_omap3 args After calculating the required decimation for scaling, the dispc driver checks once more if the resulting configuration is valid by calling check_horiz_timing_omap3(). Earlier calls to this function have correctly used in_width and in_height as parameters, but the last call uses width and height. This causes the driver to possibly reject scaling that would work. This patch fixes the parameters. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2015-03-17 13:31:09 +00:00
if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
in_height, out_width, out_height, *five_taps)) {
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
DSSERR("horizontal timing too tight\n");
return -EINVAL;
OMAPDSS: DISPC: Update Scaling Clock Logic Clock requirements for scaling in OMAP2, OMAP3 and OMAP4 are different. In OMAP2 and OMAP3 the required clock rate is a function of pixel clock, vertical downscale ratio and horizontal downscale ratio whereas in OMAP4 it is a function of pixel clock and horizontal downscale ratio only. Selection of 3-tap vs 5-tap coefficients depends on clock rate line buffer width in OMAP3 whereas in OMAP4 it is independent of clock rate and line buffer width. In OMAP2 3-tap for vertical and 5-tap for horizontal scaling is used. In OMAP4 5-tap is used both for horizontal and vertical scaling for better performance. Also, the number and width of line buffers differs in OMAP3 and OMAP4. So, clock functions have been fined tuned for OMAP3 and support has been added added for OMAP4. This code has been tested on OMAP2, OMAP3 and OMAP4, and scaling issues due to clock errors have been resolved. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-12-19 08:33:56 +00:00
}
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
if (in_width > (maxsinglelinewidth * 2)) {
DSSERR("Cannot setup scaling");
DSSERR("width exceeds maximum width possible");
return -EINVAL;
}
if (in_width > maxsinglelinewidth && *five_taps) {
DSSERR("cannot setup scaling with five taps");
return -EINVAL;
}
return 0;
}
OMAPDSS: DISPC: pass pclk & lclk to calc_scaling In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes calc_scaling to get pclk and lclk as parameters. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:43:29 +00:00
static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
const struct omap_video_timings *mgr_timings,
u16 width, u16 height, u16 out_width, u16 out_height,
enum omap_color_mode color_mode, bool *five_taps,
int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
{
u16 in_width, in_width_max;
int decim_x_min = *decim_x;
OMAPDSS: DISPC: decimation rounding fix The driver uses DIV_ROUND_UP when calculating decimated width & height. For example, when decimating with 3, the width is calculated as: width = DIV_ROUND_UP(width, decim_x); This yields bad results for some values. For example, 800/3=266.666..., which is rounded to 267. When the input width is set to 267, and pixel increment is set to 3, this causes the dispc to read a line of 801 pixels, i.e. it reads a wrong pixel at the end of the line. Even more pressing, the above rounding causes a BUG() in pixinc(), as the value of 801 is used to calculate row increment, leading to a bad value being passed to pixinc(). This patch fixes the decimation by removing the DIV_ROUND_UP()s when calculating width and height for decimation. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-01-27 09:29:53 +00:00
u16 in_height = height / *decim_y;
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
const int maxsinglelinewidth =
dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
OMAPDSS: DISPC: Don't pass channel out when configuring overlays dispc_ovl_setup_common() is to be used by both overlays and writeback. We pass channel out to figure out what manager the overlay is connected to, to determine the pixel clock rate. This is used to decide the scaling limitations for that overlay. writeback doesn't have a channel out, it has a channel in field which tells where writeback gets its input from. These are 2 different fields, and this prevents us reusing the overlay configuration code for writeback. To overcome this, we now pass omap_plane to overlay related functions rather than passing channel out. We create helper functions which can derive pclk/lclk from the omap_plane id. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:28:52 +00:00
OMAPDSS: DISPC: Fix calc_scaling_44xx() bugs for writeback pipeline dispc_ovl_calc_scaling_44xx() doesn't work correctly for writeback. There are two issues with it: - the function tries to calculate pixel clock for the input plane using dispc_plane_pclk_rate(), calling this with writeback as input plane results in a BUG(), this function shouldn't be called for writeback at all. Fix this by calculating pixel clock only when we are not in mem to mem mode. - the maximum input_width is the product of the downscale ratio supported and the and the given output_width. This was calculated incorrectly by dividing output_width with maxdownscale. Fix this. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 06:15:02 +00:00
if (mem_to_mem) {
in_width_max = out_width * maxdownscale;
} else {
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
in_width_max = dispc_core_clk_rate() /
DIV_ROUND_UP(pclk, out_width);
OMAPDSS: DISPC: Fix calc_scaling_44xx() bugs for writeback pipeline dispc_ovl_calc_scaling_44xx() doesn't work correctly for writeback. There are two issues with it: - the function tries to calculate pixel clock for the input plane using dispc_plane_pclk_rate(), calling this with writeback as input plane results in a BUG(), this function shouldn't be called for writeback at all. Fix this by calculating pixel clock only when we are not in mem to mem mode. - the maximum input_width is the product of the downscale ratio supported and the and the given output_width. This was calculated incorrectly by dividing output_width with maxdownscale. Fix this. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 06:15:02 +00:00
}
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
*decim_x = DIV_ROUND_UP(width, in_width_max);
*decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
if (*decim_x > *x_predecim)
return -EINVAL;
do {
OMAPDSS: DISPC: decimation rounding fix The driver uses DIV_ROUND_UP when calculating decimated width & height. For example, when decimating with 3, the width is calculated as: width = DIV_ROUND_UP(width, decim_x); This yields bad results for some values. For example, 800/3=266.666..., which is rounded to 267. When the input width is set to 267, and pixel increment is set to 3, this causes the dispc to read a line of 801 pixels, i.e. it reads a wrong pixel at the end of the line. Even more pressing, the above rounding causes a BUG() in pixinc(), as the value of 801 is used to calculate row increment, leading to a bad value being passed to pixinc(). This patch fixes the decimation by removing the DIV_ROUND_UP()s when calculating width and height for decimation. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-01-27 09:29:53 +00:00
in_width = width / *decim_x;
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
} while (*decim_x <= *x_predecim &&
in_width > maxsinglelinewidth && ++*decim_x);
if (in_width > maxsinglelinewidth) {
DSSERR("Cannot scale width exceeds max line width");
return -EINVAL;
}
OMAPDSS: DISPC: pass pclk to calc_core_clk() In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes calc_core_clk() function to get pclk as a parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:36:11 +00:00
*core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
out_width, out_height, mem_to_mem);
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
return 0;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: DISPC: pass pclk & lclk to dispc_ovl_calc_scaling In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes dispc_ovl_calc_scaling to get pclk and lclk as parameters. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:46:30 +00:00
static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
OMAPDSS: DISPC: Don't pass channel out when configuring overlays dispc_ovl_setup_common() is to be used by both overlays and writeback. We pass channel out to figure out what manager the overlay is connected to, to determine the pixel clock rate. This is used to decide the scaling limitations for that overlay. writeback doesn't have a channel out, it has a channel in field which tells where writeback gets its input from. These are 2 different fields, and this prevents us reusing the overlay configuration code for writeback. To overcome this, we now pass omap_plane to overlay related functions rather than passing channel out. We create helper functions which can derive pclk/lclk from the omap_plane id. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:28:52 +00:00
enum omap_overlay_caps caps,
OMAPDSS: DISPC: Remove usage of dispc_mgr_get_device() The functions calc_fclk_five_taps() and check_horiz_timing_omap3() use the function dispc_mgr_get_device() to get the omap_dss_device pointer to which the manager is connected, the width of the panel is derived from that. The manager's timing is stored in it's private data in APPLY. This contains the latest timings applied to the manager. Pass these timings to dispc_ovl_setup() and use them in the above functions. Remove the function dispc_mgr_get_device() as it isn't used any more. Signed-off-by: Archit Taneja <archit@ti.com>
2012-05-08 10:23:20 +00:00
const struct omap_video_timings *mgr_timings,
u16 width, u16 height, u16 out_width, u16 out_height,
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
enum omap_color_mode color_mode, bool *five_taps,
OMAPDSS: DISPC: Add predecimation limit for TILER based rotations In OMAP4 and OMAP5 when TILER 2D burst mode is used, a maximum of one line can be skipped as per the respective TRMs. The MBlockStride OCP signal, which is sum of ROWINC and image width in memory, is only 17 bits wide. In 2D mode TILER supports 8192, 16384, 32768 and 65536 values of MBlockStride. In case when 2 or more lines are skipped the ROWINC value exceeds 65536 resulting in OCP errors. So, maximum vertical predecimation achievable is 2. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-24 06:38:27 +00:00
int *x_predecim, int *y_predecim, u16 pos_x,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
OMAPDSS: DISPC: Clean up scaling related clock and five tap calculations Move DISPC scaling related code from dispc_ovl_setup() to a new function dispc_ovl_calc_scaling(). Use overlay caps to check if the overlay can scale or not. No functional changes are made. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 07:45:11 +00:00
{
OMAPDSS: FEATURES: Create a range param to get max downscaling Create a dss_range_param member called FEAT_PARAM_DOWNSCALE to get the maximum downscaling possible on the current platform. Use this in dispc_ovl_calc_scaling(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 07:55:17 +00:00
const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
const int max_decim_limit = 16;
OMAPDSS: DISPC: Correct DISPC functional clock usage DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC. DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC divisor LCD. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-23 06:46:50 +00:00
unsigned long core_clk = 0;
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
int decim_x, decim_y, ret;
OMAPDSS: DISPC: Clean up scaling related clock and five tap calculations Move DISPC scaling related code from dispc_ovl_setup() to a new function dispc_ovl_calc_scaling(). Use overlay caps to check if the overlay can scale or not. No functional changes are made. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 07:45:11 +00:00
OMAPDSS: DISPC: skip scaling calculations when not scaling Current code calculates scaling factors for video overlays even when the overlays are not scaled. Change the code to skip calculations when not scaling. This optimizes the code a bit, but also fixes a problem when configuring an overlay for a disabled display: if the display is disabled we don't necessarily know the pixel clock used when the display is enabled, and in some cases (like HDMI) the pixel clock is set to zero until a proper video mode is set later. A wrong pixel clock will mess up the scaling calculations, causing an error like: omapdss DISPC error: failed to set up scaling, required fclk rate = 0 Hz, current fclk rate = 170666666 Hz A proper fix would be to check later whether the clocks are enough for the scaling, at the point when the overlay or display is actually enabled, but this patch removes the problem for now. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-01 08:50:45 +00:00
if (width == out_width && height == out_height)
return 0;
OMAPDSS: DISPC: fix div by zero issue in overlay scaling omapdrm doesn't always configure the overlays correctly, causing the overlay setup functions to be called with zero timings. This leads to division by zero error. This happens, for example, when a HDMI cable is not connected, but a user tries to setup a plane with scaling. Fixing omapdrm is a big job, so for now let's check for the bad timings in DISPC and return an error. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-03 15:14:09 +00:00
if (pclk == 0 || mgr_timings->pixelclock == 0) {
DSSERR("cannot calculate scaling settings: pclk is zero\n");
return -EINVAL;
}
OMAPDSS: DISPC: Pass overlay caps as a parameter to dispc plane functions Currently, the functions below take the omap_plane parameter and derive the overlay caps within them. Pass the overlay caps as a parameter to the function to allow these to be used by writeback too. - dispc_ovl_set_zorder() - dispc_ovl_set_pre_mult_alpha() - dispc_ovl_setup_global_alpha() - dispc_ovl_calc_scaling() - dispc_ovl_setup() These functions will be used for writeback later, and the caps will help in deciding if they are to be used for writeback or not. This allows reuse of overlay caps for writeback. Using omap_overlay_caps for writeback seems a bit incorrect, but caps is something already in use by users of OMAPDSS(omapfb/omap_vout), so we use overlay caps for overlay like features of writeback too. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:25:27 +00:00
if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
OMAPDSS: DISPC: skip scaling calculations when not scaling Current code calculates scaling factors for video overlays even when the overlays are not scaled. Change the code to skip calculations when not scaling. This optimizes the code a bit, but also fixes a problem when configuring an overlay for a disabled display: if the display is disabled we don't necessarily know the pixel clock used when the display is enabled, and in some cases (like HDMI) the pixel clock is set to zero until a proper video mode is set later. A wrong pixel clock will mess up the scaling calculations, causing an error like: omapdss DISPC error: failed to set up scaling, required fclk rate = 0 Hz, current fclk rate = 170666666 Hz A proper fix would be to check later whether the clocks are enough for the scaling, at the point when the overlay or display is actually enabled, but this patch removes the problem for now. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-01 08:50:45 +00:00
return -EINVAL;
OMAPDSS: DISPC: Clean up scaling related clock and five tap calculations Move DISPC scaling related code from dispc_ovl_setup() to a new function dispc_ovl_calc_scaling(). Use overlay caps to check if the overlay can scale or not. No functional changes are made. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 07:45:11 +00:00
OMAPDSS: DISPC: pass pclk & lclk to dispc_ovl_calc_scaling In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes dispc_ovl_calc_scaling to get pclk and lclk as parameters. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:46:30 +00:00
if (mem_to_mem) {
OMAPDSS: DISPC: Don't allow predecimation for writeback Since writeback writes to a buffer instead of reading from one, predecimation doesn't make sense for it. Configure the width and height predecimation limits to 1 if the plane is writeback. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 06:15:03 +00:00
*x_predecim = *y_predecim = 1;
} else {
*x_predecim = max_decim_limit;
*y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
dss_has_feature(FEAT_BURST_2D)) ?
2 : max_decim_limit;
}
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
color_mode == OMAP_DSS_COLOR_CLUT2 ||
color_mode == OMAP_DSS_COLOR_CLUT4 ||
color_mode == OMAP_DSS_COLOR_CLUT8) {
*x_predecim = 1;
*y_predecim = 1;
*five_taps = false;
return 0;
}
decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
if (decim_x > *x_predecim || out_width > width * 8)
OMAPDSS: DISPC: Clean up scaling related clock and five tap calculations Move DISPC scaling related code from dispc_ovl_setup() to a new function dispc_ovl_calc_scaling(). Use overlay caps to check if the overlay can scale or not. No functional changes are made. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 07:45:11 +00:00
return -EINVAL;
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
if (decim_y > *y_predecim || out_height > height * 8)
OMAPDSS: DISPC: Clean up scaling related clock and five tap calculations Move DISPC scaling related code from dispc_ovl_setup() to a new function dispc_ovl_calc_scaling(). Use overlay caps to check if the overlay can scale or not. No functional changes are made. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 07:45:11 +00:00
return -EINVAL;
OMAPDSS: DISPC: pass pclk & lclk to calc_scaling In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes calc_scaling to get pclk and lclk as parameters. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:43:29 +00:00
ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
OMAPDSS: DISPC: Don't pass channel out when configuring overlays dispc_ovl_setup_common() is to be used by both overlays and writeback. We pass channel out to figure out what manager the overlay is connected to, to determine the pixel clock rate. This is used to decide the scaling limitations for that overlay. writeback doesn't have a channel out, it has a channel in field which tells where writeback gets its input from. These are 2 different fields, and this prevents us reusing the overlay configuration code for writeback. To overcome this, we now pass omap_plane to overlay related functions rather than passing channel out. We create helper functions which can derive pclk/lclk from the omap_plane id. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:28:52 +00:00
out_width, out_height, color_mode, five_taps,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
mem_to_mem);
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
if (ret)
return ret;
OMAPDSS: DISPC: Clean up scaling related clock and five tap calculations Move DISPC scaling related code from dispc_ovl_setup() to a new function dispc_ovl_calc_scaling(). Use overlay caps to check if the overlay can scale or not. No functional changes are made. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 07:45:11 +00:00
OMAPDSS: DISPC: Correct DISPC functional clock usage DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC. DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC divisor LCD. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-23 06:46:50 +00:00
DSSDBG("required core clk rate = %lu Hz\n", core_clk);
DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
OMAPDSS: DISPC: Clean up scaling related clock and five tap calculations Move DISPC scaling related code from dispc_ovl_setup() to a new function dispc_ovl_calc_scaling(). Use overlay caps to check if the overlay can scale or not. No functional changes are made. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 07:45:11 +00:00
OMAPDSS: DISPC: Correct DISPC functional clock usage DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC. DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC divisor LCD. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-23 06:46:50 +00:00
if (!core_clk || core_clk > dispc_core_clk_rate()) {
OMAPDSS: DISPC: Clean up scaling related clock and five tap calculations Move DISPC scaling related code from dispc_ovl_setup() to a new function dispc_ovl_calc_scaling(). Use overlay caps to check if the overlay can scale or not. No functional changes are made. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 07:45:11 +00:00
DSSERR("failed to set up scaling, "
OMAPDSS: DISPC: Correct DISPC functional clock usage DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC. DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC divisor LCD. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-23 06:46:50 +00:00
"required core clk rate = %lu Hz, "
"current core clk rate = %lu Hz\n",
core_clk, dispc_core_clk_rate());
OMAPDSS: DISPC: Clean up scaling related clock and five tap calculations Move DISPC scaling related code from dispc_ovl_setup() to a new function dispc_ovl_calc_scaling(). Use overlay caps to check if the overlay can scale or not. No functional changes are made. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 07:45:11 +00:00
return -EINVAL;
}
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
*x_predecim = decim_x;
*y_predecim = decim_y;
OMAPDSS: DISPC: Clean up scaling related clock and five tap calculations Move DISPC scaling related code from dispc_ovl_setup() to a new function dispc_ovl_calc_scaling(). Use overlay caps to check if the overlay can scale or not. No functional changes are made. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 07:45:11 +00:00
return 0;
}
OMAPDSS: DISPC: add dispc_ovl_check() This patch adds a new function, dispc_ovl_check(), which can be used to verify scaling configuration for an overlay. The function gets both the overlay and overlay manager as parameters, so that the caller does not need to configure the hardware before using this function. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:57:11 +00:00
int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
const struct omap_overlay_info *oi,
const struct omap_video_timings *timings,
int *x_predecim, int *y_predecim)
{
enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
bool five_taps = true;
OMAPDSS: DISPC: Fix assignment of 0/1 to bool variables Convert 0 to false and 1 to true when assigning values to bool variables. Inspired by commit 3db1cd5c05f35fb43eb134df6f321de4e63141f2. The simplified semantic patch that find this problem is as follows (http://coccinelle.lip6.fr/): @@ bool b; @@ ( -b = 0 +b = false | -b = 1 +b = true ) Signed-off-by: Peter Senna Tschudin <peter.senna@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-09-22 18:44:11 +00:00
bool fieldmode = false;
OMAPDSS: DISPC: add dispc_ovl_check() This patch adds a new function, dispc_ovl_check(), which can be used to verify scaling configuration for an overlay. The function gets both the overlay and overlay manager as parameters, so that the caller does not need to configure the hardware before using this function. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:57:11 +00:00
u16 in_height = oi->height;
u16 in_width = oi->width;
bool ilace = timings->interlace;
u16 out_width, out_height;
int pos_x = oi->pos_x;
unsigned long pclk = dispc_mgr_pclk_rate(channel);
unsigned long lclk = dispc_mgr_lclk_rate(channel);
out_width = oi->out_width == 0 ? oi->width : oi->out_width;
out_height = oi->out_height == 0 ? oi->height : oi->out_height;
if (ilace && oi->height == out_height)
OMAPDSS: DISPC: Fix assignment of 0/1 to bool variables Convert 0 to false and 1 to true when assigning values to bool variables. Inspired by commit 3db1cd5c05f35fb43eb134df6f321de4e63141f2. The simplified semantic patch that find this problem is as follows (http://coccinelle.lip6.fr/): @@ bool b; @@ ( -b = 0 +b = false | -b = 1 +b = true ) Signed-off-by: Peter Senna Tschudin <peter.senna@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-09-22 18:44:11 +00:00
fieldmode = true;
OMAPDSS: DISPC: add dispc_ovl_check() This patch adds a new function, dispc_ovl_check(), which can be used to verify scaling configuration for an overlay. The function gets both the overlay and overlay manager as parameters, so that the caller does not need to configure the hardware before using this function. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:57:11 +00:00
if (ilace) {
if (fieldmode)
in_height /= 2;
out_height /= 2;
DSSDBG("adjusting for ilace: height %d, out_height %d\n",
in_height, out_height);
}
if (!dss_feat_color_mode_supported(plane, oi->color_mode))
return -EINVAL;
return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
in_height, out_width, out_height, oi->color_mode,
&five_taps, x_predecim, y_predecim, pos_x,
oi->rotation_type, false);
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_ovl_check);
OMAPDSS: DISPC: add dispc_ovl_check() This patch adds a new function, dispc_ovl_check(), which can be used to verify scaling configuration for an overlay. The function gets both the overlay and overlay manager as parameters, so that the caller does not need to configure the hardware before using this function. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:57:11 +00:00
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
static int dispc_ovl_setup_common(enum omap_plane plane,
OMAPDSS: DISPC: Don't pass channel out when configuring overlays dispc_ovl_setup_common() is to be used by both overlays and writeback. We pass channel out to figure out what manager the overlay is connected to, to determine the pixel clock rate. This is used to decide the scaling limitations for that overlay. writeback doesn't have a channel out, it has a channel in field which tells where writeback gets its input from. These are 2 different fields, and this prevents us reusing the overlay configuration code for writeback. To overcome this, we now pass omap_plane to overlay related functions rather than passing channel out. We create helper functions which can derive pclk/lclk from the omap_plane id. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:28:52 +00:00
enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
u16 out_width, u16 out_height, enum omap_color_mode color_mode,
u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
u8 global_alpha, enum omap_dss_rotation_type rotation_type,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
bool replication, const struct omap_video_timings *mgr_timings,
bool mem_to_mem)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: DISPC: Update Scaling Clock Logic Clock requirements for scaling in OMAP2, OMAP3 and OMAP4 are different. In OMAP2 and OMAP3 the required clock rate is a function of pixel clock, vertical downscale ratio and horizontal downscale ratio whereas in OMAP4 it is a function of pixel clock and horizontal downscale ratio only. Selection of 3-tap vs 5-tap coefficients depends on clock rate line buffer width in OMAP3 whereas in OMAP4 it is independent of clock rate and line buffer width. In OMAP2 3-tap for vertical and 5-tap for horizontal scaling is used. In OMAP4 5-tap is used both for horizontal and vertical scaling for better performance. Also, the number and width of line buffers differs in OMAP3 and OMAP4. So, clock functions have been fined tuned for OMAP3 and support has been added added for OMAP4. This code has been tested on OMAP2, OMAP3 and OMAP4, and scaling issues due to clock errors have been resolved. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-12-19 08:33:56 +00:00
bool five_taps = true;
OMAPDSS: DISPC: Fix assignment of 0/1 to bool variables Convert 0 to false and 1 to true when assigning values to bool variables. Inspired by commit 3db1cd5c05f35fb43eb134df6f321de4e63141f2. The simplified semantic patch that find this problem is as follows (http://coccinelle.lip6.fr/): @@ bool b; @@ ( -b = 0 +b = false | -b = 1 +b = true ) Signed-off-by: Peter Senna Tschudin <peter.senna@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-09-22 18:44:11 +00:00
bool fieldmode = false;
OMAPDSS: DISPC: Clean up scaling related clock and five tap calculations Move DISPC scaling related code from dispc_ovl_setup() to a new function dispc_ovl_calc_scaling(). Use overlay caps to check if the overlay can scale or not. No functional changes are made. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 07:45:11 +00:00
int r, cconv = 0;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
unsigned offset0, offset1;
s32 row_inc;
s32 pix_inc;
OMAPDSS: DISPC: Use output width and height to calculate row/pix inc for writeback When calculating row and pixel increments for graphics and video pipes, we need to consider the dimensions of the input frame to know how to read from the buffer. Hence, we need to calculate these parameters from the input to the pipeline. For writeback, the row and pixel increments need to be calculated based on the output of the writeback pipeline, i.e, the dimensions of the frame after scaling. Ensure that dispc driver uses values of out_width and out_height when calling calc_dma/calc_tiler_rotation_offset. For graphics and video pipes, the original code passed the original height as frame_height to calc_dma_rotation_offset, and not the predecimated height. This is left as it is for now. We need to figure out why pre decimated height isn't needed. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 06:15:04 +00:00
u16 frame_width, frame_height;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
unsigned int field_offset = 0;
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
u16 in_height = height;
u16 in_width = width;
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
int x_predecim = 1, y_predecim = 1;
OMAPDSS: DISPC/APPLY: Use interlace info in manager timings for dispc_ovl_setup() Currently the interlace parameter passed to dispc_ovl_setup() is configured by checking the display type, and set to true if the display type is VENC. This isn't correct as other panels can take interlaced content too. The omap_video_timings struct in manager's private data contains the info whether the panel is in interlaced mode or not. Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-06 10:55:52 +00:00
bool ilace = mgr_timings->interlace;
OMAPDSS: DISPC: pass pclk & lclk to dispc_ovl_calc_scaling In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes dispc_ovl_calc_scaling to get pclk and lclk as parameters. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:46:30 +00:00
unsigned long pclk = dispc_plane_pclk_rate(plane);
unsigned long lclk = dispc_plane_lclk_rate(plane);
OMAP: DSS2: DISPC: remove finegrained clk enables/disables dispc.c enables and disables clocks in almost every function to make sure the clocks are enabled when the function is called. This is rather unoptimal way to handle the problem. With pm_runtime other components have to call dispc_runtime_get() to enable dispc clocks before calling any other dispc functions. Thus the finegrained clk enables/disables can be removed. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 11:12:26 +00:00
OMAPDSS: fix paddr check for TILER addresses The DISPC driver checks that the buffer address is not 0. However, when using TILER, the address space is TILER specific and 0 is a valid address. Fix the check to allow address of 0 for TILER. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reported-by: srinivas pulukuru <srinivas.pulukuru@ti.com>
2014-11-28 12:34:15 +00:00
if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
return -EINVAL;
OMAPDSS: DISPC: fix predecimation for YUV modes DISPC needs even input buffer width for YUV modes. The DISPC driver doesn't check this at the moment (although omapdrm does), but worse, when DISPC driver does x predecimation the result may be uneven. This causes sometimes sync losts, underflows, or just visual errors. This patch makes DISPC driver return an error if the user gives uneven input width for a YUV buffer. It also makes the input width even in case of predecimation. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2015-02-27 11:07:58 +00:00
switch (color_mode) {
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
case OMAP_DSS_COLOR_NV12:
if (in_width & 1) {
DSSERR("input width %d is not even for YUV format\n",
in_width);
return -EINVAL;
}
break;
default:
break;
}
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
out_width = out_width == 0 ? width : out_width;
out_height = out_height == 0 ? height : out_height;
OMAPDSS: DISPC: handle 0 out_width/out_height in ovl_setup() Overlay out_width/height are set to 0 when scaling is not used by the users of omapdss. Currently ovl_setup() expects the caller of ovl_setup() to convert those zero values to width or height. This patch makes ovl_setup() accept zero values for out_width/height, making calling ovl_setup() a bit simpler as the overlay_info can be just passed to this function without modifications. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-03 14:08:27 +00:00
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
if (ilace && height == out_height)
OMAPDSS: DISPC: Fix assignment of 0/1 to bool variables Convert 0 to false and 1 to true when assigning values to bool variables. Inspired by commit 3db1cd5c05f35fb43eb134df6f321de4e63141f2. The simplified semantic patch that find this problem is as follows (http://coccinelle.lip6.fr/): @@ bool b; @@ ( -b = 0 +b = false | -b = 1 +b = true ) Signed-off-by: Peter Senna Tschudin <peter.senna@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-09-22 18:44:11 +00:00
fieldmode = true;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
if (ilace) {
if (fieldmode)
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
in_height /= 2;
OMAPDSS: DISPC: Constify omap_overlay_info in dispc_ovl_setup() The struct omap_overlay_info passed to dispc_ovl_setup() is used to configure DISPC registers. It shouldn't modify the overlay_info structure. The pos_y field was being changed in dispc_ovl_setup in the case of interlaced displays. Fix this and const qualifier to the omap_overlay_info argument. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-22 07:03:49 +00:00
pos_y /= 2;
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
out_height /= 2;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
DSSDBG("adjusting for ilace: height %d, pos_y %d, "
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
"out_height %d\n", in_height, pos_y,
out_height);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
if (!dss_feat_color_mode_supported(plane, color_mode))
OMAP: DSS2: Clean up DISPC color mode validation checks The supported set of color modes varies for different DISPC pipelines(plane) and omap version. This makes the checks for validation of a color mode more complicated as new omap versions are added. A dss_feature function is created which tells if a color_mode is supported for a plane on the current omap revision. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-11-25 12:28:10 +00:00
return -EINVAL;
OMAPDSS: DISPC: pass pclk & lclk to dispc_ovl_calc_scaling In order to make the scaling calculations independent of the current hardware configuration (e.g. which manager is connected to this output), we need to change the calc funcs to get all the variables needed for the calculations via parameters. This patch changes dispc_ovl_calc_scaling to get pclk and lclk as parameters. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 12:46:30 +00:00
r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
in_height, out_width, out_height, color_mode,
&five_taps, &x_predecim, &y_predecim, pos_x,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
rotation_type, mem_to_mem);
OMAPDSS: DISPC: Clean up scaling related clock and five tap calculations Move DISPC scaling related code from dispc_ovl_setup() to a new function dispc_ovl_calc_scaling(). Use overlay caps to check if the overlay can scale or not. No functional changes are made. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 07:45:11 +00:00
if (r)
return r;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: decimation rounding fix The driver uses DIV_ROUND_UP when calculating decimated width & height. For example, when decimating with 3, the width is calculated as: width = DIV_ROUND_UP(width, decim_x); This yields bad results for some values. For example, 800/3=266.666..., which is rounded to 267. When the input width is set to 267, and pixel increment is set to 3, this causes the dispc to read a line of 801 pixels, i.e. it reads a wrong pixel at the end of the line. Even more pressing, the above rounding causes a BUG() in pixinc(), as the value of 801 is used to calculate row increment, leading to a bad value being passed to pixinc(). This patch fixes the decimation by removing the DIV_ROUND_UP()s when calculating width and height for decimation. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-01-27 09:29:53 +00:00
in_width = in_width / x_predecim;
in_height = in_height / y_predecim;
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
OMAPDSS: DISPC: fix predecimation for YUV modes DISPC needs even input buffer width for YUV modes. The DISPC driver doesn't check this at the moment (although omapdrm does), but worse, when DISPC driver does x predecimation the result may be uneven. This causes sometimes sync losts, underflows, or just visual errors. This patch makes DISPC driver return an error if the user gives uneven input width for a YUV buffer. It also makes the input width even in case of predecimation. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2015-02-27 11:07:58 +00:00
if (x_predecim > 1 || y_predecim > 1)
DSSDBG("predecimation %d x %x, new input size %d x %d\n",
x_predecim, y_predecim, in_width, in_height);
switch (color_mode) {
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
case OMAP_DSS_COLOR_NV12:
if (in_width & 1) {
DSSDBG("predecimated input width is not even for YUV format\n");
DSSDBG("adjusting input width %d -> %d\n",
in_width, in_width & ~1);
in_width &= ~1;
}
break;
default:
break;
}
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY ||
color_mode == OMAP_DSS_COLOR_NV12)
OMAPDSS: DISPC: Clean up scaling related clock and five tap calculations Move DISPC scaling related code from dispc_ovl_setup() to a new function dispc_ovl_calc_scaling(). Use overlay caps to check if the overlay can scale or not. No functional changes are made. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 07:45:11 +00:00
cconv = 1;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
if (ilace && !fieldmode) {
/*
* when downscaling the bottom field may have to start several
* source lines below the top field. Unfortunately ACCUI
* registers will only hold the fractional part of the offset
* so the integer part must be added to the base address of the
* bottom field.
*/
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
if (!in_height || in_height == out_height)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
field_offset = 0;
else
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
field_offset = in_height / out_height / 2;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
/* Fields are independent but interleaved in memory. */
if (fieldmode)
field_offset = 1;
OMAPDSS: remove compiler warnings when CONFIG_BUG=n If CONFIG_BUG is not enabled, BUG() does not stop the execution. Many places in code expect the execution to stop, and this causes compiler warnings about uninitialized variables and returning from a non-void function without a return value. This patch fixes the warnings by initializing the variables and returning properly after BUG() lines. However, the behaviour is still undefined after the BUG, but this is the choice the user makes when using CONFIG_BUG=n. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 08:47:02 +00:00
offset0 = 0;
offset1 = 0;
row_inc = 0;
pix_inc = 0;
OMAPDSS: DISPC: Use output width and height to calculate row/pix inc for writeback When calculating row and pixel increments for graphics and video pipes, we need to consider the dimensions of the input frame to know how to read from the buffer. Hence, we need to calculate these parameters from the input to the pipeline. For writeback, the row and pixel increments need to be calculated based on the output of the writeback pipeline, i.e, the dimensions of the frame after scaling. Ensure that dispc driver uses values of out_width and out_height when calling calc_dma/calc_tiler_rotation_offset. For graphics and video pipes, the original code passed the original height as frame_height to calc_dma_rotation_offset, and not the predecimated height. This is left as it is for now. We need to figure out why pre decimated height isn't needed. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 06:15:04 +00:00
if (plane == OMAP_DSS_WB) {
frame_width = out_width;
frame_height = out_height;
} else {
frame_width = in_width;
frame_height = height;
}
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
if (rotation_type == OMAP_DSS_ROT_TILER)
OMAPDSS: DISPC: Use output width and height to calculate row/pix inc for writeback When calculating row and pixel increments for graphics and video pipes, we need to consider the dimensions of the input frame to know how to read from the buffer. Hence, we need to calculate these parameters from the input to the pipeline. For writeback, the row and pixel increments need to be calculated based on the output of the writeback pipeline, i.e, the dimensions of the frame after scaling. Ensure that dispc driver uses values of out_width and out_height when calling calc_dma/calc_tiler_rotation_offset. For graphics and video pipes, the original code passed the original height as frame_height to calc_dma_rotation_offset, and not the predecimated height. This is left as it is for now. We need to figure out why pre decimated height isn't needed. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 06:15:04 +00:00
calc_tiler_rotation_offset(screen_width, frame_width,
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
color_mode, fieldmode, field_offset,
OMAPDSS: DISPC: Support rotation through TILER TILER is a block in OMAP4's DMM which lets DSS fetch frames in a rotated manner. Physical memory can be mapped to a portion of OMAP's system address space called TILER address space. The TILER address space is split into 8 views. Each view represents a rotated or mirrored form of the mapped physical memory. When a DISPC overlay's base address is programmed to one of these views, the TILER fetches the pixels according to the orientation of the view. A view is further split into 4 containers, each container holds elements of a particular size. Rotation can be achieved at the granularity of elements in the container. For more information on TILER, refer to the Memory Subsytem section in OMAP4 TRM. Rotation type TILER has been added which is used to exploit the capabilities of these 8 views for performing various rotations. When fetching from addresses mapped to TILER space, the DISPC DMA can fetch pixels in either 1D or 2D bursts. The fetch depends on which TILER container we are accessing. Accessing 8, 16 and 32 bit sized containers requires 2D bursts, and page mode sized containers require 1D bursts. The DSS2 user is expected to provide the Tiler address of the view that it is interested in. This is passed to the paddr and p_uv_addr parameters in omap_overlay_info. It is also expected to provide the stride value based on the view's orientation and container type, this should be passed to the screen_width parameter of omap_overlay_info. In calc_tiler_rotation_offset screen_width is used to calculate the required row_inc for DISPC. x_predecim and y_predecim are also used to calculate row_inc and pix_inc thereby adding predecimation support for TILER. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-11 13:49:55 +00:00
&offset0, &offset1, &row_inc, &pix_inc,
x_predecim, y_predecim);
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
else if (rotation_type == OMAP_DSS_ROT_DMA)
OMAPDSS: DISPC: Use output width and height to calculate row/pix inc for writeback When calculating row and pixel increments for graphics and video pipes, we need to consider the dimensions of the input frame to know how to read from the buffer. Hence, we need to calculate these parameters from the input to the pipeline. For writeback, the row and pixel increments need to be calculated based on the output of the writeback pipeline, i.e, the dimensions of the frame after scaling. Ensure that dispc driver uses values of out_width and out_height when calling calc_dma/calc_tiler_rotation_offset. For graphics and video pipes, the original code passed the original height as frame_height to calc_dma_rotation_offset, and not the predecimated height. This is left as it is for now. We need to figure out why pre decimated height isn't needed. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 06:15:04 +00:00
calc_dma_rotation_offset(rotation, mirror, screen_width,
frame_width, frame_height,
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
color_mode, fieldmode, field_offset,
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
&offset0, &offset1, &row_inc, &pix_inc,
x_predecim, y_predecim);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
else
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
calc_vrfb_rotation_offset(rotation, mirror,
OMAPDSS: DISPC: Use output width and height to calculate row/pix inc for writeback When calculating row and pixel increments for graphics and video pipes, we need to consider the dimensions of the input frame to know how to read from the buffer. Hence, we need to calculate these parameters from the input to the pipeline. For writeback, the row and pixel increments need to be calculated based on the output of the writeback pipeline, i.e, the dimensions of the frame after scaling. Ensure that dispc driver uses values of out_width and out_height when calling calc_dma/calc_tiler_rotation_offset. For graphics and video pipes, the original code passed the original height as frame_height to calc_dma_rotation_offset, and not the predecimated height. This is left as it is for now. We need to figure out why pre decimated height isn't needed. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 06:15:04 +00:00
screen_width, frame_width, frame_height,
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
color_mode, fieldmode, field_offset,
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
&offset0, &offset1, &row_inc, &pix_inc,
x_predecim, y_predecim);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
offset0, offset1, row_inc, pix_inc);
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
dispc_ovl_set_color_mode(plane, color_mode);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
dispc_ovl_configure_burst_type(plane, rotation_type);
OMAPDSS: DISPC: Support rotation through TILER TILER is a block in OMAP4's DMM which lets DSS fetch frames in a rotated manner. Physical memory can be mapped to a portion of OMAP's system address space called TILER address space. The TILER address space is split into 8 views. Each view represents a rotated or mirrored form of the mapped physical memory. When a DISPC overlay's base address is programmed to one of these views, the TILER fetches the pixels according to the orientation of the view. A view is further split into 4 containers, each container holds elements of a particular size. Rotation can be achieved at the granularity of elements in the container. For more information on TILER, refer to the Memory Subsytem section in OMAP4 TRM. Rotation type TILER has been added which is used to exploit the capabilities of these 8 views for performing various rotations. When fetching from addresses mapped to TILER space, the DISPC DMA can fetch pixels in either 1D or 2D bursts. The fetch depends on which TILER container we are accessing. Accessing 8, 16 and 32 bit sized containers requires 2D bursts, and page mode sized containers require 1D bursts. The DSS2 user is expected to provide the Tiler address of the view that it is interested in. This is passed to the paddr and p_uv_addr parameters in omap_overlay_info. It is also expected to provide the stride value based on the view's orientation and container type, this should be passed to the screen_width parameter of omap_overlay_info. In calc_tiler_rotation_offset screen_width is used to calculate the required row_inc for DISPC. x_predecim and y_predecim are also used to calculate row_inc and pix_inc thereby adding predecimation support for TILER. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-11 13:49:55 +00:00
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
dispc_ovl_set_ba0(plane, paddr + offset0);
dispc_ovl_set_ba1(plane, paddr + offset1);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
if (OMAP_DSS_COLOR_NV12 == color_mode) {
dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
OMAP: DSS2: Add support for NV12 format Add the support for NV12 color format. Configure base address for UV component of NV12 color format. Change the way chroma scaling is handled for YUV formats on OMAP4 by enabling chroma-resampling for video pipeline and hence using FIR2 register set for scaling UV. Changes to _dispc_set_scaling(), because of the reason above, are: - call _dispc_set_scaling_common() to handle scaling for all color formats except for OMAP4 where it only handles scaling for RGB or Y-component - call _dispc_set_scaling_uv() for special handling required for UV component on OMAP4. - dispc_set_scaling_uv() also resets chroma-resampling bit for RGB color modes. Contains chroma scaling (_dispc_set_scaling_uv) design and implemented by Lajos Molnar <molnar@ti.com> Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:54 +00:00
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
dispc_ovl_set_row_inc(plane, row_inc);
dispc_ovl_set_pix_inc(plane, pix_inc);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
in_height, out_width, out_height);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Simplify function names for setting pipeline input and output sizes The DISPC pipeline register names in the TRM for setting the buffer size and the output size are a bit misleading, for example, there are different register names for setting the buffer size for VID and GFX pipes. Things get more confusing when considering writeback pipeline. Rename the functions so that they tell whether they are configuring the input to the scalar or the output. These will be extended later to support writeback registers. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-21 09:21:49 +00:00
dispc_ovl_set_input_size(plane, in_width, in_height);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Pass overlay caps as a parameter to dispc plane functions Currently, the functions below take the omap_plane parameter and derive the overlay caps within them. Pass the overlay caps as a parameter to the function to allow these to be used by writeback too. - dispc_ovl_set_zorder() - dispc_ovl_set_pre_mult_alpha() - dispc_ovl_setup_global_alpha() - dispc_ovl_calc_scaling() - dispc_ovl_setup() These functions will be used for writeback later, and the caps will help in deciding if they are to be used for writeback or not. This allows reuse of overlay caps for writeback. Using omap_overlay_caps for writeback seems a bit incorrect, but caps is something already in use by users of OMAPDSS(omapfb/omap_vout), so we use overlay caps for overlay like features of writeback too. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:25:27 +00:00
if (caps & OMAP_DSS_OVL_CAP_SCALE) {
OMAPDSS: DISPC: Enable predecimation In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and up to 2 times in OMAP2. However, with predecimation, the image can be reduced to 16 times by fetching only the necessary pixels in memory. Then this predecimated image can be downscaled further by the DISPC scaler. The pipeline is configured to use a burst of size 8 * 128 bits which consists of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16 can lead to complete discarding of such mini bursts. L3 interconnect may handover the bus to some other initiator and inturn delay the fetching of pixels leading to underflows. So, maximum predecimation limit is fixed at 16. Based on the downscaling required, a prior calculation of predecimation values for width and height of an image is done. Since, Predecimation reduces quality of an image higher priorty is given to DISPC Scaler for downscaling. This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical predecimation worked fine except for some synclost errors due to undocumented errata in OMAP3 which are fixed later and skewed images were seen on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in the future patches. This code is based on code written by Lajos Molnar <lajos@ti.com> who had added predecimation support for NV12/YUV/rotated/SDMA buffers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-02 15:13:16 +00:00
dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
out_height, ilace, five_taps, fieldmode,
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
color_mode, rotation);
OMAPDSS: DISPC: Simplify function names for setting pipeline input and output sizes The DISPC pipeline register names in the TRM for setting the buffer size and the output size are a bit misleading, for example, there are different register names for setting the buffer size for VID and GFX pipes. Things get more confusing when considering writeback pipeline. Rename the functions so that they tell whether they are configuring the input to the scalar or the output. These will be extended later to support writeback registers. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-21 09:21:49 +00:00
dispc_ovl_set_output_size(plane, out_width, out_height);
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
dispc_ovl_set_vid_color_conv(plane, cconv);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: DISPC: Configure doublestride for NV12 when using 2D Tiler buffers When using a DISPC video pipeline to a fetch a NV12 buffer in a 2D container, we need to set set a doublestride bit in the video pipe's ATTRIBUTES register. This is needed because the stride for the UV plane(using a 16 bit Tiler container) is double the stride for the Y plane(using a 8 bit Tiler container) for the 0 or 180 degree views. The ROW_INC register is meant for the Y plane, and the HW will calculate the row increment needed for the UV plane by using double the stride value based on whether this bit is set or not. Set the bit when we are using a 2D Tiler buffer and when rotation is 0 or 180 degrees. The stride value is the same for 90 and 270 degree Tiler views, hence the bit shouldn't be set. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:24 +00:00
dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
color_mode);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
dispc_ovl_set_zorder(plane, caps, zorder);
dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: OVERLAY: Add position and replication as overlay caps Add position and replication as overlay caps, and pass overlay caps as an argument to the corresponding functions. Adding position and replication to overlay caps seems a bit unnecessary, but it allows us to use the corresponding functions for writeback too. These caps will be set for all overlays, but not for writeback. This is done so writeback can reuse dispc_ovl_setup() to the maximum. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-22 07:00:17 +00:00
dispc_ovl_enable_replication(plane, caps, replication);
OMAPDSS: DISPC: Pass overlay params as arguments to dispc_ovl_setup() dispc_ovl_enable_replication() and dispc_ovl_set_fifo_threshold() are currently called in configure_overlay(). These are the only functions which cause DISPC register writes of overlay parameters outside of dispc_ovl_setup(). Move these to dispc_ovl_setup() and pass replication, fifo_low and fifo_high thresholds as arguments to dispc_ovl_setup() in order to be aligned with other overlay parameters. No functional changes are made. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-14 06:22:54 +00:00
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
return 0;
}
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
bool replication, const struct omap_video_timings *mgr_timings,
bool mem_to_mem)
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
{
int r;
OMAPDSS: DISPC: remove struct omap_overlay use dispc_ovl_setup() uses struct omap_overlay to get the caps for the overlay. We can change the code to get the caps directly from dss features, thus removing the dependency to struct omap_overlay. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-15 12:33:22 +00:00
enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
enum omap_channel channel;
channel = dispc_ovl_get_channel_out(plane);
video: omap2dss: fix LPAE warnings If LPAE is enabled, dma_addr_t is 64 bit, so we have to change a few type for everything in this driver to match again. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: linux-fbdev@vger.kernel.org Cc: linux-omap@vger.kernel.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-24 12:28:18 +00:00
DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
" %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
oi->color_mode, oi->rotation, oi->mirror, channel, replication);
OMAPDSS: DISPC: remove struct omap_overlay use dispc_ovl_setup() uses struct omap_overlay to get the caps for the overlay. We can change the code to get the caps directly from dss features, thus removing the dependency to struct omap_overlay. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-15 12:33:22 +00:00
r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
OMAPDSS: DISPC: Don't pass channel out when configuring overlays dispc_ovl_setup_common() is to be used by both overlays and writeback. We pass channel out to figure out what manager the overlay is connected to, to determine the pixel clock rate. This is used to decide the scaling limitations for that overlay. writeback doesn't have a channel out, it has a channel in field which tells where writeback gets its input from. These are 2 different fields, and this prevents us reusing the overlay configuration code for writeback. To overcome this, we now pass omap_plane to overlay related functions rather than passing channel out. We create helper functions which can derive pclk/lclk from the omap_plane id. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:28:52 +00:00
oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
OMAPDSS: DIPSC: Relax scaling limitations when in memory to memory mode The scalers of overlays and writeback do not have any constraints on downscale ratio when operating in memory to memory mode. This is because in memory to memory mode, we aren't connected to a display which needs data output at the rate of pixel clock. The scalers can perform as much downscaling as needed, the rate at which the scaler outputs is adjusted accordingly. Relax constraints related to downscaling based on whether the input overlays are connected to writeback in memory to memory mode. We pass a mem_to_mem boolean parameter to dispc_ovl_setup() from APPLY. This is currently set to false, this will later be configured to the correct value based on whether the overlay is connected to writeback or not. Do the same later for writeback when writeback is configured. In the scaling calculation code, we calculate the minimum amount of core clock we need to achieve the required downscaling. If we are in memory to memory mode, we set this to a very small value(1 in this case), this value would always be lesser than the actual DISPC core clock value, and hence the scaling checks would succeed. We take care that pixel clock isn't calculated for writeback and the overlays connected to it when in memory to memory mode. A pixel clock in such cases doesn't make sense. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:30:37 +00:00
oi->rotation_type, replication, mgr_timings, mem_to_mem);
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
return r;
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_ovl_setup);
OMAPDSS: DISPC: Make dispc_ovl_setup call dispc_ovl_setup_common Add a new static function called dispc_ovl_setup_common(). This function is used by dispc_ovl_setup() to configure the overlay registers. This split is done so that dispc_wb_setup() can reuse overlay register configuration related code. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:27:37 +00:00
OMAPDSS: DISPC: Configure overlay-like parameters in dispc_wb_setup Create struct omap_dss_writeback_info, this is similar to omap_overlay_info, the major difference is that there is no parameter which describes the input size to writeback, this is because this is always fixed, and decided by the connected overlay or overlay manager. One more difference is that screen_width is renamed to buf_width, to give the value of stride the writeback buffer has. Call dispc_ovl_setup_common() through dispc_wb_setup() to configure overlay-like parameters. The parameters in dispc_ovl_setup_common() which do not hold for writeback are filled passed as zeroes or false, the code takes care of not configuring them as they won't possess the needed overlay caps. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-31 07:02:52 +00:00
int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
OMAPDSS: DISPC: Configure writeback specific parameters in dispc_wb_setup() Configure some of the writeback specific parameters in dispc_wb_setup(). The writeback parameters configured are: truncation: This needs to be set if the color depth input to writeback is more than the color depth of the color mode we want to store in memory. writeback mode: This configures whether we want to use writeback in mem to mem or capture mode. This information will be directly passed by APPLY later. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-24 11:29:26 +00:00
bool mem_to_mem, const struct omap_video_timings *mgr_timings)
OMAPDSS: DISPC: Configure overlay-like parameters in dispc_wb_setup Create struct omap_dss_writeback_info, this is similar to omap_overlay_info, the major difference is that there is no parameter which describes the input size to writeback, this is because this is always fixed, and decided by the connected overlay or overlay manager. One more difference is that screen_width is renamed to buf_width, to give the value of stride the writeback buffer has. Call dispc_ovl_setup_common() through dispc_wb_setup() to configure overlay-like parameters. The parameters in dispc_ovl_setup_common() which do not hold for writeback are filled passed as zeroes or false, the code takes care of not configuring them as they won't possess the needed overlay caps. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-31 07:02:52 +00:00
{
int r;
OMAPDSS: DISPC: Configure writeback specific parameters in dispc_wb_setup() Configure some of the writeback specific parameters in dispc_wb_setup(). The writeback parameters configured are: truncation: This needs to be set if the color depth input to writeback is more than the color depth of the color mode we want to store in memory. writeback mode: This configures whether we want to use writeback in mem to mem or capture mode. This information will be directly passed by APPLY later. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-24 11:29:26 +00:00
u32 l;
OMAPDSS: DISPC: Configure overlay-like parameters in dispc_wb_setup Create struct omap_dss_writeback_info, this is similar to omap_overlay_info, the major difference is that there is no parameter which describes the input size to writeback, this is because this is always fixed, and decided by the connected overlay or overlay manager. One more difference is that screen_width is renamed to buf_width, to give the value of stride the writeback buffer has. Call dispc_ovl_setup_common() through dispc_wb_setup() to configure overlay-like parameters. The parameters in dispc_ovl_setup_common() which do not hold for writeback are filled passed as zeroes or false, the code takes care of not configuring them as they won't possess the needed overlay caps. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-31 07:02:52 +00:00
enum omap_plane plane = OMAP_DSS_WB;
const int pos_x = 0, pos_y = 0;
const u8 zorder = 0, global_alpha = 0;
const bool replication = false;
OMAPDSS: DISPC: Configure writeback specific parameters in dispc_wb_setup() Configure some of the writeback specific parameters in dispc_wb_setup(). The writeback parameters configured are: truncation: This needs to be set if the color depth input to writeback is more than the color depth of the color mode we want to store in memory. writeback mode: This configures whether we want to use writeback in mem to mem or capture mode. This information will be directly passed by APPLY later. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-24 11:29:26 +00:00
bool truncation;
OMAPDSS: DISPC: Configure overlay-like parameters in dispc_wb_setup Create struct omap_dss_writeback_info, this is similar to omap_overlay_info, the major difference is that there is no parameter which describes the input size to writeback, this is because this is always fixed, and decided by the connected overlay or overlay manager. One more difference is that screen_width is renamed to buf_width, to give the value of stride the writeback buffer has. Call dispc_ovl_setup_common() through dispc_wb_setup() to configure overlay-like parameters. The parameters in dispc_ovl_setup_common() which do not hold for writeback are filled passed as zeroes or false, the code takes care of not configuring them as they won't possess the needed overlay caps. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-31 07:02:52 +00:00
int in_width = mgr_timings->x_res;
int in_height = mgr_timings->y_res;
enum omap_overlay_caps caps =
OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
"rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
wi->mirror);
r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
wi->pre_mult_alpha, global_alpha, wi->rotation_type,
OMAPDSS: DISPC: Configure writeback specific parameters in dispc_wb_setup() Configure some of the writeback specific parameters in dispc_wb_setup(). The writeback parameters configured are: truncation: This needs to be set if the color depth input to writeback is more than the color depth of the color mode we want to store in memory. writeback mode: This configures whether we want to use writeback in mem to mem or capture mode. This information will be directly passed by APPLY later. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-24 11:29:26 +00:00
replication, mgr_timings, mem_to_mem);
switch (wi->color_mode) {
case OMAP_DSS_COLOR_RGB16:
case OMAP_DSS_COLOR_RGB24P:
case OMAP_DSS_COLOR_ARGB16:
case OMAP_DSS_COLOR_RGBA16:
case OMAP_DSS_COLOR_RGB12U:
case OMAP_DSS_COLOR_ARGB16_1555:
case OMAP_DSS_COLOR_XRGB16_1555:
case OMAP_DSS_COLOR_RGBX16:
truncation = true;
break;
default:
truncation = false;
break;
}
/* setup extra DISPC_WB_ATTRIBUTES */
l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
OMAPDSS: DISPC: Configure overlay-like parameters in dispc_wb_setup Create struct omap_dss_writeback_info, this is similar to omap_overlay_info, the major difference is that there is no parameter which describes the input size to writeback, this is because this is always fixed, and decided by the connected overlay or overlay manager. One more difference is that screen_width is renamed to buf_width, to give the value of stride the writeback buffer has. Call dispc_ovl_setup_common() through dispc_wb_setup() to configure overlay-like parameters. The parameters in dispc_ovl_setup_common() which do not hold for writeback are filled passed as zeroes or false, the code takes care of not configuring them as they won't possess the needed overlay caps. Signed-off-by: Archit Taneja <archit@ti.com>
2012-08-31 07:02:52 +00:00
return r;
}
OMAP: DSS2: DISPC: rename overlay related funcs Rename dispc's overlay related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_ovl_* - Remove "plane" from the name, e.g. dispc_set_plane_ba0 -> dispc_ovl_set_ba0 The idea is to group overlay related functions so that it can be deduced from the function name that it writes to overlay spesific registers. All dispc_ovl_* functions have enum omap_plane as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:25:00 +00:00
int dispc_ovl_enable(enum omap_plane plane, bool enable)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: DISPC: remove finegrained clk enables/disables dispc.c enables and disables clocks in almost every function to make sure the clocks are enabled when the function is called. This is rather unoptimal way to handle the problem. With pm_runtime other components have to call dispc_runtime_get() to enable dispc clocks before calling any other dispc functions. Thus the finegrained clk enables/disables can be removed. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 11:12:26 +00:00
DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
OMAP: DSS2: DISPC: remove finegrained clk enables/disables dispc.c enables and disables clocks in almost every function to make sure the clocks are enabled when the function is called. This is rather unoptimal way to handle the problem. With pm_runtime other components have to call dispc_runtime_get() to enable dispc clocks before calling any other dispc functions. Thus the finegrained clk enables/disables can be removed. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 11:12:26 +00:00
return 0;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_ovl_enable);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: add dispc_ovl_enabled() Add new dispc function, dispc_ovl_enabled(). This returns if the overlay enable bit is set in the registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 11:13:15 +00:00
bool dispc_ovl_enabled(enum omap_plane plane)
{
return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_ovl_enabled);
OMAPDSS: add dispc_ovl_enabled() Add new dispc function, dispc_ovl_enabled(). This returns if the overlay enable bit is set in the registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 11:13:15 +00:00
OMAPDSS: DISPC: make _enable_mgr_out public as "dispc_mgr_enable" We need a low level manager-enable function for omapdrm. We have that function as dispc internal func, _enable_mgr_out(). This patch exposes that function, and renames it to dispc_mgr_enable(). Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-19 11:16:06 +00:00
void dispc_mgr_enable(enum omap_channel channel, bool enable)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
/* flush posted write */
mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_mgr_enable);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: cleanup lcd and digit enable dispc.c's functions to enable LCD and DIGIT outputs can be cleaned up a bit by using common functions to set the enable bit and to check if the output is enabled. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 08:44:17 +00:00
bool dispc_mgr_is_enabled(enum omap_channel channel)
{
return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_mgr_is_enabled);
OMAPDSS: DISPC: cleanup lcd and digit enable dispc.c's functions to enable LCD and DIGIT outputs can be cleaned up a bit by using common functions to set the enable bit and to check if the output is enabled. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 08:44:17 +00:00
OMAPDSS: DISPC: Add manager like functions for writeback Add functions to enable writeback, and set/check state of GO bit. These bits are identical in behaviour with the corresponding overlay manager bits. Configure them in a similar way to mgr_enable() and mgr_go_* functions. Add a helper to get the FRAMEDONE irq corresponding to writeback. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-22 07:09:33 +00:00
void dispc_wb_enable(bool enable)
{
OMAPDSS: cleanup WB enable/is_enabled functions Instead of doing direct register reads/writes, dispc_wb_enable() and dispc_wb_is_enabled() functions can use the common overlay functions to set and check the enable bit. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 11:13:26 +00:00
dispc_ovl_enable(OMAP_DSS_WB, enable);
OMAPDSS: DISPC: Add manager like functions for writeback Add functions to enable writeback, and set/check state of GO bit. These bits are identical in behaviour with the corresponding overlay manager bits. Configure them in a similar way to mgr_enable() and mgr_go_* functions. Add a helper to get the FRAMEDONE irq corresponding to writeback. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-22 07:09:33 +00:00
}
bool dispc_wb_is_enabled(void)
{
OMAPDSS: cleanup WB enable/is_enabled functions Instead of doing direct register reads/writes, dispc_wb_enable() and dispc_wb_is_enabled() functions can use the common overlay functions to set and check the enable bit. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 11:13:26 +00:00
return dispc_ovl_enabled(OMAP_DSS_WB);
OMAPDSS: DISPC: Add manager like functions for writeback Add functions to enable writeback, and set/check state of GO bit. These bits are identical in behaviour with the corresponding overlay manager bits. Configure them in a similar way to mgr_enable() and mgr_go_* functions. Add a helper to get the FRAMEDONE irq corresponding to writeback. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-22 07:09:33 +00:00
}
OMAPDSS: combine LCD related config into one func Dispc has a bunch of functions used to configure output related parameters: - dispc_mgr_set_io_pad_mode - dispc_mgr_enable_stallmode - dispc_mgr_enable_fifohandcheck - dispc_mgr_set_clock_div - dispc_mgr_set_tft_data_lines - dispc_lcd_enable_signal_polarity - dispc_mgr_set_lcd_type_tft These are all called together, and the configuration values are taken from struct dss_lcd_mgr_config. Instead of exposing those individual dispc functions, create a new one, dispc_mgr_set_lcd_config(), which is used to configure the above parameters from values in struct dss_lcd_mgr_config. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-12 10:30:39 +00:00
static void dispc_lcd_enable_signal_polarity(bool act_high)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: Use dss_features to handle DISPC bits removed on OMAP4 DISPC_CONFIG bits LCDENABLEPOL, LCDENABLESIGNAL, PCKFREEENABLE and FUNCGATED have been removed from OMAP4, use dss_features to handle them correctly. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:13 +00:00
if (!dss_has_feature(FEAT_LCDENABLEPOL))
return;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
}
void dispc_lcd_enable_signal(bool enable)
{
OMAP: DSS2: Use dss_features to handle DISPC bits removed on OMAP4 DISPC_CONFIG bits LCDENABLEPOL, LCDENABLESIGNAL, PCKFREEENABLE and FUNCGATED have been removed from OMAP4, use dss_features to handle them correctly. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:13 +00:00
if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
return;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
}
void dispc_pck_free_enable(bool enable)
{
OMAP: DSS2: Use dss_features to handle DISPC bits removed on OMAP4 DISPC_CONFIG bits LCDENABLEPOL, LCDENABLESIGNAL, PCKFREEENABLE and FUNCGATED have been removed from OMAP4, use dss_features to handle them correctly. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:13 +00:00
if (!dss_has_feature(FEAT_PCKFREEENABLE))
return;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
}
OMAPDSS: combine LCD related config into one func Dispc has a bunch of functions used to configure output related parameters: - dispc_mgr_set_io_pad_mode - dispc_mgr_enable_stallmode - dispc_mgr_enable_fifohandcheck - dispc_mgr_set_clock_div - dispc_mgr_set_tft_data_lines - dispc_lcd_enable_signal_polarity - dispc_mgr_set_lcd_type_tft These are all called together, and the configuration values are taken from struct dss_lcd_mgr_config. Instead of exposing those individual dispc functions, create a new one, dispc_mgr_set_lcd_config(), which is used to configure the above parameters from values in struct dss_lcd_mgr_config. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-12 10:30:39 +00:00
static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: combine LCD related config into one func Dispc has a bunch of functions used to configure output related parameters: - dispc_mgr_set_io_pad_mode - dispc_mgr_enable_stallmode - dispc_mgr_enable_fifohandcheck - dispc_mgr_set_clock_div - dispc_mgr_set_tft_data_lines - dispc_lcd_enable_signal_polarity - dispc_mgr_set_lcd_type_tft These are all called together, and the configuration values are taken from struct dss_lcd_mgr_config. Instead of exposing those individual dispc functions, create a new one, dispc_mgr_set_lcd_config(), which is used to configure the above parameters from values in struct dss_lcd_mgr_config. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-12 10:30:39 +00:00
static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: Remove passive matrix LCD support (part 3) Remove omap_lcd_display_type enum The enum omap_lcd_display_type is used to configure the lcd display type in DISPC. Remove this enum and always set display type to TFT by creating function dss_mgr_set_lcd_type_tft(). Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-21 04:15:11 +00:00
mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
void dispc_set_loadmode(enum omap_dss_load_mode mode)
{
REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
}
OMAPDSS: setup manager with dispc_mgr_setup() Change manager configuration to be similar to overlay configuration by creating dispc_mgr_setup() which takes omap_overlay_manager_info as parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-04 16:14:20 +00:00
static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: Represent DISPC register defines with channel as parameter On OMAP4, we have a new DISPC channel for Overlay Manager LCD2. There is a set of regsiters for LCD2 channel similar to the existing LCD channel, like DISPC_CONTROL2, DISPC_DIVISOR2, DISPC_CONFIG2 and so on. Introduce new enum members for LCD2 Channel and corresponding Overlay Manager in display.h. Represent the following DISPC register defines with channel as a parameter to differentiate between LCD and LCD2 registers (and also DIGIT in some cases): DISPC_DEFAULT_COLOR, DISPC_TRANS_COLOR, DISPC_TIMING_H, DISPC_TIMING_V, DISPC_POL_FREQ, DISPC_DIVISOR, DISPC_SIZE_LCD, DISPC_DATA_CYCLEk, DISPC_CPR_COEF_R, DISPC_CPR_COEF_G and DISPC_CPR_COEF_B This parametrization helps in reducing the number of register defines for DISPC. Replace the existing reads/writes to these registers in this new way. Also, Introduce defines for registers DISPC_CONTROL2 and DISPC_CONFIG2 which are used exclusively for LCD2 channel. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:09 +00:00
dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: setup manager with dispc_mgr_setup() Change manager configuration to be similar to overlay configuration by creating dispc_mgr_setup() which takes omap_overlay_manager_info as parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-04 16:14:20 +00:00
static void dispc_mgr_set_trans_key(enum omap_channel ch,
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
enum omap_dss_trans_key_type type,
u32 trans_key)
{
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Represent DISPC register defines with channel as parameter On OMAP4, we have a new DISPC channel for Overlay Manager LCD2. There is a set of regsiters for LCD2 channel similar to the existing LCD channel, like DISPC_CONTROL2, DISPC_DIVISOR2, DISPC_CONFIG2 and so on. Introduce new enum members for LCD2 Channel and corresponding Overlay Manager in display.h. Represent the following DISPC register defines with channel as a parameter to differentiate between LCD and LCD2 registers (and also DIGIT in some cases): DISPC_DEFAULT_COLOR, DISPC_TRANS_COLOR, DISPC_TIMING_H, DISPC_TIMING_V, DISPC_POL_FREQ, DISPC_DIVISOR, DISPC_SIZE_LCD, DISPC_DATA_CYCLEk, DISPC_CPR_COEF_R, DISPC_CPR_COEF_G and DISPC_CPR_COEF_B This parametrization helps in reducing the number of register defines for DISPC. Replace the existing reads/writes to these registers in this new way. Also, Introduce defines for registers DISPC_CONTROL2 and DISPC_CONFIG2 which are used exclusively for LCD2 channel. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:09 +00:00
dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: setup manager with dispc_mgr_setup() Change manager configuration to be similar to overlay configuration by creating dispc_mgr_setup() which takes omap_overlay_manager_info as parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-04 16:14:20 +00:00
static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS/OMAP_VOUT: Fix incorrect OMAP3-alpha compatibility setting On OMAP3, in order to enable alpha blending for LCD and TV managers, we needed to set LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits in DISPC_CONFIG. On OMAP4, alpha blending is always enabled by default, if the above bits are set, we switch to an OMAP3 compatibility mode where the zorder values in the pipeline attribute registers are ignored and a fixed priority is configured. Rename the manager_info member "alpha_enabled" to "partial_alpha_enabled" for more clarity. Introduce two dss_features FEAT_ALPHA_FIXED_ZORDER and FEAT_ALPHA_FREE_ZORDER which represent OMAP3-alpha compatibility mode and OMAP4 alpha mode respectively. Introduce an overlay cap for ZORDER. The DSS2 user is expected to check for the ZORDER cap, if an overlay doesn't have this cap, the user is expected to set the parameter partial_alpha_enabled. If the overlay has ZORDER cap, the DSS2 user can assume that alpha blending is already enabled. Don't support OMAP3 compatibility mode for now. Trying to read/write to alpha_blending_enabled sysfs attribute issues a warning for OMAP4 and does not set the LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits. Change alpha_enabled to partial_alpha_enabled in the omap_vout driver. Use overlay cap "OMAP_DSS_OVL_CAP_GLOBAL_ALPHA" to check if overlay supports alpha blending or not. Replace this with checks for VIDEO1 pipeline. Cc: linux-media@vger.kernel.org Cc: Lajos Molnar <molnar@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Acked-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-26 06:17:29 +00:00
OMAPDSS: setup manager with dispc_mgr_setup() Change manager configuration to be similar to overlay configuration by creating dispc_mgr_setup() which takes omap_overlay_manager_info as parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-04 16:14:20 +00:00
static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
bool enable)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS/OMAP_VOUT: Fix incorrect OMAP3-alpha compatibility setting On OMAP3, in order to enable alpha blending for LCD and TV managers, we needed to set LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits in DISPC_CONFIG. On OMAP4, alpha blending is always enabled by default, if the above bits are set, we switch to an OMAP3 compatibility mode where the zorder values in the pipeline attribute registers are ignored and a fixed priority is configured. Rename the manager_info member "alpha_enabled" to "partial_alpha_enabled" for more clarity. Introduce two dss_features FEAT_ALPHA_FIXED_ZORDER and FEAT_ALPHA_FREE_ZORDER which represent OMAP3-alpha compatibility mode and OMAP4 alpha mode respectively. Introduce an overlay cap for ZORDER. The DSS2 user is expected to check for the ZORDER cap, if an overlay doesn't have this cap, the user is expected to set the parameter partial_alpha_enabled. If the overlay has ZORDER cap, the DSS2 user can assume that alpha blending is already enabled. Don't support OMAP3 compatibility mode for now. Trying to read/write to alpha_blending_enabled sysfs attribute issues a warning for OMAP4 and does not set the LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits. Change alpha_enabled to partial_alpha_enabled in the omap_vout driver. Use overlay cap "OMAP_DSS_OVL_CAP_GLOBAL_ALPHA" to check if overlay supports alpha blending or not. Replace this with checks for VIDEO1 pipeline. Cc: linux-media@vger.kernel.org Cc: Lajos Molnar <molnar@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Acked-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-26 06:17:29 +00:00
if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
return;
if (ch == OMAP_DSS_CHANNEL_LCD)
REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
}
OMAPDSS/OMAP_VOUT: Fix incorrect OMAP3-alpha compatibility setting On OMAP3, in order to enable alpha blending for LCD and TV managers, we needed to set LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits in DISPC_CONFIG. On OMAP4, alpha blending is always enabled by default, if the above bits are set, we switch to an OMAP3 compatibility mode where the zorder values in the pipeline attribute registers are ignored and a fixed priority is configured. Rename the manager_info member "alpha_enabled" to "partial_alpha_enabled" for more clarity. Introduce two dss_features FEAT_ALPHA_FIXED_ZORDER and FEAT_ALPHA_FREE_ZORDER which represent OMAP3-alpha compatibility mode and OMAP4 alpha mode respectively. Introduce an overlay cap for ZORDER. The DSS2 user is expected to check for the ZORDER cap, if an overlay doesn't have this cap, the user is expected to set the parameter partial_alpha_enabled. If the overlay has ZORDER cap, the DSS2 user can assume that alpha blending is already enabled. Don't support OMAP3 compatibility mode for now. Trying to read/write to alpha_blending_enabled sysfs attribute issues a warning for OMAP4 and does not set the LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits. Change alpha_enabled to partial_alpha_enabled in the omap_vout driver. Use overlay cap "OMAP_DSS_OVL_CAP_GLOBAL_ALPHA" to check if overlay supports alpha blending or not. Replace this with checks for VIDEO1 pipeline. Cc: linux-media@vger.kernel.org Cc: Lajos Molnar <molnar@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Acked-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-26 06:17:29 +00:00
OMAPDSS: setup manager with dispc_mgr_setup() Change manager configuration to be similar to overlay configuration by creating dispc_mgr_setup() which takes omap_overlay_manager_info as parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-04 16:14:20 +00:00
void dispc_mgr_setup(enum omap_channel channel,
OMAPDSS: DISPC: constify function parameters Add consts to dispc function parameters which do not modify the passed structs. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-03 07:09:11 +00:00
const struct omap_overlay_manager_info *info)
OMAPDSS: setup manager with dispc_mgr_setup() Change manager configuration to be similar to overlay configuration by creating dispc_mgr_setup() which takes omap_overlay_manager_info as parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-11-04 16:14:20 +00:00
{
dispc_mgr_set_default_color(channel, info->default_color);
dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
dispc_mgr_enable_trans_key(channel, info->trans_enabled);
dispc_mgr_enable_alpha_fixed_zorder(channel,
info->partial_alpha_enabled);
if (dss_has_feature(FEAT_CPR)) {
dispc_mgr_enable_cpr(channel, info->cpr_enable);
dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
}
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_mgr_setup);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: combine LCD related config into one func Dispc has a bunch of functions used to configure output related parameters: - dispc_mgr_set_io_pad_mode - dispc_mgr_enable_stallmode - dispc_mgr_enable_fifohandcheck - dispc_mgr_set_clock_div - dispc_mgr_set_tft_data_lines - dispc_lcd_enable_signal_polarity - dispc_mgr_set_lcd_type_tft These are all called together, and the configuration values are taken from struct dss_lcd_mgr_config. Instead of exposing those individual dispc functions, create a new one, dispc_mgr_set_lcd_config(), which is used to configure the above parameters from values in struct dss_lcd_mgr_config. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-12 10:30:39 +00:00
static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
int code;
switch (data_lines) {
case 12:
code = 0;
break;
case 16:
code = 1;
break;
case 18:
code = 2;
break;
case 24:
code = 3;
break;
default:
BUG();
return;
}
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: combine LCD related config into one func Dispc has a bunch of functions used to configure output related parameters: - dispc_mgr_set_io_pad_mode - dispc_mgr_enable_stallmode - dispc_mgr_enable_fifohandcheck - dispc_mgr_set_clock_div - dispc_mgr_set_tft_data_lines - dispc_lcd_enable_signal_polarity - dispc_mgr_set_lcd_type_tft These are all called together, and the configuration values are taken from struct dss_lcd_mgr_config. Instead of exposing those individual dispc functions, create a new one, dispc_mgr_set_lcd_config(), which is used to configure the above parameters from values in struct dss_lcd_mgr_config. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-12 10:30:39 +00:00
static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
u32 l;
OMAP: DSS2: Clean up stallmode and io pad mode selection Split the function dispc_set_parallel_interface_mode() into 2 separate functions called dispc_mgr_set_io_pad_mode() and dispc_mgr_enable_stallmode(). The current function tries to set 2 different modes(io pad mode and stall mode) based on a parameter omap_parallel_interface_mode which loosely corresponds to the panel interface type. This isn't correct because a) these 2 modes are independent to some extent, b) we are currently configuring gpout0/gpout1 for DSI panels which is unnecessary, c) a DSI Video mode panel won't get configured correctly. Splitting the functions allows the interface driver to set these modes independently and hence allow more flexibility. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-22 12:11:57 +00:00
int gpout0, gpout1;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
switch (mode) {
OMAP: DSS2: Clean up stallmode and io pad mode selection Split the function dispc_set_parallel_interface_mode() into 2 separate functions called dispc_mgr_set_io_pad_mode() and dispc_mgr_enable_stallmode(). The current function tries to set 2 different modes(io pad mode and stall mode) based on a parameter omap_parallel_interface_mode which loosely corresponds to the panel interface type. This isn't correct because a) these 2 modes are independent to some extent, b) we are currently configuring gpout0/gpout1 for DSI panels which is unnecessary, c) a DSI Video mode panel won't get configured correctly. Splitting the functions allows the interface driver to set these modes independently and hence allow more flexibility. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-22 12:11:57 +00:00
case DSS_IO_PAD_MODE_RESET:
gpout0 = 0;
gpout1 = 0;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
break;
OMAP: DSS2: Clean up stallmode and io pad mode selection Split the function dispc_set_parallel_interface_mode() into 2 separate functions called dispc_mgr_set_io_pad_mode() and dispc_mgr_enable_stallmode(). The current function tries to set 2 different modes(io pad mode and stall mode) based on a parameter omap_parallel_interface_mode which loosely corresponds to the panel interface type. This isn't correct because a) these 2 modes are independent to some extent, b) we are currently configuring gpout0/gpout1 for DSI panels which is unnecessary, c) a DSI Video mode panel won't get configured correctly. Splitting the functions allows the interface driver to set these modes independently and hence allow more flexibility. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-22 12:11:57 +00:00
case DSS_IO_PAD_MODE_RFBI:
gpout0 = 1;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
gpout1 = 0;
break;
OMAP: DSS2: Clean up stallmode and io pad mode selection Split the function dispc_set_parallel_interface_mode() into 2 separate functions called dispc_mgr_set_io_pad_mode() and dispc_mgr_enable_stallmode(). The current function tries to set 2 different modes(io pad mode and stall mode) based on a parameter omap_parallel_interface_mode which loosely corresponds to the panel interface type. This isn't correct because a) these 2 modes are independent to some extent, b) we are currently configuring gpout0/gpout1 for DSI panels which is unnecessary, c) a DSI Video mode panel won't get configured correctly. Splitting the functions allows the interface driver to set these modes independently and hence allow more flexibility. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-22 12:11:57 +00:00
case DSS_IO_PAD_MODE_BYPASS:
gpout0 = 1;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
gpout1 = 1;
break;
default:
BUG();
return;
}
OMAP: DSS2: Clean up stallmode and io pad mode selection Split the function dispc_set_parallel_interface_mode() into 2 separate functions called dispc_mgr_set_io_pad_mode() and dispc_mgr_enable_stallmode(). The current function tries to set 2 different modes(io pad mode and stall mode) based on a parameter omap_parallel_interface_mode which loosely corresponds to the panel interface type. This isn't correct because a) these 2 modes are independent to some extent, b) we are currently configuring gpout0/gpout1 for DSI panels which is unnecessary, c) a DSI Video mode panel won't get configured correctly. Splitting the functions allows the interface driver to set these modes independently and hence allow more flexibility. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-22 12:11:57 +00:00
l = dispc_read_reg(DISPC_CONTROL);
l = FLD_MOD(l, gpout0, 15, 15);
l = FLD_MOD(l, gpout1, 16, 16);
dispc_write_reg(DISPC_CONTROL, l);
}
OMAPDSS: combine LCD related config into one func Dispc has a bunch of functions used to configure output related parameters: - dispc_mgr_set_io_pad_mode - dispc_mgr_enable_stallmode - dispc_mgr_enable_fifohandcheck - dispc_mgr_set_clock_div - dispc_mgr_set_tft_data_lines - dispc_lcd_enable_signal_polarity - dispc_mgr_set_lcd_type_tft These are all called together, and the configuration values are taken from struct dss_lcd_mgr_config. Instead of exposing those individual dispc functions, create a new one, dispc_mgr_set_lcd_config(), which is used to configure the above parameters from values in struct dss_lcd_mgr_config. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-12 10:30:39 +00:00
static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
OMAP: DSS2: Clean up stallmode and io pad mode selection Split the function dispc_set_parallel_interface_mode() into 2 separate functions called dispc_mgr_set_io_pad_mode() and dispc_mgr_enable_stallmode(). The current function tries to set 2 different modes(io pad mode and stall mode) based on a parameter omap_parallel_interface_mode which loosely corresponds to the panel interface type. This isn't correct because a) these 2 modes are independent to some extent, b) we are currently configuring gpout0/gpout1 for DSI panels which is unnecessary, c) a DSI Video mode panel won't get configured correctly. Splitting the functions allows the interface driver to set these modes independently and hence allow more flexibility. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-22 12:11:57 +00:00
{
OMAPDSS: Cleanup implementation of LCD channels The current implementation of LCD channels and managers consists of a number of if-else construct which has been replaced by a simpler interface. A constant structure mgr_desc has been created in Display Controller (DISPC) module. The mgr_desc contains for each channel its name, irqs and is initialized one time with all registers and their corresponding fields to be written to enable various features of Display Subsystem. This structure is later used by various functions of DISPC which simplifies the further implementation of LCD channels and its corresponding managers. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:37:44 +00:00
mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: combine LCD related config into one func Dispc has a bunch of functions used to configure output related parameters: - dispc_mgr_set_io_pad_mode - dispc_mgr_enable_stallmode - dispc_mgr_enable_fifohandcheck - dispc_mgr_set_clock_div - dispc_mgr_set_tft_data_lines - dispc_lcd_enable_signal_polarity - dispc_mgr_set_lcd_type_tft These are all called together, and the configuration values are taken from struct dss_lcd_mgr_config. Instead of exposing those individual dispc functions, create a new one, dispc_mgr_set_lcd_config(), which is used to configure the above parameters from values in struct dss_lcd_mgr_config. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-12 10:30:39 +00:00
void dispc_mgr_set_lcd_config(enum omap_channel channel,
const struct dss_lcd_mgr_config *config)
{
dispc_mgr_set_io_pad_mode(config->io_pad_mode);
dispc_mgr_enable_stallmode(channel, config->stallmode);
dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
dispc_mgr_set_clock_div(channel, &config->clock_info);
dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
dispc_mgr_set_lcd_type_tft(channel);
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
OMAPDSS: combine LCD related config into one func Dispc has a bunch of functions used to configure output related parameters: - dispc_mgr_set_io_pad_mode - dispc_mgr_enable_stallmode - dispc_mgr_enable_fifohandcheck - dispc_mgr_set_clock_div - dispc_mgr_set_tft_data_lines - dispc_lcd_enable_signal_polarity - dispc_mgr_set_lcd_type_tft These are all called together, and the configuration values are taken from struct dss_lcd_mgr_config. Instead of exposing those individual dispc functions, create a new one, dispc_mgr_set_lcd_config(), which is used to configure the above parameters from values in struct dss_lcd_mgr_config. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-12 10:30:39 +00:00
OMAPDSS: DISPC: Clean up manager timing/size functions Clean up the DISPC manager timings related function by: - Create a common function to set size for LCD and TV. - Create a common function to check timings for LCD and TV. - Add dss params to get the range of manager size. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:44 +00:00
static bool _dispc_mgr_size_ok(u16 width, u16 height)
{
OMAPDSS: Add overlay manager width and height limits as a dispc feature The overlay manager width and height vary in OMAP5 from previous OMAPs in terms of maximum limit and register field positions. Add parameters in dispc_features for these. Also remove params related to manager width and height from dss_features, as we want to maintain a feature list for individual IPs. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-14 08:20:15 +00:00
return width <= dispc.feat->mgr_width_max &&
height <= dispc.feat->mgr_height_max;
OMAPDSS: DISPC: Clean up manager timing/size functions Clean up the DISPC manager timings related function by: - Create a common function to set size for LCD and TV. - Create a common function to check timings for LCD and TV. - Add dss params to get the range of manager size. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:44 +00:00
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
int vsw, int vfp, int vbp)
{
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
if (hsw < 1 || hsw > dispc.feat->sw_max ||
hfp < 1 || hfp > dispc.feat->hp_max ||
hbp < 1 || hbp > dispc.feat->hp_max ||
vsw < 1 || vsw > dispc.feat->sw_max ||
vfp < 0 || vfp > dispc.feat->vp_max ||
vbp < 0 || vbp > dispc.feat->vp_max)
return false;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
return true;
}
omapdss: DISPC: add max pixel clock limits for LCD and TV managers Each version of OMAP has a limitation on the maximum pixel clock frequency supported by an overlay manager. This limit isn't checked by omapdss. Add dispc feats for lcd and tv managers and check whether the target timings can be supported or not. The pixel clock limitations are actually more complex. They depend on which OPP OMAP is in, and they also depend on which encoder is the manager connected to. The OPP dependence is ignored as DSS forces the PM framework to be on OPP100 when DSS is enabled, and the encoder dependencies are ignored by DISPC for now. These limits should come from the encoder driver. The OMAP2 TRM doesn't mention the maximum pixel clock limit. This value is left as half of DSS_FCLK, as OMAP2 requires the PCD to be atleast 2. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:22 +00:00
static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
unsigned long pclk)
{
if (dss_mgr_is_lcd(channel))
return pclk <= dispc.feat->max_lcd_pclk ? true : false;
else
return pclk <= dispc.feat->max_tv_pclk ? true : false;
}
OMAPDSS: DISPC: Clean up manager timing/size functions Clean up the DISPC manager timings related function by: - Create a common function to set size for LCD and TV. - Create a common function to check timings for LCD and TV. - Add dss params to get the range of manager size. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:44 +00:00
bool dispc_mgr_timings_ok(enum omap_channel channel,
OMAPDSS: MANAGER: Create a function to check manager timings Create a function dss_mgr_check_timings() which wraps around the function dispc_mgr_timings_ok(). This is mainly a clean up to hide dispc functions from interface drivers. dss_mgr_check_timings() is added in the function dss_mgr_check(), it currently takes the timings maintained in the omap_dss_device struct. This would be later replaced by the timings stored in the manager's private data. Make dss_mgr_check_timings() and dispc_mgr_timings_ok() take a const omap_video_timings pointer since these functions just check the timings. Signed-off-by: Archit Taneja <archit@ti.com>
2012-04-26 19:37:28 +00:00
const struct omap_video_timings *timings)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: DISPC: clean up dispc_mgr_timings_ok dispc_mgr_timings_ok() is a bit confusing how it handles the return value. Change the function to just return immediately when a timing is deemed not valid, making the code much easier to follow. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-06-05 08:36:08 +00:00
if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
return false;
OMAPDSS: DISPC: Clean up manager timing/size functions Clean up the DISPC manager timings related function by: - Create a common function to set size for LCD and TV. - Create a common function to check timings for LCD and TV. - Add dss params to get the range of manager size. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:44 +00:00
OMAPDSS: DISPC: clean up dispc_mgr_timings_ok dispc_mgr_timings_ok() is a bit confusing how it handles the return value. Change the function to just return immediately when a timing is deemed not valid, making the code much easier to follow. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-06-05 08:36:08 +00:00
if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
return false;
omapdss: DISPC: add max pixel clock limits for LCD and TV managers Each version of OMAP has a limitation on the maximum pixel clock frequency supported by an overlay manager. This limit isn't checked by omapdss. Add dispc feats for lcd and tv managers and check whether the target timings can be supported or not. The pixel clock limitations are actually more complex. They depend on which OPP OMAP is in, and they also depend on which encoder is the manager connected to. The OPP dependence is ignored as DSS forces the PM framework to be on OPP100 when DSS is enabled, and the encoder dependencies are ignored by DISPC for now. These limits should come from the encoder driver. The OMAP2 TRM doesn't mention the maximum pixel clock limit. This value is left as half of DSS_FCLK, as OMAP2 requires the PCD to be atleast 2. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:22 +00:00
if (dss_mgr_is_lcd(channel)) {
OMAPDSS: DISPC: reject interlace for lcd out OMAP2/3 does not support interlace for LCD out. OMAP4+ does, but is not supported by the driver at the moment. The driver still accepts interlaced mode for LCD out, causing broken display output. This patch makes dispc reject interlace for LCD out. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-06-05 08:35:10 +00:00
/* TODO: OMAP4+ supports interlace for LCD outputs */
OMAPDSS: DISPC: clean up dispc_mgr_timings_ok dispc_mgr_timings_ok() is a bit confusing how it handles the return value. Change the function to just return immediately when a timing is deemed not valid, making the code much easier to follow. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-06-05 08:36:08 +00:00
if (timings->interlace)
return false;
OMAPDSS: DISPC: reject interlace for lcd out OMAP2/3 does not support interlace for LCD out. OMAP4+ does, but is not supported by the driver at the moment. The driver still accepts interlaced mode for LCD out, causing broken display output. This patch makes dispc reject interlace for LCD out. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-06-05 08:35:10 +00:00
OMAPDSS: DISPC: clean up dispc_mgr_timings_ok dispc_mgr_timings_ok() is a bit confusing how it handles the return value. Change the function to just return immediately when a timing is deemed not valid, making the code much easier to follow. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-06-05 08:36:08 +00:00
if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
omapdss: DISPC: add max pixel clock limits for LCD and TV managers Each version of OMAP has a limitation on the maximum pixel clock frequency supported by an overlay manager. This limit isn't checked by omapdss. Add dispc feats for lcd and tv managers and check whether the target timings can be supported or not. The pixel clock limitations are actually more complex. They depend on which OPP OMAP is in, and they also depend on which encoder is the manager connected to. The OPP dependence is ignored as DSS forces the PM framework to be on OPP100 when DSS is enabled, and the encoder dependencies are ignored by DISPC for now. These limits should come from the encoder driver. The OMAP2 TRM doesn't mention the maximum pixel clock limit. This value is left as half of DSS_FCLK, as OMAP2 requires the PCD to be atleast 2. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:22 +00:00
timings->hbp, timings->vsw, timings->vfp,
OMAPDSS: DISPC: clean up dispc_mgr_timings_ok dispc_mgr_timings_ok() is a bit confusing how it handles the return value. Change the function to just return immediately when a timing is deemed not valid, making the code much easier to follow. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-06-05 08:36:08 +00:00
timings->vbp))
return false;
omapdss: DISPC: add max pixel clock limits for LCD and TV managers Each version of OMAP has a limitation on the maximum pixel clock frequency supported by an overlay manager. This limit isn't checked by omapdss. Add dispc feats for lcd and tv managers and check whether the target timings can be supported or not. The pixel clock limitations are actually more complex. They depend on which OPP OMAP is in, and they also depend on which encoder is the manager connected to. The OPP dependence is ignored as DSS forces the PM framework to be on OPP100 when DSS is enabled, and the encoder dependencies are ignored by DISPC for now. These limits should come from the encoder driver. The OMAP2 TRM doesn't mention the maximum pixel clock limit. This value is left as half of DSS_FCLK, as OMAP2 requires the PCD to be atleast 2. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:22 +00:00
}
OMAPDSS: DISPC: Clean up manager timing/size functions Clean up the DISPC manager timings related function by: - Create a common function to set size for LCD and TV. - Create a common function to check timings for LCD and TV. - Add dss params to get the range of manager size. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:44 +00:00
OMAPDSS: DISPC: clean up dispc_mgr_timings_ok dispc_mgr_timings_ok() is a bit confusing how it handles the return value. Change the function to just return immediately when a timing is deemed not valid, making the code much easier to follow. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-06-05 08:36:08 +00:00
return true;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename manager related funcs Rename dispc's manager related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_mgr_* - Remove "channel" from the name, e.g. dispc_enable_channel -> dispc_mgr_enable The idea is to group manager related functions so that it can be deduced from the function name that it writes to manager spesific registers. All dispc_mgr_* functions have enum omap_channel as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:45:15 +00:00
static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
OMAPDSS: DISPC: Configure newly added omap_video_timing fields Hsync, Vsync, Data enable enable logic levels and latching info of Data lanes, Hsync and Vsync signals(with respect to pixel clock) are newly added parameters in omap_video_timings. Program these in dispc_mgr_set_lcd_timings. These will be configured when the manager's timings are set via dss_mgr_set_timings(). Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-21 05:07:43 +00:00
int hfp, int hbp, int vsw, int vfp, int vbp,
enum omap_dss_signal_level vsync_level,
enum omap_dss_signal_level hsync_level,
enum omap_dss_signal_edge data_pclk_edge,
enum omap_dss_signal_level de_level,
enum omap_dss_signal_edge sync_pclk_edge)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: DISPC: Configure newly added omap_video_timing fields Hsync, Vsync, Data enable enable logic levels and latching info of Data lanes, Hsync and Vsync signals(with respect to pixel clock) are newly added parameters in omap_video_timings. Program these in dispc_mgr_set_lcd_timings. These will be configured when the manager's timings are set via dss_mgr_set_timings(). Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-21 05:07:43 +00:00
u32 timing_h, timing_v, l;
OMAPDSS: DISPC: explicit handling for sync and de levels When configuring the lcd timings, instead of writing enum values directly to the HW, use switch-case to get the value to be programmed. This is safer and also allows us to change the enum values. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-02 17:58:49 +00:00
bool onoff, rf, ipc, vs, hs, de;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
FLD_VAL(vfp, dispc.feat->fp_start, 8) |
FLD_VAL(vbp, dispc.feat->bp_start, 20);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Introduce omap_channel argument to DISPC functions used by interface drivers The interface drivers (dsi.c, sdi.c etc) need to call dispc functions with dssdev->manager->id as a parameter to specify the DISPC channel which they want to configure/use, this is required as the same functions are now used to configure dispc registers of different channels. The following dispc functions are changed to incorporate channel as an argument: -dispc_enable_fifohandcheck() -dispc_set_lcd_size() -dispc_set_parallel_interface_mode() -dispc_set_tft_data_lines() -dispc_set_lcd_display_type() -dispc_set_lcd_timings() Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> [tomi.valkeinen@nokia.com: fixed trivial compile error] Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:10 +00:00
dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
OMAPDSS: DISPC: Configure newly added omap_video_timing fields Hsync, Vsync, Data enable enable logic levels and latching info of Data lanes, Hsync and Vsync signals(with respect to pixel clock) are newly added parameters in omap_video_timings. Program these in dispc_mgr_set_lcd_timings. These will be configured when the manager's timings are set via dss_mgr_set_timings(). Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-21 05:07:43 +00:00
OMAPDSS: DISPC: explicit handling for sync and de levels When configuring the lcd timings, instead of writing enum values directly to the HW, use switch-case to get the value to be programmed. This is safer and also allows us to change the enum values. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-02 17:58:49 +00:00
switch (vsync_level) {
case OMAPDSS_SIG_ACTIVE_LOW:
vs = true;
break;
case OMAPDSS_SIG_ACTIVE_HIGH:
vs = false;
break;
default:
BUG();
}
switch (hsync_level) {
case OMAPDSS_SIG_ACTIVE_LOW:
hs = true;
break;
case OMAPDSS_SIG_ACTIVE_HIGH:
hs = false;
break;
default:
BUG();
}
switch (de_level) {
case OMAPDSS_SIG_ACTIVE_LOW:
de = true;
break;
case OMAPDSS_SIG_ACTIVE_HIGH:
de = false;
break;
default:
BUG();
}
OMAPDSS: DISPC: Configure newly added omap_video_timing fields Hsync, Vsync, Data enable enable logic levels and latching info of Data lanes, Hsync and Vsync signals(with respect to pixel clock) are newly added parameters in omap_video_timings. Program these in dispc_mgr_set_lcd_timings. These will be configured when the manager's timings are set via dss_mgr_set_timings(). Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-21 05:07:43 +00:00
switch (data_pclk_edge) {
case OMAPDSS_DRIVE_SIG_RISING_EDGE:
ipc = false;
break;
case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
ipc = true;
break;
default:
BUG();
}
OMAPDSS: DISPC: remove OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES DISPC can drive data lines either on rising or falling pixel clock edge, which can be configured by the user. Sync lines can also be driven on rising or falling pixel clock edge, but additionally the HW can be configured to drive the sync lines on opposite clock edge from the data lines. This opposite edge setting does not make any sense, as the same effect can be achieved by just setting the sync lines to be driven on the other edge compared to the data lines. It feels like some kind of backward compatibility option, even if all DSS versions seem to have the same implementation. To simplify the code and configuration of the signals, and to make the dispc timings more compatible with what is used on other platforms, let's just remove the whole opposite-edge support. The drivers that used OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES setting are changed so that they use the opposite setting from the data edge. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-02 17:58:48 +00:00
/* always use the 'rf' setting */
onoff = true;
OMAPDSS: DISPC: Configure newly added omap_video_timing fields Hsync, Vsync, Data enable enable logic levels and latching info of Data lanes, Hsync and Vsync signals(with respect to pixel clock) are newly added parameters in omap_video_timings. Program these in dispc_mgr_set_lcd_timings. These will be configured when the manager's timings are set via dss_mgr_set_timings(). Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-21 05:07:43 +00:00
switch (sync_pclk_edge) {
case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
rf = false;
break;
case OMAPDSS_DRIVE_SIG_RISING_EDGE:
rf = true;
break;
default:
BUG();
video: Remove unnecessary semicolons These aren't necessary after switch, for, and if blocks. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-10-08 23:23:24 +00:00
}
OMAPDSS: DISPC: Configure newly added omap_video_timing fields Hsync, Vsync, Data enable enable logic levels and latching info of Data lanes, Hsync and Vsync signals(with respect to pixel clock) are newly added parameters in omap_video_timings. Program these in dispc_mgr_set_lcd_timings. These will be configured when the manager's timings are set via dss_mgr_set_timings(). Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-21 05:07:43 +00:00
OMAPDSS: Fix writes to DISPC_POL_FREQ When omapdss writes to DISPC_POL_FREQ register, it always ORs the bits with the current contents of the register, never clearing the old ones, causing wrong signal polarity settings. As we write all the bits in DISPC_POL_FREQ, we don't need to care about the current contents of the register. So fix the issue by constructing new register value from scratch. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-25 08:46:16 +00:00
l = FLD_VAL(onoff, 17, 17) |
FLD_VAL(rf, 16, 16) |
OMAPDSS: DISPC: explicit handling for sync and de levels When configuring the lcd timings, instead of writing enum values directly to the HW, use switch-case to get the value to be programmed. This is safer and also allows us to change the enum values. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-02 17:58:49 +00:00
FLD_VAL(de, 15, 15) |
OMAPDSS: Fix writes to DISPC_POL_FREQ When omapdss writes to DISPC_POL_FREQ register, it always ORs the bits with the current contents of the register, never clearing the old ones, causing wrong signal polarity settings. As we write all the bits in DISPC_POL_FREQ, we don't need to care about the current contents of the register. So fix the issue by constructing new register value from scratch. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-25 08:46:16 +00:00
FLD_VAL(ipc, 14, 14) |
OMAPDSS: DISPC: explicit handling for sync and de levels When configuring the lcd timings, instead of writing enum values directly to the HW, use switch-case to get the value to be programmed. This is safer and also allows us to change the enum values. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-02 17:58:49 +00:00
FLD_VAL(hs, 13, 13) |
FLD_VAL(vs, 12, 12);
OMAPDSS: Fix writes to DISPC_POL_FREQ When omapdss writes to DISPC_POL_FREQ register, it always ORs the bits with the current contents of the register, never clearing the old ones, causing wrong signal polarity settings. As we write all the bits in DISPC_POL_FREQ, we don't need to care about the current contents of the register. So fix the issue by constructing new register value from scratch. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-25 08:46:16 +00:00
OMAPDSS: DISPC: Configure newly added omap_video_timing fields Hsync, Vsync, Data enable enable logic levels and latching info of Data lanes, Hsync and Vsync signals(with respect to pixel clock) are newly added parameters in omap_video_timings. Program these in dispc_mgr_set_lcd_timings. These will be configured when the manager's timings are set via dss_mgr_set_timings(). Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-21 05:07:43 +00:00
dispc_write_reg(DISPC_POL_FREQ(channel), l);
OMAPDSS: DISPC: program dispc polarities to control module On DRA7xx, DISPC needs to write output signal polarities not only to a DISPC register, like for all earlier DSS versions, but to control module's CTRL_CORE_SMA_SW_1 register. This patch adds support to write the polarities to control module. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-09-05 19:15:03 +00:00
if (dispc.syscon_pol) {
const int shifts[] = {
[OMAP_DSS_CHANNEL_LCD] = 0,
[OMAP_DSS_CHANNEL_LCD2] = 1,
[OMAP_DSS_CHANNEL_LCD3] = 2,
};
u32 mask, val;
mask = (1 << 0) | (1 << 3) | (1 << 6);
val = (rf << 0) | (ipc << 3) | (onoff << 6);
mask <<= 16 + shifts[channel];
val <<= 16 + shifts[channel];
regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
mask, val);
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
/* change name to mode? */
OMAPDSS: DISPC: Use a common function to set manager timings Currently, a LCD manager's timings is set by dispc_mgr_set_lcd_timings() and TV manager's timings is set by dispc_set_digit_size(). Use a common function called dispc_mgr_set_timings() which sets timings for both type of managers. We finally want the interface drivers to use an overlay manager function to configure it's timings, having a common DISPC function would make things cleaner. For LCD managers, dispc_mgr_set_timings() sets LCD size and blanking values, for TV manager, it sets only the TV size since blanking values don't exist for TV. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:43 +00:00
void dispc_mgr_set_timings(enum omap_channel channel,
OMAPDSS: DISPC: constify function parameters Add consts to dispc function parameters which do not modify the passed structs. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-03 07:09:11 +00:00
const struct omap_video_timings *timings)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
unsigned xtot, ytot;
unsigned long ht, vt;
OMAPDSS: VENC/DISPC: Delay dividing Y resolution for managers connected to VENC DSS2 driver uses the timings in manager's private data to check the validity of overlay and manager infos written by the user. For VENC interface, we divide the Y resolution by half when writing to the DISPC_DIGIT_SIZE register as the content is interlaced. However, the height of the manager/display with respect to the content shown through VENC still remains the same. The VENC driver divides the y_res parameter in omap_video_timings by half, and then applies the configuration. This leads to manager's private data storing the wrong Y resolution. Hence, overlay related checks fail. Ensure that manager's private data stores the original timings, and the Y resolution is halved only when we write to the DISPC register. This is a hack, the proper solution would be to pass some sort of interlace parameter which makes the call whether we should divide y_res or not. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 09:06:54 +00:00
struct omap_video_timings t = *timings;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: VENC/DISPC: Delay dividing Y resolution for managers connected to VENC DSS2 driver uses the timings in manager's private data to check the validity of overlay and manager infos written by the user. For VENC interface, we divide the Y resolution by half when writing to the DISPC_DIGIT_SIZE register as the content is interlaced. However, the height of the manager/display with respect to the content shown through VENC still remains the same. The VENC driver divides the y_res parameter in omap_video_timings by half, and then applies the configuration. This leads to manager's private data storing the wrong Y resolution. Hence, overlay related checks fail. Ensure that manager's private data stores the original timings, and the Y resolution is halved only when we write to the DISPC register. This is a hack, the proper solution would be to pass some sort of interlace parameter which makes the call whether we should divide y_res or not. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 09:06:54 +00:00
DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: VENC/DISPC: Delay dividing Y resolution for managers connected to VENC DSS2 driver uses the timings in manager's private data to check the validity of overlay and manager infos written by the user. For VENC interface, we divide the Y resolution by half when writing to the DISPC_DIGIT_SIZE register as the content is interlaced. However, the height of the manager/display with respect to the content shown through VENC still remains the same. The VENC driver divides the y_res parameter in omap_video_timings by half, and then applies the configuration. This leads to manager's private data storing the wrong Y resolution. Hence, overlay related checks fail. Ensure that manager's private data stores the original timings, and the Y resolution is halved only when we write to the DISPC register. This is a hack, the proper solution would be to pass some sort of interlace parameter which makes the call whether we should divide y_res or not. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 09:06:54 +00:00
if (!dispc_mgr_timings_ok(channel, &t)) {
OMAPDSS: DISPC: Clean up manager timing/size functions Clean up the DISPC manager timings related function by: - Create a common function to set size for LCD and TV. - Create a common function to check timings for LCD and TV. - Add dss params to get the range of manager size. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:44 +00:00
BUG();
OMAPDSS: remove compiler warnings when CONFIG_BUG=n If CONFIG_BUG is not enabled, BUG() does not stop the execution. Many places in code expect the execution to stop, and this causes compiler warnings about uninitialized variables and returning from a non-void function without a return value. This patch fixes the warnings by initializing the variables and returning properly after BUG() lines. However, the behaviour is still undefined after the BUG, but this is the choice the user makes when using CONFIG_BUG=n. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 08:47:02 +00:00
return;
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Remove a redundant function dss_mgr_is_lcd() available in dss.h does the same thing as dispc_mgr_is_lcd() in dispc.c. Remove the function from dispc.c and replace it with the one in dss.h. Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-29 09:11:30 +00:00
if (dss_mgr_is_lcd(channel)) {
OMAPDSS: VENC/DISPC: Delay dividing Y resolution for managers connected to VENC DSS2 driver uses the timings in manager's private data to check the validity of overlay and manager infos written by the user. For VENC interface, we divide the Y resolution by half when writing to the DISPC_DIGIT_SIZE register as the content is interlaced. However, the height of the manager/display with respect to the content shown through VENC still remains the same. The VENC driver divides the y_res parameter in omap_video_timings by half, and then applies the configuration. This leads to manager's private data storing the wrong Y resolution. Hence, overlay related checks fail. Ensure that manager's private data stores the original timings, and the Y resolution is halved only when we write to the DISPC register. This is a hack, the proper solution would be to pass some sort of interlace parameter which makes the call whether we should divide y_res or not. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 09:06:54 +00:00
_dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
OMAPDSS: DISPC: Configure newly added omap_video_timing fields Hsync, Vsync, Data enable enable logic levels and latching info of Data lanes, Hsync and Vsync signals(with respect to pixel clock) are newly added parameters in omap_video_timings. Program these in dispc_mgr_set_lcd_timings. These will be configured when the manager's timings are set via dss_mgr_set_timings(). Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-21 05:07:43 +00:00
t.vfp, t.vbp, t.vsync_level, t.hsync_level,
t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: VENC/DISPC: Delay dividing Y resolution for managers connected to VENC DSS2 driver uses the timings in manager's private data to check the validity of overlay and manager infos written by the user. For VENC interface, we divide the Y resolution by half when writing to the DISPC_DIGIT_SIZE register as the content is interlaced. However, the height of the manager/display with respect to the content shown through VENC still remains the same. The VENC driver divides the y_res parameter in omap_video_timings by half, and then applies the configuration. This leads to manager's private data storing the wrong Y resolution. Hence, overlay related checks fail. Ensure that manager's private data stores the original timings, and the Y resolution is halved only when we write to the DISPC register. This is a hack, the proper solution would be to pass some sort of interlace parameter which makes the call whether we should divide y_res or not. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 09:06:54 +00:00
xtot = t.x_res + t.hfp + t.hsw + t.hbp;
ytot = t.y_res + t.vfp + t.vsw + t.vbp;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: convert pixel clock to common videomode style omapdss has its own video-timings struct, but we want to move the common videomode. The first step is to change the omapdss's pixelclock unit from kHz to Hz. Also, omapdss uses "pixel_clock" field name, whereas the common videomode uses "pixelclock" field name. This patch changes the field name also, as that makes it easy to spot any non-converted pixel_clock uses. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-04-10 11:12:14 +00:00
ht = timings->pixelclock / xtot;
vt = timings->pixelclock / xtot / ytot;
OMAPDSS: DISPC: Use a common function to set manager timings Currently, a LCD manager's timings is set by dispc_mgr_set_lcd_timings() and TV manager's timings is set by dispc_set_digit_size(). Use a common function called dispc_mgr_set_timings() which sets timings for both type of managers. We finally want the interface drivers to use an overlay manager function to configure it's timings, having a common DISPC function would make things cleaner. For LCD managers, dispc_mgr_set_timings() sets LCD size and blanking values, for TV manager, it sets only the TV size since blanking values don't exist for TV. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:43 +00:00
OMAPDSS: convert pixel clock to common videomode style omapdss has its own video-timings struct, but we want to move the common videomode. The first step is to change the omapdss's pixelclock unit from kHz to Hz. Also, omapdss uses "pixel_clock" field name, whereas the common videomode uses "pixelclock" field name. This patch changes the field name also, as that makes it easy to spot any non-converted pixel_clock uses. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-04-10 11:12:14 +00:00
DSSDBG("pck %u\n", timings->pixelclock);
OMAPDSS: DISPC: Use a common function to set manager timings Currently, a LCD manager's timings is set by dispc_mgr_set_lcd_timings() and TV manager's timings is set by dispc_set_digit_size(). Use a common function called dispc_mgr_set_timings() which sets timings for both type of managers. We finally want the interface drivers to use an overlay manager function to configure it's timings, having a common DISPC function would make things cleaner. For LCD managers, dispc_mgr_set_timings() sets LCD size and blanking values, for TV manager, it sets only the TV size since blanking values don't exist for TV. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:43 +00:00
DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
OMAPDSS: VENC/DISPC: Delay dividing Y resolution for managers connected to VENC DSS2 driver uses the timings in manager's private data to check the validity of overlay and manager infos written by the user. For VENC interface, we divide the Y resolution by half when writing to the DISPC_DIGIT_SIZE register as the content is interlaced. However, the height of the manager/display with respect to the content shown through VENC still remains the same. The VENC driver divides the y_res parameter in omap_video_timings by half, and then applies the configuration. This leads to manager's private data storing the wrong Y resolution. Hence, overlay related checks fail. Ensure that manager's private data stores the original timings, and the Y resolution is halved only when we write to the DISPC register. This is a hack, the proper solution would be to pass some sort of interlace parameter which makes the call whether we should divide y_res or not. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 09:06:54 +00:00
t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
OMAPDSS: DISPC: Configure newly added omap_video_timing fields Hsync, Vsync, Data enable enable logic levels and latching info of Data lanes, Hsync and Vsync signals(with respect to pixel clock) are newly added parameters in omap_video_timings. Program these in dispc_mgr_set_lcd_timings. These will be configured when the manager's timings are set via dss_mgr_set_timings(). Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-21 05:07:43 +00:00
DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
t.vsync_level, t.hsync_level, t.data_pclk_edge,
t.de_level, t.sync_pclk_edge);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Use a common function to set manager timings Currently, a LCD manager's timings is set by dispc_mgr_set_lcd_timings() and TV manager's timings is set by dispc_set_digit_size(). Use a common function called dispc_mgr_set_timings() which sets timings for both type of managers. We finally want the interface drivers to use an overlay manager function to configure it's timings, having a common DISPC function would make things cleaner. For LCD managers, dispc_mgr_set_timings() sets LCD size and blanking values, for TV manager, it sets only the TV size since blanking values don't exist for TV. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:43 +00:00
DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
OMAPDSS: VENC/DISPC: Delay dividing Y resolution for managers connected to VENC DSS2 driver uses the timings in manager's private data to check the validity of overlay and manager infos written by the user. For VENC interface, we divide the Y resolution by half when writing to the DISPC_DIGIT_SIZE register as the content is interlaced. However, the height of the manager/display with respect to the content shown through VENC still remains the same. The VENC driver divides the y_res parameter in omap_video_timings by half, and then applies the configuration. This leads to manager's private data storing the wrong Y resolution. Hence, overlay related checks fail. Ensure that manager's private data stores the original timings, and the Y resolution is halved only when we write to the DISPC register. This is a hack, the proper solution would be to pass some sort of interlace parameter which makes the call whether we should divide y_res or not. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 09:06:54 +00:00
} else {
OMAPDSS: Add interlace parameter to omap_video_timings Add a parameter called interlace which tells whether the timings are in interlaced or progressive mode. This aligns the omap_video_timings struct with the Xorg modeline configuration. It also removes the hack needed to write to divide the manager height by 2 if the connected interface is VENC. Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-28 05:45:51 +00:00
if (t.interlace == true)
OMAPDSS: VENC/DISPC: Delay dividing Y resolution for managers connected to VENC DSS2 driver uses the timings in manager's private data to check the validity of overlay and manager infos written by the user. For VENC interface, we divide the Y resolution by half when writing to the DISPC_DIGIT_SIZE register as the content is interlaced. However, the height of the manager/display with respect to the content shown through VENC still remains the same. The VENC driver divides the y_res parameter in omap_video_timings by half, and then applies the configuration. This leads to manager's private data storing the wrong Y resolution. Hence, overlay related checks fail. Ensure that manager's private data stores the original timings, and the Y resolution is halved only when we write to the DISPC register. This is a hack, the proper solution would be to pass some sort of interlace parameter which makes the call whether we should divide y_res or not. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 09:06:54 +00:00
t.y_res /= 2;
OMAPDSS: DISPC: Use a common function to set manager timings Currently, a LCD manager's timings is set by dispc_mgr_set_lcd_timings() and TV manager's timings is set by dispc_set_digit_size(). Use a common function called dispc_mgr_set_timings() which sets timings for both type of managers. We finally want the interface drivers to use an overlay manager function to configure it's timings, having a common DISPC function would make things cleaner. For LCD managers, dispc_mgr_set_timings() sets LCD size and blanking values, for TV manager, it sets only the TV size since blanking values don't exist for TV. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:43 +00:00
}
OMAPDSS: DISPC: Clean up manager timing/size functions Clean up the DISPC manager timings related function by: - Create a common function to set size for LCD and TV. - Create a common function to check timings for LCD and TV. - Add dss params to get the range of manager size. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-16 07:23:44 +00:00
OMAPDSS: VENC/DISPC: Delay dividing Y resolution for managers connected to VENC DSS2 driver uses the timings in manager's private data to check the validity of overlay and manager infos written by the user. For VENC interface, we divide the Y resolution by half when writing to the DISPC_DIGIT_SIZE register as the content is interlaced. However, the height of the manager/display with respect to the content shown through VENC still remains the same. The VENC driver divides the y_res parameter in omap_video_timings by half, and then applies the configuration. This leads to manager's private data storing the wrong Y resolution. Hence, overlay related checks fail. Ensure that manager's private data stores the original timings, and the Y resolution is halved only when we write to the DISPC register. This is a hack, the proper solution would be to pass some sort of interlace parameter which makes the call whether we should divide y_res or not. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 09:06:54 +00:00
dispc_mgr_set_size(channel, t.x_res, t.y_res);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_mgr_set_timings);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: DISPC: rename manager related funcs Rename dispc's manager related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_mgr_* - Remove "channel" from the name, e.g. dispc_enable_channel -> dispc_mgr_enable The idea is to group manager related functions so that it can be deduced from the function name that it writes to manager spesific registers. All dispc_mgr_* functions have enum omap_channel as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:45:15 +00:00
static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
OMAP: DSS2: Change remaining DISPC functions for new omap_channel argument The following dispc functions are also changed to incorporate channel as an argument: -dispc_lclk_rate() -dispc_pclk_rate() -dispc_set_pol_freq() -dispc_set_clock_div() -dispc_get_clock_div() Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> [tomi.valkeinen@nokia.com: fixed trivial compile error] Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:11 +00:00
u16 pck_div)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
BUG_ON(lck_div < 1);
OMAP: DSS2: DISPC: Fix minimum PCD value The current driver had a hardcoded minimum value of 2 for pixel clock divisor (PCD). This doesn't seem to be right. OMAP4 TRM says that PCD can be 1 when not downscaling, and inverted pixel clock (IPC) is off. OMAP3 TRM says the same, but also in the register descriptions that PCD value 1 is invalid. OMAP2 TRM says PCD 2 is the minimum. OMAP2 is still untested, but for both OMAP3 and OMAP4 PCD of 1 seems to work fine. This patch adds a new DSS feature, FEAT_PARAM_DSS_PCD, which is used to find the minimum and maximum PCD. The minimum is set to 2 for OMAP2, and 1 for OMAP3/4. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-29 12:56:04 +00:00
BUG_ON(pck_div < 1);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch) The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR. However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK independent of Primary and Secondary display clocks. Renamed DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch), to facilitate introduction of DISPC_DIVISOR register, which is specific for OMAP4. OMAP4 has 3 registers DISPC_DIVISOR, DISPC_DIVISOR1 and DISPC_DIVISOR2. Also updated, all the usages of DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch). Use DISPC_DIVISORo(ch) when DISPC_DIVISOR1 or DISPC_DIVISOR2 has to be configured OMAP4 TRM uses DISPC_DIVISORo generically to refer to DISPC_DIVISOR1 and DISPC_DIVISOR2 Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-03 15:27:59 +00:00
dispc_write_reg(DISPC_DIVISORo(channel),
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
OMAPDSS: DISPC: store core clk rate Store dispc core clock rate so that it's available for calculations even if the HW is disabled. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-06 13:54:11 +00:00
if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
channel == OMAP_DSS_CHANNEL_LCD)
dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename manager related funcs Rename dispc's manager related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_mgr_* - Remove "channel" from the name, e.g. dispc_enable_channel -> dispc_mgr_enable The idea is to group manager related functions so that it can be deduced from the function name that it writes to manager spesific registers. All dispc_mgr_* functions have enum omap_channel as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:45:15 +00:00
static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
int *pck_div)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
u32 l;
OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch) The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR. However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK independent of Primary and Secondary display clocks. Renamed DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch), to facilitate introduction of DISPC_DIVISOR register, which is specific for OMAP4. OMAP4 has 3 registers DISPC_DIVISOR, DISPC_DIVISOR1 and DISPC_DIVISOR2. Also updated, all the usages of DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch). Use DISPC_DIVISORo(ch) when DISPC_DIVISOR1 or DISPC_DIVISOR2 has to be configured OMAP4 TRM uses DISPC_DIVISORo generically to refer to DISPC_DIVISOR1 and DISPC_DIVISOR2 Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-03 15:27:59 +00:00
l = dispc_read_reg(DISPC_DIVISORo(channel));
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
*lck_div = FLD_GET(l, 23, 16);
*pck_div = FLD_GET(l, 7, 0);
}
unsigned long dispc_fclk_rate(void)
{
OMAPDSS: DSI: use common DSS PLL support Now that we have the common DSS PLL support, change DSI to use it. This results in quite a lot of changes, but almost all of them are trivial name changes. The functions to calculate and program the PLL settings can be removed from dsi.c, as the common PLL API contains the same functionality. We also need to create struct dss_pll_hw entries for PLL hardware features for different OMAP platforms, instead of using the dss_features.c as the old code does. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-22 11:49:14 +00:00
struct dss_pll *pll;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
unsigned long r = 0;
OMAP2PLUS: DSS2: Cleanup clock source related code Clean up some of the DSS functions which select/get clock sources, use switch to select the clock source members since more clock sources will be introduced later on. Remove the use of macro CONFIG_OMAP2_DSS_DSI in dispc_fclk_rate, use a dummy inline for function for dsi_get_pll_hsdiv_dispc_rate() instead for code clarity. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-08 11:50:34 +00:00
switch (dss_get_dispc_clk_source()) {
OMAP2PLUS: DSS2: Change enum "dss_clk_source" to "omap_dss_clk_source" Change enum dss_clk_source to omap_dss_clock_source and move it to 'plat/display.h'. Change the enum members to attach "OMAP_" in the beginning. These changes are done in order to specify the clock sources for DSS in the board file. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-04-12 08:22:23 +00:00
case OMAP_DSS_CLK_SRC_FCK:
OMAPDSS: DISPC: get dss clock rate from dss driver Dispc currently gets dispc's fck with clk_get() and uses clk_get_rate() to get the rate for scaling calculations. This causes a problem with common clock framework, as omapdss uses the dispc functions inside a spinlock, and common clock framework uses a mutex in clk_get_rate(). Looking at the DSS clock tree, the above use of the dispc fck is not quite correct. The DSS_FCLK from PRCM goes to DSS core block, which has a mux to select the clock for DISPC from various options, so the current use of dispc fck bypasses that. Fortunately we never change the dispc clock mux for now. To fix the issue with clk_get_rate(), this patch caches the dss clock rate in dss.c when it is set. Dispc will then ask for the clock rate from dss. While this is not very elegant, it does fix the issue, and it's not totally wrong when considering that the dispc fck actually comes via dss. In the future we should probably look into common clock framework and see if that could be used to represent the DSS clock tree properly. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-12-12 08:37:03 +00:00
r = dss_get_dispc_clk_rate();
OMAP2PLUS: DSS2: Cleanup clock source related code Clean up some of the DSS functions which select/get clock sources, use switch to select the clock source members since more clock sources will be introduced later on. Remove the use of macro CONFIG_OMAP2_DSS_DSI in dispc_fclk_rate, use a dummy inline for function for dsi_get_pll_hsdiv_dispc_rate() instead for code clarity. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-08 11:50:34 +00:00
break;
OMAP2PLUS: DSS2: Change enum "dss_clk_source" to "omap_dss_clk_source" Change enum dss_clk_source to omap_dss_clock_source and move it to 'plat/display.h'. Change the enum members to attach "OMAP_" in the beginning. These changes are done in order to specify the clock sources for DSS in the board file. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-04-12 08:22:23 +00:00
case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
OMAPDSS: DSI: use common DSS PLL support Now that we have the common DSS PLL support, change DSI to use it. This results in quite a lot of changes, but almost all of them are trivial name changes. The functions to calculate and program the PLL settings can be removed from dsi.c, as the common PLL API contains the same functionality. We also need to create struct dss_pll_hw entries for PLL hardware features for different OMAP platforms, instead of using the dss_features.c as the old code does. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-22 11:49:14 +00:00
pll = dss_pll_find("dsi0");
OMAPDSS: DISPC: Add DRA7xx support Add DRA7xx support to DISPC driver. The DISPC block is the same as on OMAP5, except the PLL's used for clocking are "videoX", not "dsiX". Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-12-31 09:25:48 +00:00
if (!pll)
pll = dss_pll_find("video0");
OMAPDSS: DSI: use common DSS PLL support Now that we have the common DSS PLL support, change DSI to use it. This results in quite a lot of changes, but almost all of them are trivial name changes. The functions to calculate and program the PLL settings can be removed from dsi.c, as the common PLL API contains the same functionality. We also need to create struct dss_pll_hw entries for PLL hardware features for different OMAP platforms, instead of using the dss_features.c as the old code does. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-22 11:49:14 +00:00
r = pll->cinfo.clkout[0];
OMAP2PLUS: DSS2: Cleanup clock source related code Clean up some of the DSS functions which select/get clock sources, use switch to select the clock source members since more clock sources will be introduced later on. Remove the use of macro CONFIG_OMAP2_DSS_DSI in dispc_fclk_rate, use a dummy inline for function for dsi_get_pll_hsdiv_dispc_rate() instead for code clarity. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-08 11:50:34 +00:00
break;
OMAP4: DSS2: DSI: Changes for DSI2 on OMAP4 Introduce DSI2 PLL clock sources needed by LCD2 channel and DSI2 Protocol engine and DISPC Functional clock. Do the following: - Modify dss_get_dsi_clk_source() and dss_select_dsi_clk_source() to take the dsi module number as an argument. - Create debugfs files for dsi2, split the corresponding debugfs functions. - Allow DPI to use these new clock sources. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-12 11:56:29 +00:00
case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
OMAPDSS: DSI: use common DSS PLL support Now that we have the common DSS PLL support, change DSI to use it. This results in quite a lot of changes, but almost all of them are trivial name changes. The functions to calculate and program the PLL settings can be removed from dsi.c, as the common PLL API contains the same functionality. We also need to create struct dss_pll_hw entries for PLL hardware features for different OMAP platforms, instead of using the dss_features.c as the old code does. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-22 11:49:14 +00:00
pll = dss_pll_find("dsi1");
OMAPDSS: DISPC: Add DRA7xx support Add DRA7xx support to DISPC driver. The DISPC block is the same as on OMAP5, except the PLL's used for clocking are "videoX", not "dsiX". Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-12-31 09:25:48 +00:00
if (!pll)
pll = dss_pll_find("video1");
OMAPDSS: DSI: use common DSS PLL support Now that we have the common DSS PLL support, change DSI to use it. This results in quite a lot of changes, but almost all of them are trivial name changes. The functions to calculate and program the PLL settings can be removed from dsi.c, as the common PLL API contains the same functionality. We also need to create struct dss_pll_hw entries for PLL hardware features for different OMAP platforms, instead of using the dss_features.c as the old code does. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-22 11:49:14 +00:00
r = pll->cinfo.clkout[0];
OMAP4: DSS2: DSI: Changes for DSI2 on OMAP4 Introduce DSI2 PLL clock sources needed by LCD2 channel and DSI2 Protocol engine and DISPC Functional clock. Do the following: - Modify dss_get_dsi_clk_source() and dss_select_dsi_clk_source() to take the dsi module number as an argument. - Create debugfs files for dsi2, split the corresponding debugfs functions. - Allow DPI to use these new clock sources. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-12 11:56:29 +00:00
break;
OMAP2PLUS: DSS2: Cleanup clock source related code Clean up some of the DSS functions which select/get clock sources, use switch to select the clock source members since more clock sources will be introduced later on. Remove the use of macro CONFIG_OMAP2_DSS_DSI in dispc_fclk_rate, use a dummy inline for function for dsi_get_pll_hsdiv_dispc_rate() instead for code clarity. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-08 11:50:34 +00:00
default:
BUG();
OMAPDSS: remove compiler warnings when CONFIG_BUG=n If CONFIG_BUG is not enabled, BUG() does not stop the execution. Many places in code expect the execution to stop, and this causes compiler warnings about uninitialized variables and returning from a non-void function without a return value. This patch fixes the warnings by initializing the variables and returning properly after BUG() lines. However, the behaviour is still undefined after the BUG, but this is the choice the user makes when using CONFIG_BUG=n. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-05-18 08:47:02 +00:00
return 0;
OMAP2PLUS: DSS2: Cleanup clock source related code Clean up some of the DSS functions which select/get clock sources, use switch to select the clock source members since more clock sources will be introduced later on. Remove the use of macro CONFIG_OMAP2_DSS_DSI in dispc_fclk_rate, use a dummy inline for function for dsi_get_pll_hsdiv_dispc_rate() instead for code clarity. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-08 11:50:34 +00:00
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
return r;
}
OMAP: DSS2: DISPC: rename manager related funcs Rename dispc's manager related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_mgr_* - Remove "channel" from the name, e.g. dispc_enable_channel -> dispc_mgr_enable The idea is to group manager related functions so that it can be deduced from the function name that it writes to manager spesific registers. All dispc_mgr_* functions have enum omap_channel as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:45:15 +00:00
unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAPDSS: DSI: use common DSS PLL support Now that we have the common DSS PLL support, change DSI to use it. This results in quite a lot of changes, but almost all of them are trivial name changes. The functions to calculate and program the PLL settings can be removed from dsi.c, as the common PLL API contains the same functionality. We also need to create struct dss_pll_hw entries for PLL hardware features for different OMAP platforms, instead of using the dss_features.c as the old code does. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-22 11:49:14 +00:00
struct dss_pll *pll;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
int lcd;
unsigned long r;
u32 l;
OMAPDSS: DISPC: fix dispc_mgr_lclk_rate for DIGIT output dispc_mgr_lclk_rate() cannot currently be called with DIGIT channel parameter, even if dispc_ovl_lclk_rate() can. Fix this by making dispc_mgr_lclk_rate() handle DIGIT channel also. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-23 08:50:10 +00:00
if (dss_mgr_is_lcd(channel)) {
l = dispc_read_reg(DISPC_DIVISORo(channel));
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: fix dispc_mgr_lclk_rate for DIGIT output dispc_mgr_lclk_rate() cannot currently be called with DIGIT channel parameter, even if dispc_ovl_lclk_rate() can. Fix this by making dispc_mgr_lclk_rate() handle DIGIT channel also. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-23 08:50:10 +00:00
lcd = FLD_GET(l, 23, 16);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: fix dispc_mgr_lclk_rate for DIGIT output dispc_mgr_lclk_rate() cannot currently be called with DIGIT channel parameter, even if dispc_ovl_lclk_rate() can. Fix this by making dispc_mgr_lclk_rate() handle DIGIT channel also. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-23 08:50:10 +00:00
switch (dss_get_lcd_clk_source(channel)) {
case OMAP_DSS_CLK_SRC_FCK:
OMAPDSS: DISPC: get dss clock rate from dss driver Dispc currently gets dispc's fck with clk_get() and uses clk_get_rate() to get the rate for scaling calculations. This causes a problem with common clock framework, as omapdss uses the dispc functions inside a spinlock, and common clock framework uses a mutex in clk_get_rate(). Looking at the DSS clock tree, the above use of the dispc fck is not quite correct. The DSS_FCLK from PRCM goes to DSS core block, which has a mux to select the clock for DISPC from various options, so the current use of dispc fck bypasses that. Fortunately we never change the dispc clock mux for now. To fix the issue with clk_get_rate(), this patch caches the dss clock rate in dss.c when it is set. Dispc will then ask for the clock rate from dss. While this is not very elegant, it does fix the issue, and it's not totally wrong when considering that the dispc fck actually comes via dss. In the future we should probably look into common clock framework and see if that could be used to represent the DSS clock tree properly. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-12-12 08:37:03 +00:00
r = dss_get_dispc_clk_rate();
OMAPDSS: DISPC: fix dispc_mgr_lclk_rate for DIGIT output dispc_mgr_lclk_rate() cannot currently be called with DIGIT channel parameter, even if dispc_ovl_lclk_rate() can. Fix this by making dispc_mgr_lclk_rate() handle DIGIT channel also. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-23 08:50:10 +00:00
break;
case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
OMAPDSS: DSI: use common DSS PLL support Now that we have the common DSS PLL support, change DSI to use it. This results in quite a lot of changes, but almost all of them are trivial name changes. The functions to calculate and program the PLL settings can be removed from dsi.c, as the common PLL API contains the same functionality. We also need to create struct dss_pll_hw entries for PLL hardware features for different OMAP platforms, instead of using the dss_features.c as the old code does. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-22 11:49:14 +00:00
pll = dss_pll_find("dsi0");
OMAPDSS: DISPC: Add DRA7xx support Add DRA7xx support to DISPC driver. The DISPC block is the same as on OMAP5, except the PLL's used for clocking are "videoX", not "dsiX". Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-12-31 09:25:48 +00:00
if (!pll)
pll = dss_pll_find("video0");
OMAPDSS: DSI: use common DSS PLL support Now that we have the common DSS PLL support, change DSI to use it. This results in quite a lot of changes, but almost all of them are trivial name changes. The functions to calculate and program the PLL settings can be removed from dsi.c, as the common PLL API contains the same functionality. We also need to create struct dss_pll_hw entries for PLL hardware features for different OMAP platforms, instead of using the dss_features.c as the old code does. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-22 11:49:14 +00:00
r = pll->cinfo.clkout[0];
OMAPDSS: DISPC: fix dispc_mgr_lclk_rate for DIGIT output dispc_mgr_lclk_rate() cannot currently be called with DIGIT channel parameter, even if dispc_ovl_lclk_rate() can. Fix this by making dispc_mgr_lclk_rate() handle DIGIT channel also. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-23 08:50:10 +00:00
break;
case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
OMAPDSS: DSI: use common DSS PLL support Now that we have the common DSS PLL support, change DSI to use it. This results in quite a lot of changes, but almost all of them are trivial name changes. The functions to calculate and program the PLL settings can be removed from dsi.c, as the common PLL API contains the same functionality. We also need to create struct dss_pll_hw entries for PLL hardware features for different OMAP platforms, instead of using the dss_features.c as the old code does. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-22 11:49:14 +00:00
pll = dss_pll_find("dsi1");
OMAPDSS: DISPC: Add DRA7xx support Add DRA7xx support to DISPC driver. The DISPC block is the same as on OMAP5, except the PLL's used for clocking are "videoX", not "dsiX". Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-12-31 09:25:48 +00:00
if (!pll)
pll = dss_pll_find("video1");
OMAPDSS: DSI: use common DSS PLL support Now that we have the common DSS PLL support, change DSI to use it. This results in quite a lot of changes, but almost all of them are trivial name changes. The functions to calculate and program the PLL settings can be removed from dsi.c, as the common PLL API contains the same functionality. We also need to create struct dss_pll_hw entries for PLL hardware features for different OMAP platforms, instead of using the dss_features.c as the old code does. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-22 11:49:14 +00:00
r = pll->cinfo.clkout[0];
OMAPDSS: DISPC: fix dispc_mgr_lclk_rate for DIGIT output dispc_mgr_lclk_rate() cannot currently be called with DIGIT channel parameter, even if dispc_ovl_lclk_rate() can. Fix this by making dispc_mgr_lclk_rate() handle DIGIT channel also. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-23 08:50:10 +00:00
break;
default:
BUG();
return 0;
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: fix dispc_mgr_lclk_rate for DIGIT output dispc_mgr_lclk_rate() cannot currently be called with DIGIT channel parameter, even if dispc_ovl_lclk_rate() can. Fix this by making dispc_mgr_lclk_rate() handle DIGIT channel also. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-23 08:50:10 +00:00
return r / lcd;
} else {
return dispc_fclk_rate();
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename manager related funcs Rename dispc's manager related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_mgr_* - Remove "channel" from the name, e.g. dispc_enable_channel -> dispc_mgr_enable The idea is to group manager related functions so that it can be deduced from the function name that it writes to manager spesific registers. All dispc_mgr_* functions have enum omap_channel as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:45:15 +00:00
unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
unsigned long r;
OMAPDSS: DISPC: Remove a redundant function dss_mgr_is_lcd() available in dss.h does the same thing as dispc_mgr_is_lcd() in dispc.c. Remove the function from dispc.c and replace it with the one in dss.h. Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-29 09:11:30 +00:00
if (dss_mgr_is_lcd(channel)) {
OMAPDSS: DISPC: Get correct pixel clock for TV manager dispc_mgr_pclk_rate() is used to calculate minimum required functional clock for scaling in calc_fclk() and calc_fclk_five_taps(). This function returns the correct pixel clock for LCD and LCD2 managers, but not for TV manager. Extend this function so that it gets the correct pixel clock for TV manager. This also prevents the crash we get when we try to scale overlays connected to TV manager. The current code leads to a BUG() being executed if we call dispc_mgr_pclk_rate() for the TV manager. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-13 12:58:41 +00:00
int pcd;
u32 l;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Get correct pixel clock for TV manager dispc_mgr_pclk_rate() is used to calculate minimum required functional clock for scaling in calc_fclk() and calc_fclk_five_taps(). This function returns the correct pixel clock for LCD and LCD2 managers, but not for TV manager. Extend this function so that it gets the correct pixel clock for TV manager. This also prevents the crash we get when we try to scale overlays connected to TV manager. The current code leads to a BUG() being executed if we call dispc_mgr_pclk_rate() for the TV manager. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-13 12:58:41 +00:00
l = dispc_read_reg(DISPC_DIVISORo(channel));
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Get correct pixel clock for TV manager dispc_mgr_pclk_rate() is used to calculate minimum required functional clock for scaling in calc_fclk() and calc_fclk_five_taps(). This function returns the correct pixel clock for LCD and LCD2 managers, but not for TV manager. Extend this function so that it gets the correct pixel clock for TV manager. This also prevents the crash we get when we try to scale overlays connected to TV manager. The current code leads to a BUG() being executed if we call dispc_mgr_pclk_rate() for the TV manager. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-13 12:58:41 +00:00
pcd = FLD_GET(l, 7, 0);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Get correct pixel clock for TV manager dispc_mgr_pclk_rate() is used to calculate minimum required functional clock for scaling in calc_fclk() and calc_fclk_five_taps(). This function returns the correct pixel clock for LCD and LCD2 managers, but not for TV manager. Extend this function so that it gets the correct pixel clock for TV manager. This also prevents the crash we get when we try to scale overlays connected to TV manager. The current code leads to a BUG() being executed if we call dispc_mgr_pclk_rate() for the TV manager. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-13 12:58:41 +00:00
r = dispc_mgr_lclk_rate(channel);
return r / pcd;
} else {
OMAPDSS: remove dispc's dependency to VENC/HDMI DISPC needs to know the clock rate for DIGIT (i.e. TV) channel, and this clock is provided by either VENC or HDMI modules. Currently DISPC will call a function in VENC/HDMI, asking what the clock rate is. This means we have a fixed dependency from DISPC to both VENC and HDMI. To have a more generic approach, and in particular to allow adding OMAP5 HDMI driver, we need to remove this dependency. This patch makes VENC/HDMI inform DISPC when the their clock changes, thus reversing the dependency and removing the issue. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-05-16 07:44:13 +00:00
return dispc.tv_pclk_rate;
OMAPDSS: DISPC: Get correct pixel clock for TV manager dispc_mgr_pclk_rate() is used to calculate minimum required functional clock for scaling in calc_fclk() and calc_fclk_five_taps(). This function returns the correct pixel clock for LCD and LCD2 managers, but not for TV manager. Extend this function so that it gets the correct pixel clock for TV manager. This also prevents the crash we get when we try to scale overlays connected to TV manager. The current code leads to a BUG() being executed if we call dispc_mgr_pclk_rate() for the TV manager. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-13 12:58:41 +00:00
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: remove dispc's dependency to VENC/HDMI DISPC needs to know the clock rate for DIGIT (i.e. TV) channel, and this clock is provided by either VENC or HDMI modules. Currently DISPC will call a function in VENC/HDMI, asking what the clock rate is. This means we have a fixed dependency from DISPC to both VENC and HDMI. To have a more generic approach, and in particular to allow adding OMAP5 HDMI driver, we need to remove this dependency. This patch makes VENC/HDMI inform DISPC when the their clock changes, thus reversing the dependency and removing the issue. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-05-16 07:44:13 +00:00
void dispc_set_tv_pclk(unsigned long pclk)
{
dispc.tv_pclk_rate = pclk;
}
OMAPDSS: DISPC: Correct DISPC functional clock usage DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC. DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC divisor LCD. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-23 06:46:50 +00:00
unsigned long dispc_core_clk_rate(void)
{
OMAPDSS: DISPC: store core clk rate Store dispc core clock rate so that it's available for calculations even if the HW is disabled. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-06 13:54:11 +00:00
return dispc.core_clk_rate;
OMAPDSS: DISPC: Correct DISPC functional clock usage DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC. DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC divisor LCD. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-04-23 06:46:50 +00:00
}
OMAPDSS: DISPC: Don't pass channel out when configuring overlays dispc_ovl_setup_common() is to be used by both overlays and writeback. We pass channel out to figure out what manager the overlay is connected to, to determine the pixel clock rate. This is used to decide the scaling limitations for that overlay. writeback doesn't have a channel out, it has a channel in field which tells where writeback gets its input from. These are 2 different fields, and this prevents us reusing the overlay configuration code for writeback. To overcome this, we now pass omap_plane to overlay related functions rather than passing channel out. We create helper functions which can derive pclk/lclk from the omap_plane id. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:28:52 +00:00
static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
{
OMAPDSS: DISPC: pclk & lclk rates for writeback Change the dispc_plane_pclk_rate and dispc_plane_lclk_rate functions to return 0 if the given plane is the writeback plane. The clocks are not valid for WB, but returning 0 from these functions instead of running into BUG() will simplify the code that uses these functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-15 11:20:02 +00:00
enum omap_channel channel;
if (plane == OMAP_DSS_WB)
return 0;
channel = dispc_ovl_get_channel_out(plane);
OMAPDSS: DISPC: Don't pass channel out when configuring overlays dispc_ovl_setup_common() is to be used by both overlays and writeback. We pass channel out to figure out what manager the overlay is connected to, to determine the pixel clock rate. This is used to decide the scaling limitations for that overlay. writeback doesn't have a channel out, it has a channel in field which tells where writeback gets its input from. These are 2 different fields, and this prevents us reusing the overlay configuration code for writeback. To overcome this, we now pass omap_plane to overlay related functions rather than passing channel out. We create helper functions which can derive pclk/lclk from the omap_plane id. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:28:52 +00:00
return dispc_mgr_pclk_rate(channel);
}
static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
{
OMAPDSS: DISPC: pclk & lclk rates for writeback Change the dispc_plane_pclk_rate and dispc_plane_lclk_rate functions to return 0 if the given plane is the writeback plane. The clocks are not valid for WB, but returning 0 from these functions instead of running into BUG() will simplify the code that uses these functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-15 11:20:02 +00:00
enum omap_channel channel;
if (plane == OMAP_DSS_WB)
return 0;
channel = dispc_ovl_get_channel_out(plane);
OMAPDSS: DISPC: Don't pass channel out when configuring overlays dispc_ovl_setup_common() is to be used by both overlays and writeback. We pass channel out to figure out what manager the overlay is connected to, to determine the pixel clock rate. This is used to decide the scaling limitations for that overlay. writeback doesn't have a channel out, it has a channel in field which tells where writeback gets its input from. These are 2 different fields, and this prevents us reusing the overlay configuration code for writeback. To overcome this, we now pass omap_plane to overlay related functions rather than passing channel out. We create helper functions which can derive pclk/lclk from the omap_plane id. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:28:52 +00:00
OMAPDSS: DISPC: fix dispc_mgr_lclk_rate for DIGIT output dispc_mgr_lclk_rate() cannot currently be called with DIGIT channel parameter, even if dispc_ovl_lclk_rate() can. Fix this by making dispc_mgr_lclk_rate() handle DIGIT channel also. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-23 08:50:10 +00:00
return dispc_mgr_lclk_rate(channel);
OMAPDSS: DISPC: Don't pass channel out when configuring overlays dispc_ovl_setup_common() is to be used by both overlays and writeback. We pass channel out to figure out what manager the overlay is connected to, to determine the pixel clock rate. This is used to decide the scaling limitations for that overlay. writeback doesn't have a channel out, it has a channel in field which tells where writeback gets its input from. These are 2 different fields, and this prevents us reusing the overlay configuration code for writeback. To overcome this, we now pass omap_plane to overlay related functions rather than passing channel out. We create helper functions which can derive pclk/lclk from the omap_plane id. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-26 11:28:52 +00:00
}
OMAPDSS: DISPC: fix dispc_mgr_lclk_rate for DIGIT output dispc_mgr_lclk_rate() cannot currently be called with DIGIT channel parameter, even if dispc_ovl_lclk_rate() can. Fix this by making dispc_mgr_lclk_rate() handle DIGIT channel also. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-23 08:50:10 +00:00
OMAPDSS: Add dump and debug support for LCD3 DISPC functions have been modified to provide clock and register dumps and debug support for the LCD3 manager. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:53:56 +00:00
static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
int lcd, pcd;
OMAPDSS: Add dump and debug support for LCD3 DISPC functions have been modified to provide clock and register dumps and debug support for the LCD3 manager. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:53:56 +00:00
enum omap_dss_clk_source lcd_clk_src;
seq_printf(s, "- %s -\n", mgr_desc[channel].name);
lcd_clk_src = dss_get_lcd_clk_source(channel);
seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
dss_get_generic_clk_source_name(lcd_clk_src),
dss_feat_get_clk_source_name(lcd_clk_src));
dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
dispc_mgr_lclk_rate(channel), lcd);
seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
dispc_mgr_pclk_rate(channel), pcd);
}
void dispc_dump_clocks(struct seq_file *s)
{
int lcd;
OMAP4: DSS2: Using dss_features to set independent core clock divider Using dss_features to select independent core clock divider and setting it. Added the register used, to DISPC context save and restore group ----------------------------------------------------------------------- In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as: DISPC_CORE_CLK >= max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...) Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the maximum horizontal downscaling done through MANAGERi Based on the usecase, core clk can be increased or decreased at runtime to save power. Such mechanism are not yet implemented. Hence, we set the core clock divisor to 1, to support maximum range of resolutions ------------------------------------------------------------------------ Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-03 15:28:00 +00:00
u32 l;
OMAP2PLUS: DSS2: Change enum "dss_clk_source" to "omap_dss_clk_source" Change enum dss_clk_source to omap_dss_clock_source and move it to 'plat/display.h'. Change the enum members to attach "OMAP_" in the beginning. These changes are done in order to specify the clock sources for DSS in the board file. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-04-12 08:22:23 +00:00
enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
if (dispc_runtime_get())
return;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
seq_printf(s, "- DISPC -\n");
OMAP2PLUS: DSS2: Use dss features to get clock source names of current OMAP Clock source names vary across OMAP2/3 and OMAP4, the clock source enum names have been made generic in the driver, but for purposes of debugging and dumping clock sources, it is better to preserve the actual TRM name of the clock. Introduce a dss feature function 'dss_feat_get_clk_source_name()' which returns a string with the TRM clock name for the current OMAP in use. The OMAP specific name is printed along the generic name within brackets. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-02 06:27:25 +00:00
seq_printf(s, "dispc fclk source = %s (%s)\n",
dss_get_generic_clk_source_name(dispc_clk_src),
dss_feat_get_clk_source_name(dispc_clk_src));
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
OMAP4: DSS2: Using dss_features to set independent core clock divider Using dss_features to select independent core clock divider and setting it. Added the register used, to DISPC context save and restore group ----------------------------------------------------------------------- In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as: DISPC_CORE_CLK >= max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...) Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the maximum horizontal downscaling done through MANAGERi Based on the usecase, core clk can be increased or decreased at runtime to save power. Such mechanism are not yet implemented. Hence, we set the core clock divisor to 1, to support maximum range of resolutions ------------------------------------------------------------------------ Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-03 15:28:00 +00:00
if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
seq_printf(s, "- DISPC-CORE-CLK -\n");
l = dispc_read_reg(DISPC_DIVISOR);
lcd = FLD_GET(l, 23, 16);
seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
(dispc_fclk_rate()/lcd), lcd);
}
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
OMAPDSS: Add dump and debug support for LCD3 DISPC functions have been modified to provide clock and register dumps and debug support for the LCD3 manager. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:53:56 +00:00
dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
OMAP4: DSS2: Clock source changes for OMAP4 On OMAP3, the pixel clock for the LCD manager was derived through DISPC_FCLK as: Lcd Pixel clock = DISPC_FCLK / lcd / pcd Where lcd and pcd are divisors in the DISPC_DIVISOR register. On OMAP4, the pixel clocks for LCD1 and LCD2 managers are derived from 2 new clocks named LCD1_CLK and LCD2_CLK. The pixel clocks are calculated as: Lcd_o Pixel clock = LCDo_CLK / lcdo /pcdo, o = 1, 2 Where lcdo and pcdo registers are divisors in DISPC_DIVISORo registers. LCD1_CLK and LCD2_CLK can have DSS_FCLK, and the M4 divider clocks of DSI1 PLL and DSI2 PLL as clock sources respectively. Introduce functions to select and get the clock source for these new clocks. Modify DISPC functions get the correct lck and pck rates based on the clock source of these clocks. Since OMAP2/3 don't have these clocks, force OMAP2/3 to always have the LCD_CLK source as DSS_CLK_SRC_FCK by introducing a dss feature. Introduce clock source names for OMAP4 and some register field changes in DSS_CTRL on OMAP4. Currently, LCD2_CLK can only have DSS_FCLK as its clock source as DSI2 PLL functionality hasn't been introduced yet. BUG for now if DSI2 PLL is selected as clock. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-08 11:50:35 +00:00
OMAPDSS: Add dump and debug support for LCD3 DISPC functions have been modified to provide clock and register dumps and debug support for the LCD3 manager. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:53:56 +00:00
if (dss_has_feature(FEAT_MGR_LCD2))
dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
if (dss_has_feature(FEAT_MGR_LCD3))
dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
dispc_runtime_put();
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: move the creation of debugfs files Instead of having an ugly #ifdef mess in the core.c for creating debugfs files, add a dss_debugfs_create_file() function that the dss drivers can use to create the debugfs files. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-03-02 16:01:07 +00:00
static void dispc_dump_regs(struct seq_file *s)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
int i, j;
const char *mgr_names[] = {
[OMAP_DSS_CHANNEL_LCD] = "LCD",
[OMAP_DSS_CHANNEL_DIGIT] = "TV",
[OMAP_DSS_CHANNEL_LCD2] = "LCD2",
OMAPDSS: Add dump and debug support for LCD3 DISPC functions have been modified to provide clock and register dumps and debug support for the LCD3 manager. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:53:56 +00:00
[OMAP_DSS_CHANNEL_LCD3] = "LCD3",
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
};
const char *ovl_names[] = {
[OMAP_DSS_GFX] = "GFX",
[OMAP_DSS_VIDEO1] = "VID1",
[OMAP_DSS_VIDEO2] = "VID2",
OMAPDSS: DISPC: VIDEO3 pipeline support Add support for VIDEO3 pipeline on OMAP4: - Add VIDEO3 pipeline information in dss_features and omapdss.h - Add VIDEO3 pipeline register coefficients in dispc.h - Create a new overlay structure corresponding to VIDEO3. - Make changes in dispc.c for VIDEO3 Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-13 12:50:33 +00:00
[OMAP_DSS_VIDEO3] = "VID3",
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
};
const char **p_names;
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
if (dispc_runtime_get())
return;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening Prepare dispc_dump_regs() to iterate over manager and overlay id's. Doing this requires modifications of the macro "DUMPREG" which currently needs us to specify the manager/overlay name to get the correct result. For example, in order to print the register DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), we can't iterate over a varaible i and get the desired result through DUMPREG(DISPC_TIMING_H(i)). Split the registers into 3 sections, the first with no arguments(common registers), the second with one argument(manager/overlay id), and the third with two arguments(overlay id and coefficient index), redefine DUMPREG macros for each of these. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:00 +00:00
/* DISPC common registers */
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
DUMPREG(DISPC_REVISION);
DUMPREG(DISPC_SYSCONFIG);
DUMPREG(DISPC_SYSSTATUS);
DUMPREG(DISPC_IRQSTATUS);
DUMPREG(DISPC_IRQENABLE);
DUMPREG(DISPC_CONTROL);
DUMPREG(DISPC_CONFIG);
DUMPREG(DISPC_CAPABLE);
DUMPREG(DISPC_LINE_STATUS);
DUMPREG(DISPC_LINE_NUMBER);
OMAPDSS/OMAP_VOUT: Fix incorrect OMAP3-alpha compatibility setting On OMAP3, in order to enable alpha blending for LCD and TV managers, we needed to set LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits in DISPC_CONFIG. On OMAP4, alpha blending is always enabled by default, if the above bits are set, we switch to an OMAP3 compatibility mode where the zorder values in the pipeline attribute registers are ignored and a fixed priority is configured. Rename the manager_info member "alpha_enabled" to "partial_alpha_enabled" for more clarity. Introduce two dss_features FEAT_ALPHA_FIXED_ZORDER and FEAT_ALPHA_FREE_ZORDER which represent OMAP3-alpha compatibility mode and OMAP4 alpha mode respectively. Introduce an overlay cap for ZORDER. The DSS2 user is expected to check for the ZORDER cap, if an overlay doesn't have this cap, the user is expected to set the parameter partial_alpha_enabled. If the overlay has ZORDER cap, the DSS2 user can assume that alpha blending is already enabled. Don't support OMAP3 compatibility mode for now. Trying to read/write to alpha_blending_enabled sysfs attribute issues a warning for OMAP4 and does not set the LCDALPHABLENDERENABLE/TVALPHABLENDERENABLE bits. Change alpha_enabled to partial_alpha_enabled in the omap_vout driver. Use overlay cap "OMAP_DSS_OVL_CAP_GLOBAL_ALPHA" to check if overlay supports alpha blending or not. Replace this with checks for VIDEO1 pipeline. Cc: linux-media@vger.kernel.org Cc: Lajos Molnar <molnar@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Acked-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-26 06:17:29 +00:00
if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
OMAP: DSS2: Add new FEAT definitions for features missing from OMAP2 OMAP2 doesn't have CPR, PRELOAD nor FIR_COEF_V registers. Add new feature definitions for those, and check the feature before accessing those registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 11:22:16 +00:00
DUMPREG(DISPC_GLOBAL_ALPHA);
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
if (dss_has_feature(FEAT_MGR_LCD2)) {
DUMPREG(DISPC_CONTROL2);
DUMPREG(DISPC_CONFIG2);
OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening Prepare dispc_dump_regs() to iterate over manager and overlay id's. Doing this requires modifications of the macro "DUMPREG" which currently needs us to specify the manager/overlay name to get the correct result. For example, in order to print the register DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), we can't iterate over a varaible i and get the desired result through DUMPREG(DISPC_TIMING_H(i)). Split the registers into 3 sections, the first with no arguments(common registers), the second with one argument(manager/overlay id), and the third with two arguments(overlay id and coefficient index), redefine DUMPREG macros for each of these. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:00 +00:00
}
OMAPDSS: Add dump and debug support for LCD3 DISPC functions have been modified to provide clock and register dumps and debug support for the LCD3 manager. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-06-21 05:53:56 +00:00
if (dss_has_feature(FEAT_MGR_LCD3)) {
DUMPREG(DISPC_CONTROL3);
DUMPREG(DISPC_CONFIG3);
}
OMAPDSS: DISPC: Add MFLAG defines OMAP5 has MFLAG feature in DISPC. Add the register definition and dump it. The register is not used yet, though. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-11-14 09:38:25 +00:00
if (dss_has_feature(FEAT_MFLAG))
DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening Prepare dispc_dump_regs() to iterate over manager and overlay id's. Doing this requires modifications of the macro "DUMPREG" which currently needs us to specify the manager/overlay name to get the correct result. For example, in order to print the register DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), we can't iterate over a varaible i and get the desired result through DUMPREG(DISPC_TIMING_H(i)). Split the registers into 3 sections, the first with no arguments(common registers), the second with one argument(manager/overlay id), and the third with two arguments(overlay id and coefficient index), redefine DUMPREG macros for each of these. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:00 +00:00
#undef DUMPREG
#define DISPC_REG(i, name) name(i)
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
OMAPDSS: fix compilation warnings When compiling on x86 we get following warnings: warning: field width specifier ‘*’ expects argument of type ‘int’, but argument 5 has type ‘size_t’ [-Wformat] Fix these by casting the size_t to int. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-28 10:58:14 +00:00
(int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening Prepare dispc_dump_regs() to iterate over manager and overlay id's. Doing this requires modifications of the macro "DUMPREG" which currently needs us to specify the manager/overlay name to get the correct result. For example, in order to print the register DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), we can't iterate over a varaible i and get the desired result through DUMPREG(DISPC_TIMING_H(i)). Split the registers into 3 sections, the first with no arguments(common registers), the second with one argument(manager/overlay id), and the third with two arguments(overlay id and coefficient index), redefine DUMPREG macros for each of these. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:00 +00:00
dispc_read_reg(DISPC_REG(i, r)))
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
p_names = mgr_names;
OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening Prepare dispc_dump_regs() to iterate over manager and overlay id's. Doing this requires modifications of the macro "DUMPREG" which currently needs us to specify the manager/overlay name to get the correct result. For example, in order to print the register DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), we can't iterate over a varaible i and get the desired result through DUMPREG(DISPC_TIMING_H(i)). Split the registers into 3 sections, the first with no arguments(common registers), the second with one argument(manager/overlay id), and the third with two arguments(overlay id and coefficient index), redefine DUMPREG macros for each of these. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:00 +00:00
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
/* DISPC channel specific registers */
for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
DUMPREG(i, DISPC_DEFAULT_COLOR);
DUMPREG(i, DISPC_TRANS_COLOR);
DUMPREG(i, DISPC_SIZE_MGR);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
if (i == OMAP_DSS_CHANNEL_DIGIT)
continue;
OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening Prepare dispc_dump_regs() to iterate over manager and overlay id's. Doing this requires modifications of the macro "DUMPREG" which currently needs us to specify the manager/overlay name to get the correct result. For example, in order to print the register DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), we can't iterate over a varaible i and get the desired result through DUMPREG(DISPC_TIMING_H(i)). Split the registers into 3 sections, the first with no arguments(common registers), the second with one argument(manager/overlay id), and the third with two arguments(overlay id and coefficient index), redefine DUMPREG macros for each of these. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:00 +00:00
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
DUMPREG(i, DISPC_TIMING_H);
DUMPREG(i, DISPC_TIMING_V);
DUMPREG(i, DISPC_POL_FREQ);
DUMPREG(i, DISPC_DIVISORo);
OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening Prepare dispc_dump_regs() to iterate over manager and overlay id's. Doing this requires modifications of the macro "DUMPREG" which currently needs us to specify the manager/overlay name to get the correct result. For example, in order to print the register DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), we can't iterate over a varaible i and get the desired result through DUMPREG(DISPC_TIMING_H(i)). Split the registers into 3 sections, the first with no arguments(common registers), the second with one argument(manager/overlay id), and the third with two arguments(overlay id and coefficient index), redefine DUMPREG macros for each of these. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:00 +00:00
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
DUMPREG(i, DISPC_DATA_CYCLE1);
DUMPREG(i, DISPC_DATA_CYCLE2);
DUMPREG(i, DISPC_DATA_CYCLE3);
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
OMAP: DSS2: Add new FEAT definitions for features missing from OMAP2 OMAP2 doesn't have CPR, PRELOAD nor FIR_COEF_V registers. Add new feature definitions for those, and check the feature before accessing those registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 11:22:16 +00:00
if (dss_has_feature(FEAT_CPR)) {
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
DUMPREG(i, DISPC_CPR_COEF_R);
DUMPREG(i, DISPC_CPR_COEF_G);
DUMPREG(i, DISPC_CPR_COEF_B);
OMAP: DSS2: Add new FEAT definitions for features missing from OMAP2 OMAP2 doesn't have CPR, PRELOAD nor FIR_COEF_V registers. Add new feature definitions for those, and check the feature before accessing those registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 11:22:16 +00:00
}
OMAP: DSS2: LCD2 Channel Changes for DISPC DISPC functions are modified in order to work when the manager is LCD2. This includes: Adding new IRQs specific to LCD2 and their handling. Provide dumps of the new manager's registers. Provide dumps of the new manager's clocks. Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2 which can't be parametrized. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:12 +00:00
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
p_names = ovl_names;
for (i = 0; i < dss_feat_get_num_ovls(); i++) {
DUMPREG(i, DISPC_OVL_BA0);
DUMPREG(i, DISPC_OVL_BA1);
DUMPREG(i, DISPC_OVL_POSITION);
DUMPREG(i, DISPC_OVL_SIZE);
DUMPREG(i, DISPC_OVL_ATTRIBUTES);
DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
DUMPREG(i, DISPC_OVL_ROW_INC);
DUMPREG(i, DISPC_OVL_PIXEL_INC);
OMAPDSS: fix dispc register dump for preload & mflag Preload register is dumped twice for video overlays and mflag register is not dumped for GFX. Fix the register dump. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-09-29 20:46:16 +00:00
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
if (dss_has_feature(FEAT_PRELOAD))
DUMPREG(i, DISPC_OVL_PRELOAD);
OMAPDSS: fix dispc register dump for preload & mflag Preload register is dumped twice for video overlays and mflag register is not dumped for GFX. Fix the register dump. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-09-29 20:46:16 +00:00
if (dss_has_feature(FEAT_MFLAG))
DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
if (i == OMAP_DSS_GFX) {
DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
DUMPREG(i, DISPC_OVL_TABLE_BA);
continue;
}
DUMPREG(i, DISPC_OVL_FIR);
DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
DUMPREG(i, DISPC_OVL_ACCU0);
DUMPREG(i, DISPC_OVL_ACCU1);
if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
DUMPREG(i, DISPC_OVL_BA0_UV);
DUMPREG(i, DISPC_OVL_BA1_UV);
DUMPREG(i, DISPC_OVL_FIR2);
DUMPREG(i, DISPC_OVL_ACCU2_0);
DUMPREG(i, DISPC_OVL_ACCU2_1);
}
if (dss_has_feature(FEAT_ATTR2))
DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
}
OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening Prepare dispc_dump_regs() to iterate over manager and overlay id's. Doing this requires modifications of the macro "DUMPREG" which currently needs us to specify the manager/overlay name to get the correct result. For example, in order to print the register DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), we can't iterate over a varaible i and get the desired result through DUMPREG(DISPC_TIMING_H(i)). Split the registers into 3 sections, the first with no arguments(common registers), the second with one argument(manager/overlay id), and the third with two arguments(overlay id and coefficient index), redefine DUMPREG macros for each of these. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:00 +00:00
#undef DISPC_REG
#undef DUMPREG
#define DISPC_REG(plane, name, i) name(plane, i)
#define DUMPREG(plane, name, i) \
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
OMAPDSS: fix compilation warnings When compiling on x86 we get following warnings: warning: field width specifier ‘*’ expects argument of type ‘int’, but argument 5 has type ‘size_t’ [-Wformat] Fix these by casting the size_t to int. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-28 10:58:14 +00:00
(int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening Prepare dispc_dump_regs() to iterate over manager and overlay id's. Doing this requires modifications of the macro "DUMPREG" which currently needs us to specify the manager/overlay name to get the correct result. For example, in order to print the register DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), we can't iterate over a varaible i and get the desired result through DUMPREG(DISPC_TIMING_H(i)). Split the registers into 3 sections, the first with no arguments(common registers), the second with one argument(manager/overlay id), and the third with two arguments(overlay id and coefficient index), redefine DUMPREG macros for each of these. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:00 +00:00
dispc_read_reg(DISPC_REG(plane, name, i)))
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
/* Video pipeline coefficient registers */
OMAP: DSS2: Add new FEAT definitions for features missing from OMAP2 OMAP2 doesn't have CPR, PRELOAD nor FIR_COEF_V registers. Add new feature definitions for those, and check the feature before accessing those registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 11:22:16 +00:00
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
/* start from OMAP_DSS_VIDEO1 */
for (i = 1; i < dss_feat_get_num_ovls(); i++) {
for (j = 0; j < 8; j++)
DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
OMAP: DSS2: Clean up DISPC overlay register definitions Move all DISPC register definitions to a new header dispc.h. There are separate register offset definitions for GFX, VID1 and VID2 pipeline share register definitions by using an argument. The introduction of VID3 pipeline on OMAP4 will not let us use the above method since VID3 pipe register offsets don't map with VID1 and VID2 offsets. Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument tells the overlay. Register offsets are calculated as: DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane) Idea suggested by Tomi Valkeinen. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-06 06:15:49 +00:00
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
for (j = 0; j < 8; j++)
DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening Prepare dispc_dump_regs() to iterate over manager and overlay id's. Doing this requires modifications of the macro "DUMPREG" which currently needs us to specify the manager/overlay name to get the correct result. For example, in order to print the register DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), we can't iterate over a varaible i and get the desired result through DUMPREG(DISPC_TIMING_H(i)). Split the registers into 3 sections, the first with no arguments(common registers), the second with one argument(manager/overlay id), and the third with two arguments(overlay id and coefficient index), redefine DUMPREG macros for each of these. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:00 +00:00
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
for (j = 0; j < 5; j++)
DUMPREG(i, DISPC_OVL_CONV_COEF, j);
OMAP: DSS2: Add new registers for NV12 support Add new registers specific to UV color component that are introduced in OMAP4. Add simple helper functions to configure the newly added registers. These new registers are mainly: - UV base address registers used specifically for NV12 color-format - FIR registers used for UV-color-component scaling on OMAP4 - Accumulator registers used for UV-color-component scaling Add these new registers to save/restore and DUMPREG functions. Also add two new features for OMAP4: - FEAT_HANDLE_UV_SEPARATE - this is used on OMAP4 as UV color-component requires separate handling. - FEAT_ATTR2 - this is used on OMAP4 to configure new ATTRIBUTES2 register. Signed-off-by: Amber Jain <amber@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-19 14:17:53 +00:00
OMAP: DSS2: DISPC: Shorten dispc_dump_regs() Iterate over manager and overlay id's to shorten dispc_dump_regs(). Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:01 +00:00
if (dss_has_feature(FEAT_FIR_COEF_V)) {
for (j = 0; j < 8; j++)
DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
}
if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
for (j = 0; j < 8; j++)
DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
for (j = 0; j < 8; j++)
DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
for (j = 0; j < 8; j++)
DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
}
OMAP: DSS2: Add new FEAT definitions for features missing from OMAP2 OMAP2 doesn't have CPR, PRELOAD nor FIR_COEF_V registers. Add new feature definitions for those, and check the feature before accessing those registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 11:22:16 +00:00
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
dispc_runtime_put();
OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening Prepare dispc_dump_regs() to iterate over manager and overlay id's. Doing this requires modifications of the macro "DUMPREG" which currently needs us to specify the manager/overlay name to get the correct result. For example, in order to print the register DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), we can't iterate over a varaible i and get the desired result through DUMPREG(DISPC_TIMING_H(i)). Split the registers into 3 sections, the first with no arguments(common registers), the second with one argument(manager/overlay id), and the third with two arguments(overlay id and coefficient index), redefine DUMPREG macros for each of these. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-05 13:36:00 +00:00
#undef DISPC_REG
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
#undef DUMPREG
}
/* calculate clock rates using dividers in cinfo */
int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
struct dispc_clock_info *cinfo)
{
if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
return -EINVAL;
OMAP: DSS2: DISPC: Fix minimum PCD value The current driver had a hardcoded minimum value of 2 for pixel clock divisor (PCD). This doesn't seem to be right. OMAP4 TRM says that PCD can be 1 when not downscaling, and inverted pixel clock (IPC) is off. OMAP3 TRM says the same, but also in the register descriptions that PCD value 1 is invalid. OMAP2 TRM says PCD 2 is the minimum. OMAP2 is still untested, but for both OMAP3 and OMAP4 PCD of 1 seems to work fine. This patch adds a new DSS feature, FEAT_PARAM_DSS_PCD, which is used to find the minimum and maximum PCD. The minimum is set to 2 for OMAP2, and 1 for OMAP3/4. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-29 12:56:04 +00:00
if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
return -EINVAL;
cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
cinfo->pck = cinfo->lck / cinfo->pck_div;
OMAP: DSS2: DISPC: Fix minimum PCD value The current driver had a hardcoded minimum value of 2 for pixel clock divisor (PCD). This doesn't seem to be right. OMAP4 TRM says that PCD can be 1 when not downscaling, and inverted pixel clock (IPC) is off. OMAP3 TRM says the same, but also in the register descriptions that PCD value 1 is invalid. OMAP2 TRM says PCD 2 is the minimum. OMAP2 is still untested, but for both OMAP3 and OMAP4 PCD of 1 seems to work fine. This patch adds a new DSS feature, FEAT_PARAM_DSS_PCD, which is used to find the minimum and maximum PCD. The minimum is set to 2 for OMAP2, and 1 for OMAP3/4. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-29 12:56:04 +00:00
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
return 0;
}
OMAPDSS: DISPC: add new clock calculation code Add new way to iterate over DISPC clock divisors. dispc_div_calc() provides a generic way to go over all the divisors, within given pixel clock range. dispc_div_calc() will call a callback function for each divider set, making the function reusable for all use cases. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-05 14:32:08 +00:00
bool dispc_div_calc(unsigned long dispc,
unsigned long pck_min, unsigned long pck_max,
dispc_div_calc_func func, void *data)
{
int lckd, lckd_start, lckd_stop;
int pckd, pckd_start, pckd_stop;
unsigned long pck, lck;
unsigned long lck_max;
unsigned long pckd_hw_min, pckd_hw_max;
unsigned min_fck_per_pck;
unsigned long fck;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: add new clock calculation code Add new way to iterate over DISPC clock divisors. dispc_div_calc() provides a generic way to go over all the divisors, within given pixel clock range. dispc_div_calc() will call a callback function for each divider set, making the function reusable for all use cases. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-05 14:32:08 +00:00
#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
#else
min_fck_per_pck = 0;
#endif
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: add new clock calculation code Add new way to iterate over DISPC clock divisors. dispc_div_calc() provides a generic way to go over all the divisors, within given pixel clock range. dispc_div_calc() will call a callback function for each divider set, making the function reusable for all use cases. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-05 14:32:08 +00:00
pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: add new clock calculation code Add new way to iterate over DISPC clock divisors. dispc_div_calc() provides a generic way to go over all the divisors, within given pixel clock range. dispc_div_calc() will call a callback function for each divider set, making the function reusable for all use cases. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-05 14:32:08 +00:00
lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: add new clock calculation code Add new way to iterate over DISPC clock divisors. dispc_div_calc() provides a generic way to go over all the divisors, within given pixel clock range. dispc_div_calc() will call a callback function for each divider set, making the function reusable for all use cases. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-05 14:32:08 +00:00
pck_min = pck_min ? pck_min : 1;
pck_max = pck_max ? pck_max : ULONG_MAX;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: add new clock calculation code Add new way to iterate over DISPC clock divisors. dispc_div_calc() provides a generic way to go over all the divisors, within given pixel clock range. dispc_div_calc() will call a callback function for each divider set, making the function reusable for all use cases. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-05 14:32:08 +00:00
lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
lckd_stop = min(dispc / pck_min, 255ul);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: add new clock calculation code Add new way to iterate over DISPC clock divisors. dispc_div_calc() provides a generic way to go over all the divisors, within given pixel clock range. dispc_div_calc() will call a callback function for each divider set, making the function reusable for all use cases. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-05 14:32:08 +00:00
for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
lck = dispc / lckd;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: add new clock calculation code Add new way to iterate over DISPC clock divisors. dispc_div_calc() provides a generic way to go over all the divisors, within given pixel clock range. dispc_div_calc() will call a callback function for each divider set, making the function reusable for all use cases. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-05 14:32:08 +00:00
pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
pckd_stop = min(lck / pck_min, pckd_hw_max);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: add new clock calculation code Add new way to iterate over DISPC clock divisors. dispc_div_calc() provides a generic way to go over all the divisors, within given pixel clock range. dispc_div_calc() will call a callback function for each divider set, making the function reusable for all use cases. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-05 14:32:08 +00:00
for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
pck = lck / pckd;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: add new clock calculation code Add new way to iterate over DISPC clock divisors. dispc_div_calc() provides a generic way to go over all the divisors, within given pixel clock range. dispc_div_calc() will call a callback function for each divider set, making the function reusable for all use cases. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-05 14:32:08 +00:00
/*
* For OMAP2/3 the DISPC fclk is the same as LCD's logic
* clock, which means we're configuring DISPC fclk here
* also. Thus we need to use the calculated lck. For
* OMAP4+ the DISPC fclk is a separate clock.
*/
if (dss_has_feature(FEAT_CORE_CLK_DIV))
fck = dispc_core_clk_rate();
else
fck = lck;
if (fck < pck * min_fck_per_pck)
continue;
if (func(lckd, pckd, lck, pck, data))
return true;
}
}
return false;
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: DISPC: Change return type of dispc_mgr_set_clock_div() dipsc_mgr_set_clock div has an int return type to report errors or success. The function doesn't really check for errors and always returns 0. Change the return type to void. Checking for the correct DISPC clock divider ranges will be done when a DSS2 user does a manager apply. This support will be added later. Signed-off-by: Archit Taneja <archit@ti.com>
2012-06-29 08:30:54 +00:00
void dispc_mgr_set_clock_div(enum omap_channel channel,
OMAPDSS: DISPC: constify function parameters Add consts to dispc function parameters which do not modify the passed structs. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-03 07:09:11 +00:00
const struct dispc_clock_info *cinfo)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
OMAP: DSS2: DISPC: rename manager related funcs Rename dispc's manager related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_mgr_* - Remove "channel" from the name, e.g. dispc_enable_channel -> dispc_mgr_enable The idea is to group manager related functions so that it can be deduced from the function name that it writes to manager spesific registers. All dispc_mgr_* functions have enum omap_channel as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:45:15 +00:00
dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAP: DSS2: DISPC: rename manager related funcs Rename dispc's manager related functions as follows: - Remove prepending underscores, which were originally used to inform that the clocks needs to be enabled. This meaning is no longer valid. - Prepend the functions with dispc_mgr_* - Remove "channel" from the name, e.g. dispc_enable_channel -> dispc_mgr_enable The idea is to group manager related functions so that it can be deduced from the function name that it writes to manager spesific registers. All dispc_mgr_* functions have enum omap_channel as the first parameter. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-08-16 10:45:15 +00:00
int dispc_mgr_get_clock_div(enum omap_channel channel,
OMAP: DSS2: Change remaining DISPC functions for new omap_channel argument The following dispc functions are also changed to incorporate channel as an argument: -dispc_lclk_rate() -dispc_pclk_rate() -dispc_set_pol_freq() -dispc_set_clock_div() -dispc_get_clock_div() Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> [tomi.valkeinen@nokia.com: fixed trivial compile error] Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:11 +00:00
struct dispc_clock_info *cinfo)
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
{
unsigned long fck;
fck = dispc_fclk_rate();
OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch) The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR. However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK independent of Primary and Secondary display clocks. Renamed DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch), to facilitate introduction of DISPC_DIVISOR register, which is specific for OMAP4. OMAP4 has 3 registers DISPC_DIVISOR, DISPC_DIVISOR1 and DISPC_DIVISOR2. Also updated, all the usages of DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch). Use DISPC_DIVISORo(ch) when DISPC_DIVISOR1 or DISPC_DIVISOR2 has to be configured OMAP4 TRM uses DISPC_DIVISORo generically to refer to DISPC_DIVISOR1 and DISPC_DIVISOR2 Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-03 15:27:59 +00:00
cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
cinfo->lck = fck / cinfo->lck_div;
cinfo->pck = cinfo->lck / cinfo->pck_div;
return 0;
}
OMAPDSS: DISPC: Add IRQ enable/status helpers DISPC irqs need to be handled from the compat layer and also in the future by the omapdrm. To make this possible, this patchs adds a set of helper functions, so that the irqs can be managed without direct register reads/writes. The following functions are added, and all the current direct reg reads/writes are changed to use these. u32 dispc_read_irqstatus(void); void dispc_clear_irqstatus(u32 mask); u32 dispc_read_irqenable(void); void dispc_write_irqenable(u32 mask); Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 12:13:14 +00:00
u32 dispc_read_irqstatus(void)
{
return dispc_read_reg(DISPC_IRQSTATUS);
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_read_irqstatus);
OMAPDSS: DISPC: Add IRQ enable/status helpers DISPC irqs need to be handled from the compat layer and also in the future by the omapdrm. To make this possible, this patchs adds a set of helper functions, so that the irqs can be managed without direct register reads/writes. The following functions are added, and all the current direct reg reads/writes are changed to use these. u32 dispc_read_irqstatus(void); void dispc_clear_irqstatus(u32 mask); u32 dispc_read_irqenable(void); void dispc_write_irqenable(u32 mask); Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 12:13:14 +00:00
void dispc_clear_irqstatus(u32 mask)
{
dispc_write_reg(DISPC_IRQSTATUS, mask);
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_clear_irqstatus);
OMAPDSS: DISPC: Add IRQ enable/status helpers DISPC irqs need to be handled from the compat layer and also in the future by the omapdrm. To make this possible, this patchs adds a set of helper functions, so that the irqs can be managed without direct register reads/writes. The following functions are added, and all the current direct reg reads/writes are changed to use these. u32 dispc_read_irqstatus(void); void dispc_clear_irqstatus(u32 mask); u32 dispc_read_irqenable(void); void dispc_write_irqenable(u32 mask); Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 12:13:14 +00:00
u32 dispc_read_irqenable(void)
{
return dispc_read_reg(DISPC_IRQENABLE);
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_read_irqenable);
OMAPDSS: DISPC: Add IRQ enable/status helpers DISPC irqs need to be handled from the compat layer and also in the future by the omapdrm. To make this possible, this patchs adds a set of helper functions, so that the irqs can be managed without direct register reads/writes. The following functions are added, and all the current direct reg reads/writes are changed to use these. u32 dispc_read_irqstatus(void); void dispc_clear_irqstatus(u32 mask); u32 dispc_read_irqenable(void); void dispc_write_irqenable(u32 mask); Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 12:13:14 +00:00
void dispc_write_irqenable(u32 mask)
{
u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
/* clear the irqstatus for newly enabled irqs */
dispc_clear_irqstatus((mask ^ old_mask) & mask);
dispc_write_reg(DISPC_IRQENABLE, mask);
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_write_irqenable);
OMAPDSS: DISPC: Add IRQ enable/status helpers DISPC irqs need to be handled from the compat layer and also in the future by the omapdrm. To make this possible, this patchs adds a set of helper functions, so that the irqs can be managed without direct register reads/writes. The following functions are added, and all the current direct reg reads/writes are changed to use these. u32 dispc_read_irqstatus(void); void dispc_clear_irqstatus(u32 mask); u32 dispc_read_irqenable(void); void dispc_write_irqenable(u32 mask); Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 12:13:14 +00:00
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
void dispc_enable_sidle(void)
{
REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
}
void dispc_disable_sidle(void)
{
REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
}
static void _omap_dispc_initial_config(void)
{
u32 l;
OMAP4: DSS2: Using dss_features to set independent core clock divider Using dss_features to select independent core clock divider and setting it. Added the register used, to DISPC context save and restore group ----------------------------------------------------------------------- In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as: DISPC_CORE_CLK >= max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...) Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the maximum horizontal downscaling done through MANAGERi Based on the usecase, core clk can be increased or decreased at runtime to save power. Such mechanism are not yet implemented. Hence, we set the core clock divisor to 1, to support maximum range of resolutions ------------------------------------------------------------------------ Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-03 15:28:00 +00:00
/* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
l = dispc_read_reg(DISPC_DIVISOR);
/* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
l = FLD_MOD(l, 1, 0, 0);
l = FLD_MOD(l, 1, 23, 16);
dispc_write_reg(DISPC_DIVISOR, l);
OMAPDSS: DISPC: store core clk rate Store dispc core clock rate so that it's available for calculations even if the HW is disabled. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-06 13:54:11 +00:00
dispc.core_clk_rate = dispc_fclk_rate();
OMAP4: DSS2: Using dss_features to set independent core clock divider Using dss_features to select independent core clock divider and setting it. Added the register used, to DISPC context save and restore group ----------------------------------------------------------------------- In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as: DISPC_CORE_CLK >= max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...) Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the maximum horizontal downscaling done through MANAGERi Based on the usecase, core clk can be increased or decreased at runtime to save power. Such mechanism are not yet implemented. Hence, we set the core clock divisor to 1, to support maximum range of resolutions ------------------------------------------------------------------------ Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-03-03 15:28:00 +00:00
}
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
/* FUNCGATED */
OMAP: DSS2: Use dss_features to handle DISPC bits removed on OMAP4 DISPC_CONFIG bits LCDENABLEPOL, LCDENABLESIGNAL, PCKFREEENABLE and FUNCGATED have been removed from OMAP4, use dss_features to handle them correctly. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2010-12-02 11:27:13 +00:00
if (dss_has_feature(FEAT_FUNCGATED))
REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
OMAPDSS: DISPC: Configure color conversion coefficients for writeback Writeback pipeline receives RGB data from one of the overlays or one of the overlay managers. If the target color mode is YUV422 or NV12, we need to convert the RGB pixels to YUV. The scaler in WB then converts it to the target color mode. Hence, the color conversion coefficients that need to be programmed are the ones which convert a RGB24 pixel to YUV444. Program these coefficients for writeback pipeline. Rearrange the code a bit to configure different coefficients for overlays and writeback. Signed-off-by: Archit Taneja <archit@ti.com>
2012-09-11 06:34:47 +00:00
dispc_setup_color_conv_coef();
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
OMAPDSS: Improve fifo management code OMAP4+ allows assigning the overlay FIFOs freely, but that is not supported by omapdss yet. This patch takes a step forward by improving the fifo management to be more flexible. dispc.c is changed to keep track of the sizes of each fifo, and also the overlay using each fifo. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:56:57 +00:00
dispc_init_fifos();
OMAP: DSS2: Fix FIFO threshold and burst size for OMAP4 The DMA FIFO threshold registers and burst size registers have changed for OMAP4. The current code only handles OMAP2/3 case, and so the values are a bit off for OMAP4. A summary of the differences between OMAP2/3 and OMAP4: Burst size: OMAP2/3: 4 x 32 bits / 8 x 32 bits / 16 x 32 bits OMAP4: 2 x 128 bits / 4 x 128 bits / 8 x 128 bits Threshold size: OMAP2/3: in bytes (8 bit units) OMAP4: in 128bit units This patch fixes the issue by creating two new helper functions in dss_features: dss_feat_get_buffer_size_unit() and dss_feat_get_burst_size_unit(). These return (in bytes) the unit size for threshold registers and unit size for burst size register, respectively, and are used to calculate correct values. For the threshold size the usage is straightforward. However, the burst size register has different multipliers for OMAP2/3 and OMAP4. This patch solves the problem by defining the multipliers for the burst size as 2x, 4x and 8x, which fit fine for the OMAP4 burst size definition (i.e. burst size unit for OMAP4 is 128bits), but requires a slight twist on OMAP2/3 by defining the burst size unit as 64bit. As the driver in practice always uses the maximum burst size, and no use case currently exists where we would want to use a smaller burst size, this patch changes the driver to hardcode the burst size when initializing DISPC. This makes the threshold configuration code somewhat simpler. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-06-21 06:35:36 +00:00
dispc_configure_burst_sizes();
OMAPDSS: DISPC: zorder support for DSS overlays Add zorder support on OMAP4, this feature allows deciding the visibility order of the overlays based on the zorder value provided as an overlay info parameter or a sysfs attribute of the overlay object. Use the overlay cap OMAP_DSS_OVL_CAP_ZORDER to determine whether zorder is supported for the overlay or not. Use dss feature FEAT_ALPHA_FREE_ZORDER if the caps are not available. Ensure that all overlays that are enabled and connected to the same manager have different zorders. Swapping zorders of 2 enabled overlays currently requires disabling one of the overlays. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-09-08 05:59:17 +00:00
dispc_ovl_enable_zorder_planes();
OMAPDSS: DISPC: Revert to older DISPC Smart Standby mechanism for OMAP5 DISPC on OMAP5 has a more optimised mechanism of asserting Mstandby to achieve more power savings when DISPC is configured in Smart Standby mode. This mechanism leads to underflows when multiple DISPC pipes are enabled. There is a register field which can let us revert to the older mechanism of asserting Mstandby. Configure this field to prevent underflows. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:25 +00:00
if (dispc.feat->mstandby_workaround)
REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
OMAPDSS: Add support for MFLAG OMAP5 has support for MFLAG feature, which allows DSS to dynamically increase the priority of DISPC's DMA traffic. At the moment we don't have support for it. It was noticed that on DRA7 with high bandwidth use cases we see FIFO underflows. Implementing MFLAG support removed those underflows. Interestingly, on OMAP5 uEVM no such overflows were seen. This patch adds a simple MFLAG implementation, where we use a fixed MFLAG threshold value based on the FIFO size. The thresholds are set to 4/8 of fifo size for low threshold, and 5/8 of fifo size for high threshold. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-09-29 20:46:18 +00:00
if (dss_has_feature(FEAT_MFLAG))
dispc_init_mflag();
OMAP: DSS2: DISPC This file implements DISPC (display controller) block of the OMAP DSS. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2009-11-12 09:41:42 +00:00
}
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
static const struct dispc_features omap24xx_dispc_feats __initconst = {
.sw_start = 5,
.fp_start = 15,
.bp_start = 27,
.sw_max = 64,
.vp_max = 255,
.hp_max = 256,
OMAPDSS: Add overlay manager width and height limits as a dispc feature The overlay manager width and height vary in OMAP5 from previous OMAPs in terms of maximum limit and register field positions. Add parameters in dispc_features for these. Also remove params related to manager width and height from dss_features, as we want to maintain a feature list for individual IPs. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-14 08:20:15 +00:00
.mgr_width_start = 10,
.mgr_height_start = 26,
.mgr_width_max = 2048,
.mgr_height_max = 2048,
omapdss: DISPC: add max pixel clock limits for LCD and TV managers Each version of OMAP has a limitation on the maximum pixel clock frequency supported by an overlay manager. This limit isn't checked by omapdss. Add dispc feats for lcd and tv managers and check whether the target timings can be supported or not. The pixel clock limitations are actually more complex. They depend on which OPP OMAP is in, and they also depend on which encoder is the manager connected to. The OPP dependence is ignored as DSS forces the PM framework to be on OPP100 when DSS is enabled, and the encoder dependencies are ignored by DISPC for now. These limits should come from the encoder driver. The OMAP2 TRM doesn't mention the maximum pixel clock limit. This value is left as half of DSS_FCLK, as OMAP2 requires the PCD to be atleast 2. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:22 +00:00
.max_lcd_pclk = 66500000,
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
.calc_scaling = dispc_ovl_calc_scaling_24xx,
.calc_core_clk = calc_core_clk_24xx,
OMAPDSS: Improve fifo management code OMAP4+ allows assigning the overlay FIFOs freely, but that is not supported by omapdss yet. This patch takes a step forward by improving the fifo management to be more flexible. dispc.c is changed to keep track of the sizes of each fifo, and also the overlay using each fifo. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:56:57 +00:00
.num_fifos = 3,
OMAPDSS: DISPC: add no_framedone_tv feat OMAP2/3 do not have FRAMEDONETV irq, but later omaps do. We currently always return 0 from dispc_mgr_get_framedone_irq() for TV output to be compatible with OMAP2/3. This patch implements "no_framedone_tv" dispc-feature that is used in dispc_mgr_get_framedone_irq to return either 0 for OMAP2/3, or the correct IRQ number for FRAMEDONETV on OMAP4+. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-08 08:01:33 +00:00
.no_framedone_tv = true,
OMAPDSS: DISPC: Preload more data in pipeline DMAs for OMAP4+ SoCs DISPC pipeline DMAs preload some bytes of pixel data in the vertical blanking region before the start of each frame. The preload ensures the pipeline doesn't underflow when the active region of the display starts. DISPC_GFX/VIDp_PRELOAD registers allow us to program how many bytes of data should be preloaded for each pipeline. Calculating a precise preload value would be a complex function of the pixel clock of the connected display, the vertical blanking duration and the interconnect traffic at that instance. If the register is left untouched, a default value is preloaded. We observe underflows for OMAP4+ SoCs for certain bandwidth intensive use cases with many other initiators active, and in situations where memory access isn't very efficient(like accessing Tiler mapped buffers and EMIF configured in non-interleaved more). The cause of the underflow is because the default preload value isn't sufficient for the DMA to reach a steady state. We configure the PRELOAD register such that the pipelines preload data up to the high threshold of the FIFO. Preloading lot of data for older SoCs can have a negative impact. Due to slower interconnects, it's possible that the DISPC DMA cannot preload up to the high threshold within the vertical blanking region of the panel. We leave the PRELOAD registers to their reset values since we haven't faced underflows with these SoCs because of low value of PRELOAD. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-12-17 11:10:21 +00:00
.set_max_preload = false,
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
};
static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
.sw_start = 5,
.fp_start = 15,
.bp_start = 27,
.sw_max = 64,
.vp_max = 255,
.hp_max = 256,
OMAPDSS: Add overlay manager width and height limits as a dispc feature The overlay manager width and height vary in OMAP5 from previous OMAPs in terms of maximum limit and register field positions. Add parameters in dispc_features for these. Also remove params related to manager width and height from dss_features, as we want to maintain a feature list for individual IPs. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-14 08:20:15 +00:00
.mgr_width_start = 10,
.mgr_height_start = 26,
.mgr_width_max = 2048,
.mgr_height_max = 2048,
omapdss: DISPC: add max pixel clock limits for LCD and TV managers Each version of OMAP has a limitation on the maximum pixel clock frequency supported by an overlay manager. This limit isn't checked by omapdss. Add dispc feats for lcd and tv managers and check whether the target timings can be supported or not. The pixel clock limitations are actually more complex. They depend on which OPP OMAP is in, and they also depend on which encoder is the manager connected to. The OPP dependence is ignored as DSS forces the PM framework to be on OPP100 when DSS is enabled, and the encoder dependencies are ignored by DISPC for now. These limits should come from the encoder driver. The OMAP2 TRM doesn't mention the maximum pixel clock limit. This value is left as half of DSS_FCLK, as OMAP2 requires the PCD to be atleast 2. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:22 +00:00
.max_lcd_pclk = 173000000,
.max_tv_pclk = 59000000,
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
.calc_scaling = dispc_ovl_calc_scaling_34xx,
.calc_core_clk = calc_core_clk_34xx,
OMAPDSS: Improve fifo management code OMAP4+ allows assigning the overlay FIFOs freely, but that is not supported by omapdss yet. This patch takes a step forward by improving the fifo management to be more flexible. dispc.c is changed to keep track of the sizes of each fifo, and also the overlay using each fifo. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:56:57 +00:00
.num_fifos = 3,
OMAPDSS: DISPC: add no_framedone_tv feat OMAP2/3 do not have FRAMEDONETV irq, but later omaps do. We currently always return 0 from dispc_mgr_get_framedone_irq() for TV output to be compatible with OMAP2/3. This patch implements "no_framedone_tv" dispc-feature that is used in dispc_mgr_get_framedone_irq to return either 0 for OMAP2/3, or the correct IRQ number for FRAMEDONETV on OMAP4+. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-08 08:01:33 +00:00
.no_framedone_tv = true,
OMAPDSS: DISPC: Preload more data in pipeline DMAs for OMAP4+ SoCs DISPC pipeline DMAs preload some bytes of pixel data in the vertical blanking region before the start of each frame. The preload ensures the pipeline doesn't underflow when the active region of the display starts. DISPC_GFX/VIDp_PRELOAD registers allow us to program how many bytes of data should be preloaded for each pipeline. Calculating a precise preload value would be a complex function of the pixel clock of the connected display, the vertical blanking duration and the interconnect traffic at that instance. If the register is left untouched, a default value is preloaded. We observe underflows for OMAP4+ SoCs for certain bandwidth intensive use cases with many other initiators active, and in situations where memory access isn't very efficient(like accessing Tiler mapped buffers and EMIF configured in non-interleaved more). The cause of the underflow is because the default preload value isn't sufficient for the DMA to reach a steady state. We configure the PRELOAD register such that the pipelines preload data up to the high threshold of the FIFO. Preloading lot of data for older SoCs can have a negative impact. Due to slower interconnects, it's possible that the DISPC DMA cannot preload up to the high threshold within the vertical blanking region of the panel. We leave the PRELOAD registers to their reset values since we haven't faced underflows with these SoCs because of low value of PRELOAD. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-12-17 11:10:21 +00:00
.set_max_preload = false,
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
};
static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
.sw_start = 7,
.fp_start = 19,
.bp_start = 31,
.sw_max = 256,
.vp_max = 4095,
.hp_max = 4096,
OMAPDSS: Add overlay manager width and height limits as a dispc feature The overlay manager width and height vary in OMAP5 from previous OMAPs in terms of maximum limit and register field positions. Add parameters in dispc_features for these. Also remove params related to manager width and height from dss_features, as we want to maintain a feature list for individual IPs. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-14 08:20:15 +00:00
.mgr_width_start = 10,
.mgr_height_start = 26,
.mgr_width_max = 2048,
.mgr_height_max = 2048,
omapdss: DISPC: add max pixel clock limits for LCD and TV managers Each version of OMAP has a limitation on the maximum pixel clock frequency supported by an overlay manager. This limit isn't checked by omapdss. Add dispc feats for lcd and tv managers and check whether the target timings can be supported or not. The pixel clock limitations are actually more complex. They depend on which OPP OMAP is in, and they also depend on which encoder is the manager connected to. The OPP dependence is ignored as DSS forces the PM framework to be on OPP100 when DSS is enabled, and the encoder dependencies are ignored by DISPC for now. These limits should come from the encoder driver. The OMAP2 TRM doesn't mention the maximum pixel clock limit. This value is left as half of DSS_FCLK, as OMAP2 requires the PCD to be atleast 2. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:22 +00:00
.max_lcd_pclk = 173000000,
.max_tv_pclk = 59000000,
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
.calc_scaling = dispc_ovl_calc_scaling_34xx,
.calc_core_clk = calc_core_clk_34xx,
OMAPDSS: Improve fifo management code OMAP4+ allows assigning the overlay FIFOs freely, but that is not supported by omapdss yet. This patch takes a step forward by improving the fifo management to be more flexible. dispc.c is changed to keep track of the sizes of each fifo, and also the overlay using each fifo. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:56:57 +00:00
.num_fifos = 3,
OMAPDSS: DISPC: add no_framedone_tv feat OMAP2/3 do not have FRAMEDONETV irq, but later omaps do. We currently always return 0 from dispc_mgr_get_framedone_irq() for TV output to be compatible with OMAP2/3. This patch implements "no_framedone_tv" dispc-feature that is used in dispc_mgr_get_framedone_irq to return either 0 for OMAP2/3, or the correct IRQ number for FRAMEDONETV on OMAP4+. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-08 08:01:33 +00:00
.no_framedone_tv = true,
OMAPDSS: DISPC: Preload more data in pipeline DMAs for OMAP4+ SoCs DISPC pipeline DMAs preload some bytes of pixel data in the vertical blanking region before the start of each frame. The preload ensures the pipeline doesn't underflow when the active region of the display starts. DISPC_GFX/VIDp_PRELOAD registers allow us to program how many bytes of data should be preloaded for each pipeline. Calculating a precise preload value would be a complex function of the pixel clock of the connected display, the vertical blanking duration and the interconnect traffic at that instance. If the register is left untouched, a default value is preloaded. We observe underflows for OMAP4+ SoCs for certain bandwidth intensive use cases with many other initiators active, and in situations where memory access isn't very efficient(like accessing Tiler mapped buffers and EMIF configured in non-interleaved more). The cause of the underflow is because the default preload value isn't sufficient for the DMA to reach a steady state. We configure the PRELOAD register such that the pipelines preload data up to the high threshold of the FIFO. Preloading lot of data for older SoCs can have a negative impact. Due to slower interconnects, it's possible that the DISPC DMA cannot preload up to the high threshold within the vertical blanking region of the panel. We leave the PRELOAD registers to their reset values since we haven't faced underflows with these SoCs because of low value of PRELOAD. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-12-17 11:10:21 +00:00
.set_max_preload = false,
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
};
static const struct dispc_features omap44xx_dispc_feats __initconst = {
.sw_start = 7,
.fp_start = 19,
.bp_start = 31,
.sw_max = 256,
.vp_max = 4095,
.hp_max = 4096,
OMAPDSS: Add overlay manager width and height limits as a dispc feature The overlay manager width and height vary in OMAP5 from previous OMAPs in terms of maximum limit and register field positions. Add parameters in dispc_features for these. Also remove params related to manager width and height from dss_features, as we want to maintain a feature list for individual IPs. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-14 08:20:15 +00:00
.mgr_width_start = 10,
.mgr_height_start = 26,
.mgr_width_max = 2048,
.mgr_height_max = 2048,
omapdss: DISPC: add max pixel clock limits for LCD and TV managers Each version of OMAP has a limitation on the maximum pixel clock frequency supported by an overlay manager. This limit isn't checked by omapdss. Add dispc feats for lcd and tv managers and check whether the target timings can be supported or not. The pixel clock limitations are actually more complex. They depend on which OPP OMAP is in, and they also depend on which encoder is the manager connected to. The OPP dependence is ignored as DSS forces the PM framework to be on OPP100 when DSS is enabled, and the encoder dependencies are ignored by DISPC for now. These limits should come from the encoder driver. The OMAP2 TRM doesn't mention the maximum pixel clock limit. This value is left as half of DSS_FCLK, as OMAP2 requires the PCD to be atleast 2. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:22 +00:00
.max_lcd_pclk = 170000000,
.max_tv_pclk = 185625000,
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
.calc_scaling = dispc_ovl_calc_scaling_44xx,
.calc_core_clk = calc_core_clk_44xx,
OMAPDSS: Improve fifo management code OMAP4+ allows assigning the overlay FIFOs freely, but that is not supported by omapdss yet. This patch takes a step forward by improving the fifo management to be more flexible. dispc.c is changed to keep track of the sizes of each fifo, and also the overlay using each fifo. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:56:57 +00:00
.num_fifos = 5,
OMAPDSS: Use WB fifo for GFX overlay OMAP4's GFX overlay has smaller fifo than the rest of the overlays (including writeback "overlay"). This seems to be the reason for underflows in some more demanding scenarios. We can avoid the problems by using the WB fifo for GFX overlay, and vice versa. WB usage is not supported yet, but when it will, it should perform just fine with smaller fifo as there are no hard realtime constraints with WB. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-08-22 13:57:02 +00:00
.gfx_fifo_workaround = true,
OMAPDSS: DISPC: Preload more data in pipeline DMAs for OMAP4+ SoCs DISPC pipeline DMAs preload some bytes of pixel data in the vertical blanking region before the start of each frame. The preload ensures the pipeline doesn't underflow when the active region of the display starts. DISPC_GFX/VIDp_PRELOAD registers allow us to program how many bytes of data should be preloaded for each pipeline. Calculating a precise preload value would be a complex function of the pixel clock of the connected display, the vertical blanking duration and the interconnect traffic at that instance. If the register is left untouched, a default value is preloaded. We observe underflows for OMAP4+ SoCs for certain bandwidth intensive use cases with many other initiators active, and in situations where memory access isn't very efficient(like accessing Tiler mapped buffers and EMIF configured in non-interleaved more). The cause of the underflow is because the default preload value isn't sufficient for the DMA to reach a steady state. We configure the PRELOAD register such that the pipelines preload data up to the high threshold of the FIFO. Preloading lot of data for older SoCs can have a negative impact. Due to slower interconnects, it's possible that the DISPC DMA cannot preload up to the high threshold within the vertical blanking region of the panel. We leave the PRELOAD registers to their reset values since we haven't faced underflows with these SoCs because of low value of PRELOAD. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-12-17 11:10:21 +00:00
.set_max_preload = true,
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
};
OMAPDSS: Add a dispc_features struct for OMAP5 Add a dispc_features struct for OMAP5. Previously, OMAP5 used the same struct as OMAP4. The new struct for OMAP5 contains the updated register field offset and maximum limit for overlay manager width and height. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-14 08:20:16 +00:00
static const struct dispc_features omap54xx_dispc_feats __initconst = {
.sw_start = 7,
.fp_start = 19,
.bp_start = 31,
.sw_max = 256,
.vp_max = 4095,
.hp_max = 4096,
.mgr_width_start = 11,
.mgr_height_start = 27,
.mgr_width_max = 4096,
.mgr_height_max = 4096,
omapdss: DISPC: add max pixel clock limits for LCD and TV managers Each version of OMAP has a limitation on the maximum pixel clock frequency supported by an overlay manager. This limit isn't checked by omapdss. Add dispc feats for lcd and tv managers and check whether the target timings can be supported or not. The pixel clock limitations are actually more complex. They depend on which OPP OMAP is in, and they also depend on which encoder is the manager connected to. The OPP dependence is ignored as DSS forces the PM framework to be on OPP100 when DSS is enabled, and the encoder dependencies are ignored by DISPC for now. These limits should come from the encoder driver. The OMAP2 TRM doesn't mention the maximum pixel clock limit. This value is left as half of DSS_FCLK, as OMAP2 requires the PCD to be atleast 2. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:22 +00:00
.max_lcd_pclk = 170000000,
.max_tv_pclk = 186000000,
OMAPDSS: Add a dispc_features struct for OMAP5 Add a dispc_features struct for OMAP5. Previously, OMAP5 used the same struct as OMAP4. The new struct for OMAP5 contains the updated register field offset and maximum limit for overlay manager width and height. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-14 08:20:16 +00:00
.calc_scaling = dispc_ovl_calc_scaling_44xx,
.calc_core_clk = calc_core_clk_44xx,
.num_fifos = 5,
.gfx_fifo_workaround = true,
OMAPDSS: DISPC: Revert to older DISPC Smart Standby mechanism for OMAP5 DISPC on OMAP5 has a more optimised mechanism of asserting Mstandby to achieve more power savings when DISPC is configured in Smart Standby mode. This mechanism leads to underflows when multiple DISPC pipes are enabled. There is a register field which can let us revert to the older mechanism of asserting Mstandby. Configure this field to prevent underflows. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-03-26 13:45:25 +00:00
.mstandby_workaround = true,
OMAPDSS: DISPC: Preload more data in pipeline DMAs for OMAP4+ SoCs DISPC pipeline DMAs preload some bytes of pixel data in the vertical blanking region before the start of each frame. The preload ensures the pipeline doesn't underflow when the active region of the display starts. DISPC_GFX/VIDp_PRELOAD registers allow us to program how many bytes of data should be preloaded for each pipeline. Calculating a precise preload value would be a complex function of the pixel clock of the connected display, the vertical blanking duration and the interconnect traffic at that instance. If the register is left untouched, a default value is preloaded. We observe underflows for OMAP4+ SoCs for certain bandwidth intensive use cases with many other initiators active, and in situations where memory access isn't very efficient(like accessing Tiler mapped buffers and EMIF configured in non-interleaved more). The cause of the underflow is because the default preload value isn't sufficient for the DMA to reach a steady state. We configure the PRELOAD register such that the pipelines preload data up to the high threshold of the FIFO. Preloading lot of data for older SoCs can have a negative impact. Due to slower interconnects, it's possible that the DISPC DMA cannot preload up to the high threshold within the vertical blanking region of the panel. We leave the PRELOAD registers to their reset values since we haven't faced underflows with these SoCs because of low value of PRELOAD. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-12-17 11:10:21 +00:00
.set_max_preload = true,
OMAPDSS: Add a dispc_features struct for OMAP5 Add a dispc_features struct for OMAP5. Previously, OMAP5 used the same struct as OMAP4. The new struct for OMAP5 contains the updated register field offset and maximum limit for overlay manager width and height. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-14 08:20:16 +00:00
};
OMAPDSS: DISPC: use omapdss_version Use omapdss_version in dispc.c to select the proper dispc features. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-28 09:54:03 +00:00
static int __init dispc_init_features(struct platform_device *pdev)
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
{
const struct dispc_features *src;
struct dispc_features *dst;
OMAPDSS: DISPC: use omapdss_version Use omapdss_version in dispc.c to select the proper dispc features. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-28 09:54:03 +00:00
dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
if (!dst) {
OMAPDSS: DISPC: use omapdss_version Use omapdss_version in dispc.c to select the proper dispc features. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-28 09:54:03 +00:00
dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
return -ENOMEM;
}
OMAPDSS: get the dss version from core pdev The output drivers get the omapdss hw version from the platform data for their respective output device. This doesn't work with DT, as there's no platform data for them. Add a new function, omapdss_get_version(), which returns the dss version from the core device, which will have platform data on DT also. The function is exported so that users of omapdss can also use it. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-18 10:46:29 +00:00
switch (omapdss_get_version()) {
OMAPDSS: DISPC: use omapdss_version Use omapdss_version in dispc.c to select the proper dispc features. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-28 09:54:03 +00:00
case OMAPDSS_VER_OMAP24xx:
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
src = &omap24xx_dispc_feats;
OMAPDSS: DISPC: use omapdss_version Use omapdss_version in dispc.c to select the proper dispc features. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-28 09:54:03 +00:00
break;
case OMAPDSS_VER_OMAP34xx_ES1:
src = &omap34xx_rev1_0_dispc_feats;
break;
case OMAPDSS_VER_OMAP34xx_ES3:
case OMAPDSS_VER_OMAP3630:
case OMAPDSS_VER_AM35xx:
OMAPDSS: Add DSS features for AM43xx Add DSS features for AM43xx. Signed-off-by: Sathya Prakash M R <sathyap@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-03-24 11:01:51 +00:00
case OMAPDSS_VER_AM43xx:
OMAPDSS: DISPC: use omapdss_version Use omapdss_version in dispc.c to select the proper dispc features. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-28 09:54:03 +00:00
src = &omap34xx_rev3_0_dispc_feats;
break;
case OMAPDSS_VER_OMAP4430_ES1:
case OMAPDSS_VER_OMAP4430_ES2:
case OMAPDSS_VER_OMAP4:
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
src = &omap44xx_dispc_feats;
OMAPDSS: DISPC: use omapdss_version Use omapdss_version in dispc.c to select the proper dispc features. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-28 09:54:03 +00:00
break;
case OMAPDSS_VER_OMAP5:
OMAPDSS: DISPC: Add DRA7xx support Add DRA7xx support to DISPC driver. The DISPC block is the same as on OMAP5, except the PLL's used for clocking are "videoX", not "dsiX". Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-12-31 09:25:48 +00:00
case OMAPDSS_VER_DRA7xx:
OMAPDSS: Add a dispc_features struct for OMAP5 Add a dispc_features struct for OMAP5. Previously, OMAP5 used the same struct as OMAP4. The new struct for OMAP5 contains the updated register field offset and maximum limit for overlay manager width and height. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-14 08:20:16 +00:00
src = &omap54xx_dispc_feats;
OMAPDSS: DISPC: use omapdss_version Use omapdss_version in dispc.c to select the proper dispc features. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-28 09:54:03 +00:00
break;
default:
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
return -ENODEV;
}
memcpy(dst, src, sizeof(*dst));
dispc.feat = dst;
return 0;
}
OMAPDSS: fix shared irq handlers DSS uses shared irq handlers for DISPC and DSI, because on OMAP3, the DISPC and DSI share the same irq line. However, the irq handlers presume that the hardware is enabled, which, in theory, may not be the case with shared irq handlers. So if an interrupt happens while the DISPC/DSI is off, the kernel will halt as the irq handler tries to access the DISPC/DSI registers. In practice that should never happen, as both DSI and DISPC are in the same power domain. So if there's an IRQ for one of them, the other is also enabled. However, if CONFIG_DEBUG_SHIRQ is enabled, the kernel will generate a spurious IRQ, which then causes the problem. This patch adds an is_enabled field for both DISPC and DSI, which is used to track if the HW is enabled. For DISPC the code is slightly more complex, as the users of DISPC can register the interrupt handler, and we want to hide the is_enabled handling from the users of DISPC. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-11 10:49:55 +00:00
static irqreturn_t dispc_irq_handler(int irq, void *arg)
{
if (!dispc.is_enabled)
return IRQ_NONE;
return dispc.user_handler(irq, dispc.user_data);
}
OMAPDSS: move irq handling to dispc-compat The whole dispc irq handling system we currently have is only needed for compat layer, and thus can be moved from dispc.c to the compat layer. This is quite straigtforward, but we need to add new dispc functions to request and free the actual hardware irq: dispc_request_irq() and dispc_free_irq(). Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 12:55:19 +00:00
int dispc_request_irq(irq_handler_t handler, void *dev_id)
{
OMAPDSS: fix shared irq handlers DSS uses shared irq handlers for DISPC and DSI, because on OMAP3, the DISPC and DSI share the same irq line. However, the irq handlers presume that the hardware is enabled, which, in theory, may not be the case with shared irq handlers. So if an interrupt happens while the DISPC/DSI is off, the kernel will halt as the irq handler tries to access the DISPC/DSI registers. In practice that should never happen, as both DSI and DISPC are in the same power domain. So if there's an IRQ for one of them, the other is also enabled. However, if CONFIG_DEBUG_SHIRQ is enabled, the kernel will generate a spurious IRQ, which then causes the problem. This patch adds an is_enabled field for both DISPC and DSI, which is used to track if the HW is enabled. For DISPC the code is slightly more complex, as the users of DISPC can register the interrupt handler, and we want to hide the is_enabled handling from the users of DISPC. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-11 10:49:55 +00:00
int r;
if (dispc.user_handler != NULL)
return -EBUSY;
dispc.user_handler = handler;
dispc.user_data = dev_id;
/* ensure the dispc_irq_handler sees the values above */
smp_wmb();
r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
IRQF_SHARED, "OMAP DISPC", &dispc);
if (r) {
dispc.user_handler = NULL;
dispc.user_data = NULL;
}
return r;
OMAPDSS: move irq handling to dispc-compat The whole dispc irq handling system we currently have is only needed for compat layer, and thus can be moved from dispc.c to the compat layer. This is quite straigtforward, but we need to add new dispc functions to request and free the actual hardware irq: dispc_request_irq() and dispc_free_irq(). Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 12:55:19 +00:00
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_request_irq);
OMAPDSS: move irq handling to dispc-compat The whole dispc irq handling system we currently have is only needed for compat layer, and thus can be moved from dispc.c to the compat layer. This is quite straigtforward, but we need to add new dispc functions to request and free the actual hardware irq: dispc_request_irq() and dispc_free_irq(). Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 12:55:19 +00:00
void dispc_free_irq(void *dev_id)
{
OMAPDSS: fix shared irq handlers DSS uses shared irq handlers for DISPC and DSI, because on OMAP3, the DISPC and DSI share the same irq line. However, the irq handlers presume that the hardware is enabled, which, in theory, may not be the case with shared irq handlers. So if an interrupt happens while the DISPC/DSI is off, the kernel will halt as the irq handler tries to access the DISPC/DSI registers. In practice that should never happen, as both DSI and DISPC are in the same power domain. So if there's an IRQ for one of them, the other is also enabled. However, if CONFIG_DEBUG_SHIRQ is enabled, the kernel will generate a spurious IRQ, which then causes the problem. This patch adds an is_enabled field for both DISPC and DSI, which is used to track if the HW is enabled. For DISPC the code is slightly more complex, as the users of DISPC can register the interrupt handler, and we want to hide the is_enabled handling from the users of DISPC. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-11 10:49:55 +00:00
devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
dispc.user_handler = NULL;
dispc.user_data = NULL;
OMAPDSS: move irq handling to dispc-compat The whole dispc irq handling system we currently have is only needed for compat layer, and thus can be moved from dispc.c to the compat layer. This is quite straigtforward, but we need to add new dispc functions to request and free the actual hardware irq: dispc_request_irq() and dispc_free_irq(). Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 12:55:19 +00:00
}
OMAPDSS: export dispc functions Export DISPC functions. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-11-07 16:17:35 +00:00
EXPORT_SYMBOL(dispc_free_irq);
OMAPDSS: move irq handling to dispc-compat The whole dispc irq handling system we currently have is only needed for compat layer, and thus can be moved from dispc.c to the compat layer. This is quite straigtforward, but we need to add new dispc functions to request and free the actual hardware irq: dispc_request_irq() and dispc_free_irq(). Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-10-10 12:55:19 +00:00
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
/* DISPC HW IP initialisation */
OMAPDSS: add __init & __exit Now that we are using platform_driver_probe() we can add __inits and __exits all around. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-02-17 15:41:13 +00:00
static int __init omap_dispchw_probe(struct platform_device *pdev)
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
{
u32 rev;
OMAP: DSS2: Have separate irq handlers for DISPC and DSI Currently, the core DSS platform device requests for an irq line for OMAP2 and OMAP3. Make DISPC and DSI platform devices request for a shared IRQ line. On OMAP3, the logical OR of DSI and DISPC interrupt lines goes to the MPU. There is a register DSS_IRQSTATUS which tells if the interrupt came from DISPC or DSI. On OMAP2, there is no DSI, only DISPC interrupts goto the MPU. There is no DSS_IRQSTATUS register. Hence, it makes more sense to have separate irq handlers corresponding to the DSS sub modules instead of having a common handler. Since on OMAP3 the logical OR of the lines goes to MPU, the irq line is shared among the IRQ handlers. The hwmod irq info has been removed for DSS to DISPC and DSI for OMAP2 and OMAP3 hwmod databases. The Probes of DISPC and DSI now request for irq handlers. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-02-23 08:41:03 +00:00
int r = 0;
OMAP2,3: DSS2: Use platform device to get baseaddr DSS, DISPC, DSI, RFBI, VENC baseaddr can be obtained from platform_get_resource(). This API in turn picks the right silicon baseaddr from the hwmod database. So hardcoding of base addr could be removed. Reviewed-by: Paul Walmsley <paul@pwsan.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:04 +00:00
struct resource *dispc_mem;
OMAPDSS: DISPC: program dispc polarities to control module On DRA7xx, DISPC needs to write output signal polarities not only to a DISPC register, like for all earlier DSS versions, but to control module's CTRL_CORE_SMA_SW_1 register. This patch adds support to write the polarities to control module. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-09-05 19:15:03 +00:00
struct device_node *np = pdev->dev.of_node;
OMAP2,3: DSS2: Use platform device to get baseaddr DSS, DISPC, DSI, RFBI, VENC baseaddr can be obtained from platform_get_resource(). This API in turn picks the right silicon baseaddr from the hwmod database. So hardcoding of base addr could be removed. Reviewed-by: Paul Walmsley <paul@pwsan.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:04 +00:00
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
dispc.pdev = pdev;
OMAPDSS: DISPC: lock access to DISPC_CONTROL & DISPC_CONFIG Dispc driver presumes that the callers handle locking for all normal functions. However, omapdrm doesn't handle this, and presumes that all overlay manager registers are private to that overlay manager, and thus presumes that configurations for overlay managers can be written via different threads freely. For many registers the above is true. The exceptions are DISPC_CONTROL and DISPC_CONFIG registers, which contain bits for both LCD and TV overlay managers. Fixing this properly in omapdrm means a big omapdrm rewrite. So, for now, add locking to dispc for the problematic registers. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reported-by: Somnath Mukherjee <somnath@ti.com>
2014-11-10 10:23:00 +00:00
spin_lock_init(&dispc.control_lock);
OMAPDSS: DISPC: use omapdss_version Use omapdss_version in dispc.c to select the proper dispc features. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-09-28 09:54:03 +00:00
r = dispc_init_features(dispc.pdev);
OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-07-03 06:56:51 +00:00
if (r)
return r;
OMAP2,3: DSS2: Use platform device to get baseaddr DSS, DISPC, DSI, RFBI, VENC baseaddr can be obtained from platform_get_resource(). This API in turn picks the right silicon baseaddr from the hwmod database. So hardcoding of base addr could be removed. Reviewed-by: Paul Walmsley <paul@pwsan.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:04 +00:00
dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
if (!dispc_mem) {
DSSERR("can't get IORESOURCE_MEM DISPC\n");
OMAPDSS: cleanup probe functions Now that dss is using devm_ functions for allocation in probe functions, small reordering of the allocations allows us to clean up the probe functions more. This patch moves "unmanaged" allocations after the managed ones, and uses plain returns instead of gotos where possible. This lets us remove a bunch of goto labels, simplifying the probe's error handling. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-25 11:31:04 +00:00
return -EINVAL;
OMAP2,3: DSS2: Use platform device to get baseaddr DSS, DISPC, DSI, RFBI, VENC baseaddr can be obtained from platform_get_resource(). This API in turn picks the right silicon baseaddr from the hwmod database. So hardcoding of base addr could be removed. Reviewed-by: Paul Walmsley <paul@pwsan.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:04 +00:00
}
OMAPDSS: cleanup probe functions Now that dss is using devm_ functions for allocation in probe functions, small reordering of the allocations allows us to clean up the probe functions more. This patch moves "unmanaged" allocations after the managed ones, and uses plain returns instead of gotos where possible. This lets us remove a bunch of goto labels, simplifying the probe's error handling. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-25 11:31:04 +00:00
OMAPDSS: use devm_ functions The various devm_ functions allocate memory that is released when a driver detaches. This patch uses these functions for data that is allocated in the probe function of a platform device and is only freed in the remove function. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-24 13:00:45 +00:00
dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
resource_size(dispc_mem));
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
if (!dispc.base) {
DSSERR("can't ioremap DISPC\n");
OMAPDSS: cleanup probe functions Now that dss is using devm_ functions for allocation in probe functions, small reordering of the allocations allows us to clean up the probe functions more. This patch moves "unmanaged" allocations after the managed ones, and uses plain returns instead of gotos where possible. This lets us remove a bunch of goto labels, simplifying the probe's error handling. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-25 11:31:04 +00:00
return -ENOMEM;
OMAP: DSS2: Have separate irq handlers for DISPC and DSI Currently, the core DSS platform device requests for an irq line for OMAP2 and OMAP3. Make DISPC and DSI platform devices request for a shared IRQ line. On OMAP3, the logical OR of DSI and DISPC interrupt lines goes to the MPU. There is a register DSS_IRQSTATUS which tells if the interrupt came from DISPC or DSI. On OMAP2, there is no DSI, only DISPC interrupts goto the MPU. There is no DSS_IRQSTATUS register. Hence, it makes more sense to have separate irq handlers corresponding to the DSS sub modules instead of having a common handler. Since on OMAP3 the logical OR of the lines goes to MPU, the irq line is shared among the IRQ handlers. The hwmod irq info has been removed for DSS to DISPC and DSI for OMAP2 and OMAP3 hwmod databases. The Probes of DISPC and DSI now request for irq handlers. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-02-23 08:41:03 +00:00
}
OMAPDSS: cleanup probe functions Now that dss is using devm_ functions for allocation in probe functions, small reordering of the allocations allows us to clean up the probe functions more. This patch moves "unmanaged" allocations after the managed ones, and uses plain returns instead of gotos where possible. This lets us remove a bunch of goto labels, simplifying the probe's error handling. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-25 11:31:04 +00:00
OMAP: DSS2: Have separate irq handlers for DISPC and DSI Currently, the core DSS platform device requests for an irq line for OMAP2 and OMAP3. Make DISPC and DSI platform devices request for a shared IRQ line. On OMAP3, the logical OR of DSI and DISPC interrupt lines goes to the MPU. There is a register DSS_IRQSTATUS which tells if the interrupt came from DISPC or DSI. On OMAP2, there is no DSI, only DISPC interrupts goto the MPU. There is no DSS_IRQSTATUS register. Hence, it makes more sense to have separate irq handlers corresponding to the DSS sub modules instead of having a common handler. Since on OMAP3 the logical OR of the lines goes to MPU, the irq line is shared among the IRQ handlers. The hwmod irq info has been removed for DSS to DISPC and DSI for OMAP2 and OMAP3 hwmod databases. The Probes of DISPC and DSI now request for irq handlers. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-02-23 08:41:03 +00:00
dispc.irq = platform_get_irq(dispc.pdev, 0);
if (dispc.irq < 0) {
DSSERR("platform_get_irq failed\n");
OMAPDSS: cleanup probe functions Now that dss is using devm_ functions for allocation in probe functions, small reordering of the allocations allows us to clean up the probe functions more. This patch moves "unmanaged" allocations after the managed ones, and uses plain returns instead of gotos where possible. This lets us remove a bunch of goto labels, simplifying the probe's error handling. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-01-25 11:31:04 +00:00
return -ENODEV;
OMAP: DSS2: Have separate irq handlers for DISPC and DSI Currently, the core DSS platform device requests for an irq line for OMAP2 and OMAP3. Make DISPC and DSI platform devices request for a shared IRQ line. On OMAP3, the logical OR of DSI and DISPC interrupt lines goes to the MPU. There is a register DSS_IRQSTATUS which tells if the interrupt came from DISPC or DSI. On OMAP2, there is no DSI, only DISPC interrupts goto the MPU. There is no DSS_IRQSTATUS register. Hence, it makes more sense to have separate irq handlers corresponding to the DSS sub modules instead of having a common handler. Since on OMAP3 the logical OR of the lines goes to MPU, the irq line is shared among the IRQ handlers. The hwmod irq info has been removed for DSS to DISPC and DSI for OMAP2 and OMAP3 hwmod databases. The Probes of DISPC and DSI now request for irq handlers. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-02-23 08:41:03 +00:00
}
OMAPDSS: DISPC: program dispc polarities to control module On DRA7xx, DISPC needs to write output signal polarities not only to a DISPC register, like for all earlier DSS versions, but to control module's CTRL_CORE_SMA_SW_1 register. This patch adds support to write the polarities to control module. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-09-05 19:15:03 +00:00
if (np && of_property_read_bool(np, "syscon-pol")) {
dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
if (IS_ERR(dispc.syscon_pol)) {
dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
return PTR_ERR(dispc.syscon_pol);
}
if (of_property_read_u32_index(np, "syscon-pol", 1,
&dispc.syscon_pol_offset)) {
dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
return -EINVAL;
}
}
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
pm_runtime_enable(&pdev->dev);
r = dispc_runtime_get();
if (r)
goto err_runtime_get;
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
_omap_dispc_initial_config();
rev = dispc_read_reg(DISPC_REVISION);
OMAP2,3: DSS2: replace printk with dev_dbg in init This patch replaces printk's in the init/probe functions to dev_dbg for boot time optimization. Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:03 +00:00
dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
dispc_runtime_put();
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
OMAPDRM: fix overlay manager handling Currently omapdrm creates crtcs, which map directly to DSS overlay managers, only on demand at init time. This would make it difficult to manage connecting the display entities in the future, as the code cannot just search for a suitable overlay manager. We cannot fix this the sane way, which would be to create crtcs for each overlay manager, because we need an overlay for each crtc. With limited number of overlays, that's not possible. So the solution for now is to detach the overlay manager from the crtc. crtcs are still created on demand at init time, but all overlay managers are always initialized by the omapdss. This way we can create and connect whole display pipelines from the overlay manager to the display, regardless of which crtcs omapdrm would create. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-05-14 07:55:19 +00:00
dss_init_overlay_managers();
OMAPDSS: move the creation of debugfs files Instead of having an ugly #ifdef mess in the core.c for creating debugfs files, add a dss_debugfs_create_file() function that the dss drivers can use to create the debugfs files. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-03-02 16:01:07 +00:00
dss_debugfs_create_file("dispc", dispc_dump_regs);
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
return 0;
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
err_runtime_get:
pm_runtime_disable(&pdev->dev);
OMAP: DSS2: Have separate irq handlers for DISPC and DSI Currently, the core DSS platform device requests for an irq line for OMAP2 and OMAP3. Make DISPC and DSI platform devices request for a shared IRQ line. On OMAP3, the logical OR of DSI and DISPC interrupt lines goes to the MPU. There is a register DSS_IRQSTATUS which tells if the interrupt came from DISPC or DSI. On OMAP2, there is no DSI, only DISPC interrupts goto the MPU. There is no DSS_IRQSTATUS register. Hence, it makes more sense to have separate irq handlers corresponding to the DSS sub modules instead of having a common handler. Since on OMAP3 the logical OR of the lines goes to MPU, the irq line is shared among the IRQ handlers. The hwmod irq info has been removed for DSS to DISPC and DSI for OMAP2 and OMAP3 hwmod databases. The Probes of DISPC and DSI now request for irq handlers. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-02-23 08:41:03 +00:00
return r;
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
}
OMAPDSS: add __init & __exit Now that we are using platform_driver_probe() we can add __inits and __exits all around. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-02-17 15:41:13 +00:00
static int __exit omap_dispchw_remove(struct platform_device *pdev)
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
{
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
pm_runtime_disable(&pdev->dev);
OMAPDRM: fix overlay manager handling Currently omapdrm creates crtcs, which map directly to DSS overlay managers, only on demand at init time. This would make it difficult to manage connecting the display entities in the future, as the code cannot just search for a suitable overlay manager. We cannot fix this the sane way, which would be to create crtcs for each overlay manager, because we need an overlay for each crtc. With limited number of overlays, that's not possible. So the solution for now is to detach the overlay manager from the crtc. crtcs are still created on demand at init time, but all overlay managers are always initialized by the omapdss. This way we can create and connect whole display pipelines from the overlay manager to the display, regardless of which crtcs omapdrm would create. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-05-14 07:55:19 +00:00
dss_uninit_overlay_managers();
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
return 0;
}
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
static int dispc_runtime_suspend(struct device *dev)
{
OMAPDSS: fix shared irq handlers DSS uses shared irq handlers for DISPC and DSI, because on OMAP3, the DISPC and DSI share the same irq line. However, the irq handlers presume that the hardware is enabled, which, in theory, may not be the case with shared irq handlers. So if an interrupt happens while the DISPC/DSI is off, the kernel will halt as the irq handler tries to access the DISPC/DSI registers. In practice that should never happen, as both DSI and DISPC are in the same power domain. So if there's an IRQ for one of them, the other is also enabled. However, if CONFIG_DEBUG_SHIRQ is enabled, the kernel will generate a spurious IRQ, which then causes the problem. This patch adds an is_enabled field for both DISPC and DSI, which is used to track if the HW is enabled. For DISPC the code is slightly more complex, as the users of DISPC can register the interrupt handler, and we want to hide the is_enabled handling from the users of DISPC. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-11 10:49:55 +00:00
dispc.is_enabled = false;
/* ensure the dispc_irq_handler sees the is_enabled value */
smp_wmb();
/* wait for current handler to finish before turning the DISPC off */
synchronize_irq(dispc.irq);
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
dispc_save_context();
return 0;
}
static int dispc_runtime_resume(struct device *dev)
{
OMAPDSS: use DISPC register to detect context loss Instead of relying on the OMAP specific omap_pm_get_dev_context_loss_count() to detect register context loss, we can achieve the same in a much simpler way by just observing the DISPC registers. We always set DISPC's load mode to LOAD_FRAME_ONLY, which is not the reset value. Thus we can just observe the load mode to see if we have lost register context. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Archit Taneja <archit@ti.com>
2014-02-14 07:37:09 +00:00
/*
* The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
* but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
* _omap_dispc_initial_config(). We can thus use it to detect if
* we have lost register context.
*/
OMAPDSS: fix shared irq handlers DSS uses shared irq handlers for DISPC and DSI, because on OMAP3, the DISPC and DSI share the same irq line. However, the irq handlers presume that the hardware is enabled, which, in theory, may not be the case with shared irq handlers. So if an interrupt happens while the DISPC/DSI is off, the kernel will halt as the irq handler tries to access the DISPC/DSI registers. In practice that should never happen, as both DSI and DISPC are in the same power domain. So if there's an IRQ for one of them, the other is also enabled. However, if CONFIG_DEBUG_SHIRQ is enabled, the kernel will generate a spurious IRQ, which then causes the problem. This patch adds an is_enabled field for both DISPC and DSI, which is used to track if the HW is enabled. For DISPC the code is slightly more complex, as the users of DISPC can register the interrupt handler, and we want to hide the is_enabled handling from the users of DISPC. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-11 10:49:55 +00:00
if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
_omap_dispc_initial_config();
OMAPDSS: use DISPC register to detect context loss Instead of relying on the OMAP specific omap_pm_get_dev_context_loss_count() to detect register context loss, we can achieve the same in a much simpler way by just observing the DISPC registers. We always set DISPC's load mode to LOAD_FRAME_ONLY, which is not the reset value. Thus we can just observe the load mode to see if we have lost register context. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Archit Taneja <archit@ti.com>
2014-02-14 07:37:09 +00:00
OMAPDSS: fix shared irq handlers DSS uses shared irq handlers for DISPC and DSI, because on OMAP3, the DISPC and DSI share the same irq line. However, the irq handlers presume that the hardware is enabled, which, in theory, may not be the case with shared irq handlers. So if an interrupt happens while the DISPC/DSI is off, the kernel will halt as the irq handler tries to access the DISPC/DSI registers. In practice that should never happen, as both DSI and DISPC are in the same power domain. So if there's an IRQ for one of them, the other is also enabled. However, if CONFIG_DEBUG_SHIRQ is enabled, the kernel will generate a spurious IRQ, which then causes the problem. This patch adds an is_enabled field for both DISPC and DSI, which is used to track if the HW is enabled. For DISPC the code is slightly more complex, as the users of DISPC can register the interrupt handler, and we want to hide the is_enabled handling from the users of DISPC. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-11 10:49:55 +00:00
dispc_restore_context();
}
OMAPDSS: DISPC: fix context restore DISPC_MSTANDBY_CTRL register is used in the driver, but it's not restored in dispc_restore_context(), causing problems after resume. Instead of adding DISPC_MSTANDBY_CTRL to dispc_restore_context(), let's call _omap_dispc_initial_config() as the first thing in dispc_runtime_resume(). This will initialize the DISPC core registers properly, and will avoid similar issues in the future. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2013-11-21 14:01:40 +00:00
OMAPDSS: fix shared irq handlers DSS uses shared irq handlers for DISPC and DSI, because on OMAP3, the DISPC and DSI share the same irq line. However, the irq handlers presume that the hardware is enabled, which, in theory, may not be the case with shared irq handlers. So if an interrupt happens while the DISPC/DSI is off, the kernel will halt as the irq handler tries to access the DISPC/DSI registers. In practice that should never happen, as both DSI and DISPC are in the same power domain. So if there's an IRQ for one of them, the other is also enabled. However, if CONFIG_DEBUG_SHIRQ is enabled, the kernel will generate a spurious IRQ, which then causes the problem. This patch adds an is_enabled field for both DISPC and DSI, which is used to track if the HW is enabled. For DISPC the code is slightly more complex, as the users of DISPC can register the interrupt handler, and we want to hide the is_enabled handling from the users of DISPC. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-11 10:49:55 +00:00
dispc.is_enabled = true;
/* ensure the dispc_irq_handler sees the is_enabled value */
smp_wmb();
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
return 0;
}
static const struct dev_pm_ops dispc_pm_ops = {
.runtime_suspend = dispc_runtime_suspend,
.runtime_resume = dispc_runtime_resume,
};
OMAPDSS: Add DT support to DISPC Add DT support to DISPC. Only thing needed here is the of_match_table. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Archit Taneja <archit@ti.com>
2013-12-17 09:54:02 +00:00
static const struct of_device_id dispc_of_match[] = {
{ .compatible = "ti,omap2-dispc", },
{ .compatible = "ti,omap3-dispc", },
{ .compatible = "ti,omap4-dispc", },
OMAPDSS: DSS & DISPC DT support for OMAP5 Add omap5 entries to dispc's and dss's of_device_id tables. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-04-16 10:16:43 +00:00
{ .compatible = "ti,omap5-dispc", },
OMAPDSS: DISPC: Add DRA7xx support Add DRA7xx support to DISPC driver. The DISPC block is the same as on OMAP5, except the PLL's used for clocking are "videoX", not "dsiX". Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-12-31 09:25:48 +00:00
{ .compatible = "ti,dra7-dispc", },
OMAPDSS: Add DT support to DISPC Add DT support to DISPC. Only thing needed here is the of_match_table. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Archit Taneja <archit@ti.com>
2013-12-17 09:54:02 +00:00
{},
};
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
static struct platform_driver omap_dispchw_driver = {
OMAPDSS: add __init & __exit Now that we are using platform_driver_probe() we can add __inits and __exits all around. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-02-17 15:41:13 +00:00
.remove = __exit_p(omap_dispchw_remove),
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
.driver = {
.name = "omapdss_dispc",
OMAP: DSS2: Use PM runtime & HWMOD support Use PM runtime and HWMOD support to handle enabling and disabling of DSS modules. Each DSS module will have get and put functions which can be used to enable and disable that module. The functions use pm_runtime and hwmod opt-clocks to enable the hardware. Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-05-27 07:52:19 +00:00
.pm = &dispc_pm_ops,
OMAPDSS: Add DT support to DISPC Add DT support to DISPC. Only thing needed here is the of_match_table. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Archit Taneja <archit@ti.com>
2013-12-17 09:54:02 +00:00
.of_match_table = dispc_of_match,
OMAPDSS: set suppress_bind_attrs omapdss drivers cannot handle devices being unbound while the devices are part of a connected display pipeline. Module refcounts are used to prevent unloading the modules, but one can still manually unbind the devices via sysfs, causing crash. Set suppress_bind_attrs to disable the bind/unbind support via sysfs. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-10-16 06:54:25 +00:00
.suppress_bind_attrs = true,
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
},
};
OMAPDSS: add __init & __exit Now that we are using platform_driver_probe() we can add __inits and __exits all around. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-02-17 15:41:13 +00:00
int __init dispc_init_platform_driver(void)
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
{
OMAPDSS: use platform_driver_probe for core/dispc/dss The platform devices for omapdss, dss and dispc drivers are always present, so we can use platform_driver_probe instead of platform_driver_register. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-03-07 10:53:18 +00:00
return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
}
OMAPDSS: add __init & __exit Now that we are using platform_driver_probe() we can add __inits and __exits all around. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-02-17 15:41:13 +00:00
void __exit dispc_uninit_platform_driver(void)
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
{
OMAPDSS: remove return from platform_driver_unreg For unknown reasons we seem to have a return in each of the omapdss's uninit functions, which is a void function. Remove the returns. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-02-23 13:32:37 +00:00
platform_driver_unregister(&omap_dispchw_driver);
OMAP2, 3: DSS2: DISPC: create platform_driver, move init, exit to driver Hwmod adaptation design requires each of the DSS HW IP to be a platform driver. So a platform_driver for DISPC is created and init exit methods are moved from core.c to its driver probe,remove. pdev member has to be maintained by its own drivers. DISPC platform driver is registered from inside omap_dss_probe, in the order desired. Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2011-01-24 06:22:00 +00:00
}
Reference in New Issue Copy Permalink