2012-06-13 17:01:28 +00:00
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/*
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* Device Tree file for Marvell Armada 370 evaluation board
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* (DB-88F6710-BP-DDR3)
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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2015-01-26 14:15:45 +00:00
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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2016-12-27 21:36:42 +00:00
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* This file is distributed in the hope that it will be useful,
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2015-01-26 14:15:45 +00:00
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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2016-12-27 21:36:42 +00:00
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* Or, alternatively,
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2015-01-26 14:15:45 +00:00
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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2016-12-27 21:36:42 +00:00
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* restriction, including without limitation the rights to use,
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2015-01-26 14:15:45 +00:00
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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2016-12-27 21:36:42 +00:00
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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2015-01-26 14:15:45 +00:00
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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2016-12-27 21:36:42 +00:00
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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2015-01-26 14:15:45 +00:00
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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ARM: mvebu: use 0xf1000000 as internal registers on Armada 370 DB
All Marvell EBU SoCs (Kirkwood, Dove, Orion, Armada) have the
capability of changing the location of their internal registers (i.e
the registers for most hardware blocks inside the SoC). When coming
out of reset, the internal registers are mapped at 0xd0000000, but
since years and years, the tradition has been to have the internal
registers remapped at 0xf1000000 by the bootloader, and Linux has
since then assumed that the internal registers for the SoC were
located at 0xf1000000 on Kirkwood, Dove, Orion, etc. Linux has never
been aware that those registers are remappable (and there is no way to
know where they are mapped at runtime, since the register to configure
the address of the registers is itself within the internal registers).
Then came the Armada 370 and Armada XP, in which some of the very
early silicon steppings had an issue, which forced to use 0xd0000000:
the SoC was no longer working properly when the internal registers
were remapped at 0xf1000000. This issue is only affecting very early
silicon steppings and production steppings are not affected: the issue
has been fixed in between.
Since what we (Free Electrons) used to do the initial submission of
the Armada 370 and Armada XP platforms was evaluation boards with
those very early steppings, we submitted Device Tree that assumed the
internal registers were mapped at 0xd0000000. This is the case for
Armada 370 DB, Armada XP DB and Armada XP GP.
However, in practice, since Marvell has been shipping the evaluation
boards with production steppings of the SoC, they are shipping those
boards with bootloaders that remap the registers to 0xf1000000. We
have already changed this internal register address to 0xf1000000 for
the Armada XP DB in commit 82066bdb5a75 and for the Armada XP GP in
commit 91ed32200e6e (both merged in v3.15).
We only recently got our hand on an Armada 370 DB with a production
stepping of the SoC, which uses a bootloader that remaps internal
registers at 0xf1000000. Therefore, this commit aligns the Armada 370
DB to be like the Armada XP DB and Armada XP GP: assume that the
internal registers are mapped at 0xf1000000.
We would like to stress out the fact that the usage of 0xd0000000 as
the internal register base address was a temporary workaround for
early steppings deficiencies, and that the real long-term solution is
the usage of 0xf1000000. Having 0xd0000000 is an *accident* in the
life of the Marvell platform support in the kernel, as is confirmed by
the usage of 0xf1000000 in all previous Marvell platforms (Dove,
Kirkwood, Orion).
There are unfortunately a number of commercial devices that continue
to use 0xd0000000 even though they use production steppings of the
SoC, simply because the vendors of such devices have never bothered
using a more recent bootloader version from Marvell. There is not much
we can do about it, and we plan on keeping 0xd0000000 in the Device
Tree of such devices.
The main reason for remapping the internal registers at 0xf1000000
instead of 0xd0000000 is that it leaves more space in the 0 -> 4 GB
part of the physical address space for RAM. With registers at
0xd0000000, all RAM between 0xd0000000 to 0xffffffff is lost because
it's covered by the I/O registers.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Jason Cooper <jason@lakedameon.net>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-04-07 12:23:03 +00:00
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*
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* Note: this Device Tree assumes that the bootloader has remapped the
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* internal registers to 0xf1000000 (instead of the default
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* 0xd0000000). The 0xf1000000 is the default used by the recent,
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* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
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* boards were delivered with an older version of the bootloader that
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* left internal registers mapped at 0xd0000000. If you are in this
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* situation, you should either update your bootloader (preferred
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* solution) or the below Device Tree should be adjusted.
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2012-06-13 17:01:28 +00:00
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*/
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/dts-v1/;
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2013-07-26 13:17:56 +00:00
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#include "armada-370.dtsi"
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2012-06-13 17:01:28 +00:00
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/ {
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model = "Marvell Armada 370 Evaluation Board";
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compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
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chosen {
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2015-03-03 14:41:02 +00:00
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stdout-path = "serial0:115200n8";
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2012-06-13 17:01:28 +00:00
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};
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2016-11-06 08:29:35 +00:00
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memory@0 {
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2012-06-13 17:01:28 +00:00
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device_type = "memory";
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2013-01-10 12:15:14 +00:00
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reg = <0x00000000 0x40000000>; /* 1 GB */
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2012-06-13 17:01:28 +00:00
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};
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soc {
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ARM: mvebu: use 0xf1000000 as internal registers on Armada 370 DB
All Marvell EBU SoCs (Kirkwood, Dove, Orion, Armada) have the
capability of changing the location of their internal registers (i.e
the registers for most hardware blocks inside the SoC). When coming
out of reset, the internal registers are mapped at 0xd0000000, but
since years and years, the tradition has been to have the internal
registers remapped at 0xf1000000 by the bootloader, and Linux has
since then assumed that the internal registers for the SoC were
located at 0xf1000000 on Kirkwood, Dove, Orion, etc. Linux has never
been aware that those registers are remappable (and there is no way to
know where they are mapped at runtime, since the register to configure
the address of the registers is itself within the internal registers).
Then came the Armada 370 and Armada XP, in which some of the very
early silicon steppings had an issue, which forced to use 0xd0000000:
the SoC was no longer working properly when the internal registers
were remapped at 0xf1000000. This issue is only affecting very early
silicon steppings and production steppings are not affected: the issue
has been fixed in between.
Since what we (Free Electrons) used to do the initial submission of
the Armada 370 and Armada XP platforms was evaluation boards with
those very early steppings, we submitted Device Tree that assumed the
internal registers were mapped at 0xd0000000. This is the case for
Armada 370 DB, Armada XP DB and Armada XP GP.
However, in practice, since Marvell has been shipping the evaluation
boards with production steppings of the SoC, they are shipping those
boards with bootloaders that remap the registers to 0xf1000000. We
have already changed this internal register address to 0xf1000000 for
the Armada XP DB in commit 82066bdb5a75 and for the Armada XP GP in
commit 91ed32200e6e (both merged in v3.15).
We only recently got our hand on an Armada 370 DB with a production
stepping of the SoC, which uses a bootloader that remaps internal
registers at 0xf1000000. Therefore, this commit aligns the Armada 370
DB to be like the Armada XP DB and Armada XP GP: assume that the
internal registers are mapped at 0xf1000000.
We would like to stress out the fact that the usage of 0xd0000000 as
the internal register base address was a temporary workaround for
early steppings deficiencies, and that the real long-term solution is
the usage of 0xf1000000. Having 0xd0000000 is an *accident* in the
life of the Marvell platform support in the kernel, as is confirmed by
the usage of 0xf1000000 in all previous Marvell platforms (Dove,
Kirkwood, Orion).
There are unfortunately a number of commercial devices that continue
to use 0xd0000000 even though they use production steppings of the
SoC, simply because the vendors of such devices have never bothered
using a more recent bootloader version from Marvell. There is not much
we can do about it, and we plan on keeping 0xd0000000 in the Device
Tree of such devices.
The main reason for remapping the internal registers at 0xf1000000
instead of 0xd0000000 is that it leaves more space in the 0 -> 4 GB
part of the physical address space for RAM. With registers at
0xd0000000, all RAM between 0xd0000000 to 0xffffffff is lost because
it's covered by the I/O registers.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Jason Cooper <jason@lakedameon.net>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-04-07 12:23:03 +00:00
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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2015-08-18 08:08:55 +00:00
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
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2013-07-26 13:17:57 +00:00
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2013-04-12 14:29:09 +00:00
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internal-regs {
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serial@12000 {
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status = "okay";
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2012-09-04 13:06:44 +00:00
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};
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2013-04-12 14:29:09 +00:00
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sata@a0000 {
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nr-ports = <2>;
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status = "okay";
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2012-09-04 13:06:44 +00:00
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};
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2013-04-12 14:29:09 +00:00
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ethernet@70000 {
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2014-08-11 12:14:38 +00:00
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pinctrl-0 = <&ge0_rgmii_pins>;
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pinctrl-names = "default";
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2013-04-12 14:29:09 +00:00
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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ethernet@74000 {
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2014-08-11 12:14:38 +00:00
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pinctrl-0 = <&ge1_rgmii_pins>;
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pinctrl-names = "default";
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2013-04-12 14:29:09 +00:00
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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2013-01-23 15:26:31 +00:00
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2014-02-12 17:21:00 +00:00
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i2c@11000 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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2014-04-18 07:41:44 +00:00
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clock-frequency = <100000>;
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2014-02-12 17:21:00 +00:00
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status = "okay";
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audio_codec: audio-codec@4a {
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2014-10-28 16:08:43 +00:00
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#sound-dai-cells = <0>;
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2014-02-12 17:21:00 +00:00
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compatible = "cirrus,cs42l51";
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reg = <0x4a>;
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};
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};
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audio-controller@30000 {
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pinctrl-0 = <&i2s_pins2>;
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pinctrl-names = "default";
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status = "okay";
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};
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2013-04-12 14:29:09 +00:00
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mvsdio@d4000 {
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pinctrl-0 = <&sdio_pins1>;
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pinctrl-names = "default";
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/*
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* This device is disabled by default, because
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* using the SD card connector requires
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* changing the default CON40 connector
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* "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
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* different connector
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* "DB-88F6710_MPP_RGMII_SD_Jumper".
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*/
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status = "disabled";
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/* No CD or WP GPIOs */
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2013-05-13 21:18:58 +00:00
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broken-cd;
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2013-04-12 14:29:09 +00:00
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};
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2013-02-05 20:54:55 +00:00
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2013-04-12 14:29:09 +00:00
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usb@50000 {
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status = "okay";
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};
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2013-02-05 20:54:55 +00:00
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2013-04-12 14:29:09 +00:00
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usb@51000 {
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status = "okay";
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2013-02-05 20:54:55 +00:00
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};
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2013-04-09 21:06:38 +00:00
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2016-02-10 16:29:16 +00:00
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nand@d0000 {
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status = "okay";
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num-cs = <1>;
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marvell,nand-keep-config;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0 0x800000>;
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};
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partition@800000 {
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label = "Linux";
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reg = <0x800000 0x800000>;
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};
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partition@1000000 {
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label = "Filesystem";
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reg = <0x1000000 0x3f000000>;
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};
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};
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};
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2013-11-25 16:26:47 +00:00
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|
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};
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2012-06-13 17:01:28 +00:00
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};
|
2014-02-12 17:21:00 +00:00
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sound {
|
2014-10-28 16:08:43 +00:00
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compatible = "simple-audio-card";
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simple-audio-card,name = "Armada 370 DB Audio";
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simple-audio-card,mclk-fs = <256>;
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simple-audio-card,widgets =
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"Headphone", "Out Jack",
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"Line", "In Jack";
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simple-audio-card,routing =
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"Out Jack", "HPL",
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"Out Jack", "HPR",
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"AIN1L", "In Jack",
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|
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"AIN1L", "In Jack";
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status = "okay";
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simple-audio-card,dai-link@0 {
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format = "i2s";
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|
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cpu {
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sound-dai = <&audio_controller 0>;
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};
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codec {
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sound-dai = <&audio_codec>;
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};
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};
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simple-audio-card,dai-link@1 {
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format = "i2s";
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cpu {
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sound-dai = <&audio_controller 1>;
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};
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codec {
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sound-dai = <&spdif_out>;
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};
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};
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simple-audio-card,dai-link@2 {
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format = "i2s";
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cpu {
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sound-dai = <&audio_controller 1>;
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};
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codec {
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sound-dai = <&spdif_in>;
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};
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|
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|
};
|
2014-02-12 17:21:00 +00:00
|
|
|
};
|
2014-02-12 17:21:01 +00:00
|
|
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|
spdif_out: spdif-out {
|
2014-10-28 16:08:43 +00:00
|
|
|
#sound-dai-cells = <0>;
|
|
|
|
|
compatible = "linux,spdif-dit";
|
2014-02-12 17:21:01 +00:00
|
|
|
};
|
|
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|
|
|
|
spdif_in: spdif-in {
|
2014-10-28 16:08:43 +00:00
|
|
|
#sound-dai-cells = <0>;
|
|
|
|
|
compatible = "linux,spdif-dir";
|
2014-02-12 17:21:01 +00:00
|
|
|
};
|
2012-06-13 17:01:28 +00:00
|
|
|
};
|
2016-11-05 18:20:09 +00:00
|
|
|
|
|
|
|
|
&pciec {
|
|
|
|
|
status = "okay";
|
|
|
|
|
/*
|
|
|
|
|
* The two PCIe units are accessible through
|
|
|
|
|
* both standard PCIe slots and mini-PCIe
|
|
|
|
|
* slots on the board.
|
|
|
|
|
*/
|
|
|
|
|
pcie@1,0 {
|
|
|
|
|
/* Port 0, Lane 0 */
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie@2,0 {
|
|
|
|
|
/* Port 1, Lane 0 */
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2016-11-04 16:54:54 +00:00
|
|
|
&mdio {
|
|
|
|
|
pinctrl-0 = <&mdio_pins>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
phy0: ethernet-phy@0 {
|
|
|
|
|
reg = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
phy1: ethernet-phy@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2016-07-13 09:55:18 +00:00
|
|
|
|
|
|
|
|
&spi0 {
|
|
|
|
|
pinctrl-0 = <&spi0_pins2>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
spi-flash@0 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
compatible = "mx25l25635e", "jedec,spi-nor";
|
|
|
|
|
reg = <0>; /* Chip select 0 */
|
|
|
|
|
spi-max-frequency = <50000000>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
