2011-01-08 05:36:14 +00:00
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/*
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* tegra_i2s.c - Tegra I2S driver
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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* Copyright (C) 2010 - NVIDIA, Inc.
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*
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* Based on code copyright/by:
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*
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* Copyright (c) 2009-2010, NVIDIA Corporation.
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* Scott Peterson <speterson@nvidia.com>
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*
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* Copyright (C) 2010 Google, Inc.
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* Iliyan Malchev <malchev@google.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/debugfs.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <mach/iomap.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "tegra_das.h"
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#include "tegra_i2s.h"
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#define DRV_NAME "tegra-i2s"
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static inline void tegra_i2s_write(struct tegra_i2s *i2s, u32 reg, u32 val)
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{
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__raw_writel(val, i2s->regs + reg);
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}
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static inline u32 tegra_i2s_read(struct tegra_i2s *i2s, u32 reg)
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{
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return __raw_readl(i2s->regs + reg);
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}
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#ifdef CONFIG_DEBUG_FS
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static int tegra_i2s_show(struct seq_file *s, void *unused)
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{
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#define REG(r) { r, #r }
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static const struct {
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int offset;
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const char *name;
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} regs[] = {
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REG(TEGRA_I2S_CTRL),
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REG(TEGRA_I2S_STATUS),
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REG(TEGRA_I2S_TIMING),
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REG(TEGRA_I2S_FIFO_SCR),
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REG(TEGRA_I2S_PCM_CTRL),
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REG(TEGRA_I2S_NW_CTRL),
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REG(TEGRA_I2S_TDM_CTRL),
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REG(TEGRA_I2S_TDM_TX_RX_CTRL),
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};
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#undef REG
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struct tegra_i2s *i2s = s->private;
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int i;
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for (i = 0; i < ARRAY_SIZE(regs); i++) {
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u32 val = tegra_i2s_read(i2s, regs[i].offset);
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seq_printf(s, "%s = %08x\n", regs[i].name, val);
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}
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return 0;
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}
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static int tegra_i2s_debug_open(struct inode *inode, struct file *file)
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{
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return single_open(file, tegra_i2s_show, inode->i_private);
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}
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static const struct file_operations tegra_i2s_debug_fops = {
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.open = tegra_i2s_debug_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id)
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{
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char name[] = DRV_NAME ".0";
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snprintf(name, sizeof(name), DRV_NAME".%1d", id);
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2011-01-10 22:25:21 +00:00
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i2s->debug = debugfs_create_file(name, S_IRUGO, snd_soc_debugfs_root,
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2011-01-08 05:36:14 +00:00
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i2s, &tegra_i2s_debug_fops);
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}
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static void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
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{
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if (i2s->debug)
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debugfs_remove(i2s->debug);
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}
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#else
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2011-05-16 20:19:27 +00:00
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static inline void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id)
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2011-01-08 05:36:14 +00:00
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{
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}
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static inline void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
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{
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}
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#endif
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static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
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unsigned int fmt)
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{
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struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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default:
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return -EINVAL;
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}
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i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_MASTER_ENABLE;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_MASTER_ENABLE;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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break;
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default:
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return -EINVAL;
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}
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i2s->reg_ctrl &= ~(TEGRA_I2S_CTRL_BIT_FORMAT_MASK |
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TEGRA_I2S_CTRL_LRCK_MASK);
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_DSP_A:
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
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break;
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case SND_SOC_DAIFMT_DSP_B:
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_R_LOW;
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break;
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case SND_SOC_DAIFMT_I2S:
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_I2S;
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_RJM;
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_LJM;
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct device *dev = substream->pcm->card->dev;
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struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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u32 reg;
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int ret, sample_size, srate, i2sclock, bitcnt;
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i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_BIT_SIZE_MASK;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_16;
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sample_size = 16;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_24;
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sample_size = 24;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_32;
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sample_size = 32;
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break;
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default:
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return -EINVAL;
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}
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srate = params_rate(params);
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/* Final "* 2" required by Tegra hardware */
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i2sclock = srate * params_channels(params) * sample_size * 2;
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ret = clk_set_rate(i2s->clk_i2s, i2sclock);
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if (ret) {
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dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
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return ret;
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}
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bitcnt = (i2sclock / (2 * srate)) - 1;
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if (bitcnt < 0 || bitcnt > TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
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return -EINVAL;
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reg = bitcnt << TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
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if (i2sclock % (2 * srate))
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reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE;
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ASoC: Tegra: I2S: Ensure clock is enabled when writing regs
The I2S controller needs a clock to respond to register writes. Without
this, register writes will at worst hang the CPU. In practice, I've only
observed writes being dropped.
Luckily, the dropped register writes historically had no effect:
TEGRA_I2S_TIMING: The value we wrote was the reset default.
TEGRA_I2S_FIFO_SCR: The default was for the FIFOs to request more data
when one slot was empty. The requested value was for the FIFOs to request
when four slots were empty. The DMA controller in the mainline kernel is
configured to burst a single entry at a time into the FIFO, hence there
was no issue. The only negative effect was on bus efficiency losses due
to an increased number of arbitration attempts.
However, in various non-upstream changes, the DMA controller now bursts
four entries at a time into the FIFO. If there is only space for one
entry, the data is simply dropped. In practice, this resulted in 3/4 of
samples being dropped, and playback at 4x the expected rate and pitch.
By fixing the clocking issue, this is solved.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-07-01 19:56:13 +00:00
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if (!i2s->clk_refs)
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clk_enable(i2s->clk_i2s);
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2011-01-08 05:36:14 +00:00
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tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg);
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tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR,
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TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
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TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
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ASoC: Tegra: I2S: Ensure clock is enabled when writing regs
The I2S controller needs a clock to respond to register writes. Without
this, register writes will at worst hang the CPU. In practice, I've only
observed writes being dropped.
Luckily, the dropped register writes historically had no effect:
TEGRA_I2S_TIMING: The value we wrote was the reset default.
TEGRA_I2S_FIFO_SCR: The default was for the FIFOs to request more data
when one slot was empty. The requested value was for the FIFOs to request
when four slots were empty. The DMA controller in the mainline kernel is
configured to burst a single entry at a time into the FIFO, hence there
was no issue. The only negative effect was on bus efficiency losses due
to an increased number of arbitration attempts.
However, in various non-upstream changes, the DMA controller now bursts
four entries at a time into the FIFO. If there is only space for one
entry, the data is simply dropped. In practice, this resulted in 3/4 of
samples being dropped, and playback at 4x the expected rate and pitch.
By fixing the clocking issue, this is solved.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-07-01 19:56:13 +00:00
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if (!i2s->clk_refs)
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clk_disable(i2s->clk_i2s);
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2011-01-08 05:36:14 +00:00
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return 0;
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}
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static void tegra_i2s_start_playback(struct tegra_i2s *i2s)
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{
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO1_ENABLE;
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tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
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}
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static void tegra_i2s_stop_playback(struct tegra_i2s *i2s)
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{
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i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO1_ENABLE;
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tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
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}
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static void tegra_i2s_start_capture(struct tegra_i2s *i2s)
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{
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i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO2_ENABLE;
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tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
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}
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static void tegra_i2s_stop_capture(struct tegra_i2s *i2s)
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{
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i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO2_ENABLE;
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tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
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}
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static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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case SNDRV_PCM_TRIGGER_RESUME:
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if (!i2s->clk_refs)
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clk_enable(i2s->clk_i2s);
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i2s->clk_refs++;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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tegra_i2s_start_playback(i2s);
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else
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tegra_i2s_start_capture(i2s);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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tegra_i2s_stop_playback(i2s);
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else
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tegra_i2s_stop_capture(i2s);
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i2s->clk_refs--;
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if (!i2s->clk_refs)
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clk_disable(i2s->clk_i2s);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int tegra_i2s_probe(struct snd_soc_dai *dai)
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{
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struct tegra_i2s * i2s = snd_soc_dai_get_drvdata(dai);
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dai->capture_dma_data = &i2s->capture_dma_data;
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dai->playback_dma_data = &i2s->playback_dma_data;
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return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct snd_soc_dai_ops tegra_i2s_dai_ops = {
|
|
|
|
.set_fmt = tegra_i2s_set_fmt,
|
|
|
|
.hw_params = tegra_i2s_hw_params,
|
|
|
|
.trigger = tegra_i2s_trigger,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct snd_soc_dai_driver tegra_i2s_dai[] = {
|
|
|
|
{
|
|
|
|
.name = DRV_NAME ".0",
|
|
|
|
.probe = tegra_i2s_probe,
|
|
|
|
.playback = {
|
|
|
|
.channels_min = 2,
|
|
|
|
.channels_max = 2,
|
|
|
|
.rates = SNDRV_PCM_RATE_8000_96000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.capture = {
|
|
|
|
.channels_min = 2,
|
|
|
|
.channels_max = 2,
|
|
|
|
.rates = SNDRV_PCM_RATE_8000_96000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.ops = &tegra_i2s_dai_ops,
|
|
|
|
.symmetric_rates = 1,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = DRV_NAME ".1",
|
|
|
|
.probe = tegra_i2s_probe,
|
|
|
|
.playback = {
|
|
|
|
.channels_min = 2,
|
|
|
|
.channels_max = 2,
|
|
|
|
.rates = SNDRV_PCM_RATE_8000_96000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.capture = {
|
|
|
|
.channels_min = 2,
|
|
|
|
.channels_max = 2,
|
|
|
|
.rates = SNDRV_PCM_RATE_8000_96000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.ops = &tegra_i2s_dai_ops,
|
|
|
|
.symmetric_rates = 1,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct tegra_i2s * i2s;
|
|
|
|
struct resource *mem, *memregion, *dmareq;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if ((pdev->id < 0) ||
|
|
|
|
(pdev->id >= ARRAY_SIZE(tegra_i2s_dai))) {
|
|
|
|
dev_err(&pdev->dev, "ID %d out of range\n", pdev->id);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME: Until a codec driver exists for the tegra DAS, hard-code a
|
|
|
|
* 1:1 mapping between audio controllers and audio ports.
|
|
|
|
*/
|
|
|
|
ret = tegra_das_connect_dap_to_dac(TEGRA_DAS_DAP_ID_1 + pdev->id,
|
|
|
|
TEGRA_DAS_DAP_SEL_DAC1 + pdev->id);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "Can't set up DAP connection\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
ret = tegra_das_connect_dac_to_dap(TEGRA_DAS_DAC_ID_1 + pdev->id,
|
|
|
|
TEGRA_DAS_DAC_SEL_DAP1 + pdev->id);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "Can't set up DAC connection\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
i2s = kzalloc(sizeof(struct tegra_i2s), GFP_KERNEL);
|
|
|
|
if (!i2s) {
|
|
|
|
dev_err(&pdev->dev, "Can't allocate tegra_i2s\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
dev_set_drvdata(&pdev->dev, i2s);
|
|
|
|
|
2011-07-01 19:56:14 +00:00
|
|
|
i2s->clk_i2s = clk_get(&pdev->dev, NULL);
|
2011-01-11 19:48:53 +00:00
|
|
|
if (IS_ERR(i2s->clk_i2s)) {
|
2011-01-28 21:26:41 +00:00
|
|
|
dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
|
2011-01-08 05:36:14 +00:00
|
|
|
ret = PTR_ERR(i2s->clk_i2s);
|
|
|
|
goto err_free;
|
|
|
|
}
|
|
|
|
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!mem) {
|
|
|
|
dev_err(&pdev->dev, "No memory resource\n");
|
|
|
|
ret = -ENODEV;
|
|
|
|
goto err_clk_put;
|
|
|
|
}
|
|
|
|
|
|
|
|
dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
|
|
|
|
if (!dmareq) {
|
|
|
|
dev_err(&pdev->dev, "No DMA resource\n");
|
|
|
|
ret = -ENODEV;
|
|
|
|
goto err_clk_put;
|
|
|
|
}
|
|
|
|
|
|
|
|
memregion = request_mem_region(mem->start, resource_size(mem),
|
|
|
|
DRV_NAME);
|
|
|
|
if (!memregion) {
|
|
|
|
dev_err(&pdev->dev, "Memory region already claimed\n");
|
|
|
|
ret = -EBUSY;
|
|
|
|
goto err_clk_put;
|
|
|
|
}
|
|
|
|
|
|
|
|
i2s->regs = ioremap(mem->start, resource_size(mem));
|
|
|
|
if (!i2s->regs) {
|
|
|
|
dev_err(&pdev->dev, "ioremap failed\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_release;
|
|
|
|
}
|
|
|
|
|
|
|
|
i2s->capture_dma_data.addr = mem->start + TEGRA_I2S_FIFO2;
|
|
|
|
i2s->capture_dma_data.wrap = 4;
|
|
|
|
i2s->capture_dma_data.width = 32;
|
|
|
|
i2s->capture_dma_data.req_sel = dmareq->start;
|
|
|
|
|
|
|
|
i2s->playback_dma_data.addr = mem->start + TEGRA_I2S_FIFO1;
|
|
|
|
i2s->playback_dma_data.wrap = 4;
|
|
|
|
i2s->playback_dma_data.width = 32;
|
|
|
|
i2s->playback_dma_data.req_sel = dmareq->start;
|
|
|
|
|
|
|
|
i2s->reg_ctrl = TEGRA_I2S_CTRL_FIFO_FORMAT_PACKED;
|
|
|
|
|
|
|
|
ret = snd_soc_register_dai(&pdev->dev, &tegra_i2s_dai[pdev->id]);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_unmap;
|
|
|
|
}
|
|
|
|
|
|
|
|
tegra_i2s_debug_add(i2s, pdev->id);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_unmap:
|
|
|
|
iounmap(i2s->regs);
|
|
|
|
err_release:
|
|
|
|
release_mem_region(mem->start, resource_size(mem));
|
|
|
|
err_clk_put:
|
|
|
|
clk_put(i2s->clk_i2s);
|
|
|
|
err_free:
|
|
|
|
kfree(i2s);
|
|
|
|
exit:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __devexit tegra_i2s_platform_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct tegra_i2s *i2s = dev_get_drvdata(&pdev->dev);
|
|
|
|
struct resource *res;
|
|
|
|
|
|
|
|
snd_soc_unregister_dai(&pdev->dev);
|
|
|
|
|
|
|
|
tegra_i2s_debug_remove(i2s);
|
|
|
|
|
|
|
|
iounmap(i2s->regs);
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
release_mem_region(res->start, resource_size(res));
|
|
|
|
|
|
|
|
clk_put(i2s->clk_i2s);
|
|
|
|
|
|
|
|
kfree(i2s);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver tegra_i2s_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
},
|
|
|
|
.probe = tegra_i2s_platform_probe,
|
|
|
|
.remove = __devexit_p(tegra_i2s_platform_remove),
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init snd_tegra_i2s_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&tegra_i2s_driver);
|
|
|
|
}
|
|
|
|
module_init(snd_tegra_i2s_init);
|
|
|
|
|
|
|
|
static void __exit snd_tegra_i2s_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&tegra_i2s_driver);
|
|
|
|
}
|
|
|
|
module_exit(snd_tegra_i2s_exit);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
|
|
|
|
MODULE_DESCRIPTION("Tegra I2S ASoC driver");
|
|
|
|
MODULE_LICENSE("GPL");
|
2011-02-10 22:37:19 +00:00
|
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|