2012-03-05 11:49:27 +00:00
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/*
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* Low-level CPU initialisation
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* Based on arch/arm/kernel/head.S
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*
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* Copyright (C) 1994-2002 Russell King
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* Copyright (C) 2003-2012 ARM Ltd.
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* Authors: Catalin Marinas <catalin.marinas@arm.com>
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* Will Deacon <will.deacon@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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2014-03-26 18:25:55 +00:00
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#include <asm/cache.h>
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2012-08-29 17:32:18 +00:00
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#include <asm/cputype.h>
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2012-03-05 11:49:27 +00:00
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#include <asm/memory.h>
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#include <asm/thread_info.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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2012-10-26 14:40:05 +00:00
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#include <asm/virt.h>
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2012-03-05 11:49:27 +00:00
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/*
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* swapper_pg_dir is the virtual address of the initial page table. We place
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* the page tables 3 * PAGE_SIZE below KERNEL_RAM_VADDR. The idmap_pg_dir has
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* 2 pages and is placed below swapper_pg_dir.
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*/
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#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
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#if (KERNEL_RAM_VADDR & 0xfffff) != 0x80000
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#error KERNEL_RAM_VADDR must start at 0xXXX80000
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#endif
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#define SWAPPER_DIR_SIZE (3 * PAGE_SIZE)
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#define IDMAP_DIR_SIZE (2 * PAGE_SIZE)
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.globl swapper_pg_dir
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.equ swapper_pg_dir, KERNEL_RAM_VADDR - SWAPPER_DIR_SIZE
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.globl idmap_pg_dir
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.equ idmap_pg_dir, swapper_pg_dir - IDMAP_DIR_SIZE
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.macro pgtbl, ttb0, ttb1, phys
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add \ttb1, \phys, #TEXT_OFFSET - SWAPPER_DIR_SIZE
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sub \ttb0, \ttb1, #IDMAP_DIR_SIZE
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.endm
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#ifdef CONFIG_ARM64_64K_PAGES
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#define BLOCK_SHIFT PAGE_SHIFT
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#define BLOCK_SIZE PAGE_SIZE
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#else
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#define BLOCK_SHIFT SECTION_SHIFT
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#define BLOCK_SIZE SECTION_SIZE
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#endif
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#define KERNEL_START KERNEL_RAM_VADDR
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#define KERNEL_END _end
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/*
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* Initial memory map attributes.
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*/
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#ifndef CONFIG_SMP
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#define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF
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#define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF
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#else
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#define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
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#define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
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#endif
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#ifdef CONFIG_ARM64_64K_PAGES
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#define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
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#else
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#define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
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#endif
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/*
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* Kernel startup entry point.
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* ---------------------------
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*
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* The requirements are:
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* MMU = off, D-cache = off, I-cache = on or off,
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* x0 = physical address to the FDT blob.
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*
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* This code is mostly position independent so you call this at
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* __pa(PAGE_OFFSET + TEXT_OFFSET).
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*
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* Note that the callee-saved registers are used for storing variables
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* that are useful before the MMU is enabled. The allocations are described
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* in the entry routines.
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*/
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__HEAD
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/*
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* DO NOT MODIFY. Image header expected by Linux boot-loaders.
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*/
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2014-04-16 02:47:52 +00:00
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#ifdef CONFIG_EFI
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efi_head:
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/*
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* This add instruction has no meaningful effect except that
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* its opcode forms the magic "MZ" signature required by UEFI.
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*/
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add x13, x18, #0x16
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b stext
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#else
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2012-03-05 11:49:27 +00:00
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b stext // branch to kernel start, magic
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.long 0 // reserved
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2014-04-16 02:47:52 +00:00
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#endif
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2012-03-05 11:49:27 +00:00
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.quad TEXT_OFFSET // Image load offset from start of RAM
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.quad 0 // reserved
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.quad 0 // reserved
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2013-08-14 23:10:00 +00:00
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.quad 0 // reserved
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.quad 0 // reserved
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.quad 0 // reserved
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.byte 0x41 // Magic number, "ARM\x64"
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.byte 0x52
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.byte 0x4d
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.byte 0x64
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2014-04-16 02:47:52 +00:00
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#ifdef CONFIG_EFI
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.long pe_header - efi_head // Offset to the PE header.
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#else
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2013-08-14 23:10:00 +00:00
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.word 0 // reserved
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2014-04-16 02:47:52 +00:00
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#endif
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#ifdef CONFIG_EFI
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.align 3
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pe_header:
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.ascii "PE"
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.short 0
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coff_header:
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.short 0xaa64 // AArch64
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.short 2 // nr_sections
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.long 0 // TimeDateStamp
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.long 0 // PointerToSymbolTable
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.long 1 // NumberOfSymbols
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.short section_table - optional_header // SizeOfOptionalHeader
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.short 0x206 // Characteristics.
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// IMAGE_FILE_DEBUG_STRIPPED |
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// IMAGE_FILE_EXECUTABLE_IMAGE |
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// IMAGE_FILE_LINE_NUMS_STRIPPED
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optional_header:
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.short 0x20b // PE32+ format
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.byte 0x02 // MajorLinkerVersion
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.byte 0x14 // MinorLinkerVersion
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.long _edata - stext // SizeOfCode
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.long 0 // SizeOfInitializedData
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.long 0 // SizeOfUninitializedData
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.long efi_stub_entry - efi_head // AddressOfEntryPoint
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.long stext - efi_head // BaseOfCode
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extra_header_fields:
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.quad 0 // ImageBase
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.long 0x20 // SectionAlignment
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.long 0x8 // FileAlignment
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.short 0 // MajorOperatingSystemVersion
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.short 0 // MinorOperatingSystemVersion
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.short 0 // MajorImageVersion
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.short 0 // MinorImageVersion
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.short 0 // MajorSubsystemVersion
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.short 0 // MinorSubsystemVersion
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.long 0 // Win32VersionValue
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.long _edata - efi_head // SizeOfImage
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// Everything before the kernel image is considered part of the header
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.long stext - efi_head // SizeOfHeaders
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.long 0 // CheckSum
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.short 0xa // Subsystem (EFI application)
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.short 0 // DllCharacteristics
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.quad 0 // SizeOfStackReserve
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.quad 0 // SizeOfStackCommit
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.quad 0 // SizeOfHeapReserve
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.quad 0 // SizeOfHeapCommit
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.long 0 // LoaderFlags
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.long 0x6 // NumberOfRvaAndSizes
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.quad 0 // ExportTable
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.quad 0 // ImportTable
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.quad 0 // ResourceTable
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.quad 0 // ExceptionTable
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.quad 0 // CertificationTable
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.quad 0 // BaseRelocationTable
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// Section table
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section_table:
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/*
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* The EFI application loader requires a relocation section
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* because EFI applications must be relocatable. This is a
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* dummy section as far as we are concerned.
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*/
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.ascii ".reloc"
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.byte 0
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.byte 0 // end of 0 padding of section name
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.long 0
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.long 0
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.long 0 // SizeOfRawData
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.long 0 // PointerToRawData
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.long 0 // PointerToRelocations
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.long 0 // PointerToLineNumbers
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.short 0 // NumberOfRelocations
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.short 0 // NumberOfLineNumbers
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.long 0x42100040 // Characteristics (section flags)
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.ascii ".text"
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.byte 0
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.byte 0
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.byte 0 // end of 0 padding of section name
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.long _edata - stext // VirtualSize
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.long stext - efi_head // VirtualAddress
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.long _edata - stext // SizeOfRawData
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.long stext - efi_head // PointerToRawData
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.long 0 // PointerToRelocations (0 for executables)
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.long 0 // PointerToLineNumbers (0 for executables)
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.short 0 // NumberOfRelocations (0 for executables)
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.short 0 // NumberOfLineNumbers (0 for executables)
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.long 0xe0500020 // Characteristics (section flags)
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.align 5
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#endif
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2012-03-05 11:49:27 +00:00
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ENTRY(stext)
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mov x21, x0 // x21=FDT
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2013-10-11 13:52:16 +00:00
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bl el2_setup // Drop to EL1, w20=cpu_boot_mode
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2012-10-26 14:40:05 +00:00
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bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
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2013-10-11 13:52:16 +00:00
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bl set_cpu_boot_mode_flag
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2012-03-05 11:49:27 +00:00
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mrs x22, midr_el1 // x22=cpuid
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mov x0, x22
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bl lookup_processor_type
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mov x23, x0 // x23=current cpu_table
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cbz x23, __error_p // invalid processor (x23=0)?
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bl __vet_fdt
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bl __create_page_tables // x25=TTBR0, x26=TTBR1
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/*
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* The following calls CPU specific code in a position independent
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* manner. See arch/arm64/mm/proc.S for details. x23 = base of
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* cpu_info structure selected by lookup_processor_type above.
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* On return, the CPU will be ready for the MMU to be turned on and
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* the TCR will have been set.
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*/
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ldr x27, __switch_data // address to jump to after
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// MMU has been enabled
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adr lr, __enable_mmu // return (PIC) address
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ldr x12, [x23, #CPU_INFO_SETUP]
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add x12, x12, x28 // __virt_to_phys
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br x12 // initialise processor
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ENDPROC(stext)
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/*
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* If we're fortunate enough to boot at EL2, ensure that the world is
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* sane before dropping to EL1.
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2013-10-11 13:52:16 +00:00
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*
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* Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
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* booted in EL1 or EL2 respectively.
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2012-03-05 11:49:27 +00:00
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*/
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ENTRY(el2_setup)
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mrs x0, CurrentEL
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2014-06-06 13:16:21 +00:00
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cmp x0, #CurrentEL_EL2
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2013-10-11 13:52:17 +00:00
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b.ne 1f
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mrs x0, sctlr_el2
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CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
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CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
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msr sctlr_el2, x0
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b 2f
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1: mrs x0, sctlr_el1
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CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
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CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
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msr sctlr_el1, x0
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2013-10-11 13:52:16 +00:00
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mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
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2013-10-11 13:52:17 +00:00
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isb
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2012-03-05 11:49:27 +00:00
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ret
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/* Hyp configuration. */
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2013-10-11 13:52:17 +00:00
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2: mov x0, #(1 << 31) // 64-bit EL1
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2012-03-05 11:49:27 +00:00
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msr hcr_el2, x0
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/* Generic timers. */
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mrs x0, cnthctl_el2
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orr x0, x0, #3 // Enable EL1 physical timers
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msr cnthctl_el2, x0
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2012-11-29 22:48:31 +00:00
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msr cntvoff_el2, xzr // Clear virtual offset
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2012-03-05 11:49:27 +00:00
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/* Populate ID registers. */
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mrs x0, midr_el1
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mrs x1, mpidr_el1
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msr vpidr_el2, x0
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msr vmpidr_el2, x1
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/* sctlr_el1 */
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mov x0, #0x0800 // Set/clear RES{1,0} bits
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2013-10-11 13:52:17 +00:00
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CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
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CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
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2012-03-05 11:49:27 +00:00
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msr sctlr_el1, x0
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/* Coprocessor traps. */
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mov x0, #0x33ff
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msr cptr_el2, x0 // Disable copro. traps to EL2
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#ifdef CONFIG_COMPAT
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msr hstr_el2, xzr // Disable CP15 traps to EL2
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#endif
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2012-11-06 19:27:59 +00:00
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/* Stage-2 translation */
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msr vttbr_el2, xzr
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2012-10-19 16:46:27 +00:00
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/* Hypervisor stub */
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adr x0, __hyp_stub_vectors
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msr vbar_el2, x0
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2012-03-05 11:49:27 +00:00
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/* spsr */
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mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
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PSR_MODE_EL1h)
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msr spsr_el2, x0
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msr elr_el2, lr
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2013-10-11 13:52:16 +00:00
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mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
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2012-03-05 11:49:27 +00:00
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eret
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ENDPROC(el2_setup)
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2013-10-11 13:52:16 +00:00
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/*
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|
|
* Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
|
|
|
|
* in x20. See arch/arm64/include/asm/virt.h for more info.
|
|
|
|
*/
|
|
|
|
ENTRY(set_cpu_boot_mode_flag)
|
|
|
|
ldr x1, =__boot_cpu_mode // Compute __boot_cpu_mode
|
|
|
|
add x1, x1, x28
|
|
|
|
cmp w20, #BOOT_CPU_MODE_EL2
|
|
|
|
b.ne 1f
|
|
|
|
add x1, x1, #4
|
2014-05-02 15:24:13 +00:00
|
|
|
1: str w20, [x1] // This CPU has booted in EL1
|
|
|
|
dmb sy
|
|
|
|
dc ivac, x1 // Invalidate potentially stale cache line
|
2013-10-11 13:52:16 +00:00
|
|
|
ret
|
|
|
|
ENDPROC(set_cpu_boot_mode_flag)
|
|
|
|
|
2012-10-26 14:40:05 +00:00
|
|
|
/*
|
|
|
|
* We need to find out the CPU boot mode long after boot, so we need to
|
|
|
|
* store it in a writable variable.
|
|
|
|
*
|
|
|
|
* This is not in .bss, because we set it sufficiently early that the boot-time
|
|
|
|
* zeroing of .bss would clobber it.
|
|
|
|
*/
|
2014-03-26 18:25:55 +00:00
|
|
|
.pushsection .data..cacheline_aligned
|
2012-10-26 14:40:05 +00:00
|
|
|
ENTRY(__boot_cpu_mode)
|
2014-03-26 18:25:55 +00:00
|
|
|
.align L1_CACHE_SHIFT
|
2012-10-26 14:40:05 +00:00
|
|
|
.long BOOT_CPU_MODE_EL2
|
|
|
|
.long 0
|
|
|
|
.popsection
|
|
|
|
|
2012-03-05 11:49:27 +00:00
|
|
|
.align 3
|
|
|
|
2: .quad .
|
|
|
|
.quad PAGE_OFFSET
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
.align 3
|
|
|
|
1: .quad .
|
|
|
|
.quad secondary_holding_pen_release
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This provides a "holding pen" for platforms to hold all secondary
|
|
|
|
* cores are held until we're ready for them to initialise.
|
|
|
|
*/
|
|
|
|
ENTRY(secondary_holding_pen)
|
2013-10-11 13:52:16 +00:00
|
|
|
bl el2_setup // Drop to EL1, w20=cpu_boot_mode
|
|
|
|
bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
|
|
|
|
bl set_cpu_boot_mode_flag
|
2012-03-05 11:49:27 +00:00
|
|
|
mrs x0, mpidr_el1
|
2012-08-29 17:32:18 +00:00
|
|
|
ldr x1, =MPIDR_HWID_BITMASK
|
|
|
|
and x0, x0, x1
|
2012-03-05 11:49:27 +00:00
|
|
|
adr x1, 1b
|
|
|
|
ldp x2, x3, [x1]
|
|
|
|
sub x1, x1, x2
|
|
|
|
add x3, x3, x1
|
|
|
|
pen: ldr x4, [x3]
|
|
|
|
cmp x4, x0
|
|
|
|
b.eq secondary_startup
|
|
|
|
wfe
|
|
|
|
b pen
|
|
|
|
ENDPROC(secondary_holding_pen)
|
arm64: factor out spin-table boot method
The arm64 kernel has an internal holding pen, which is necessary for
some systems where we can't bring CPUs online individually and must hold
multiple CPUs in a safe area until the kernel is able to handle them.
The current SMP infrastructure for arm64 is closely coupled to this
holding pen, and alternative boot methods must launch CPUs into the pen,
where they sit before they are launched into the kernel proper.
With PSCI (and possibly other future boot methods), we can bring CPUs
online individually, and need not perform the secondary_holding_pen
dance. Instead, this patch factors the holding pen management code out
to the spin-table boot method code, as it is the only boot method
requiring the pen.
A new entry point for secondaries, secondary_entry is added for other
boot methods to use, which bypasses the holding pen and its associated
overhead when bringing CPUs online. The smp.pen.text section is also
removed, as the pen can live in head.text without problem.
The cpu_operations structure is extended with two new functions,
cpu_boot and cpu_postboot, for bringing a cpu into the kernel and
performing any post-boot cleanup required by a bootmethod (e.g.
resetting the secondary_holding_pen_release to INVALID_HWID).
Documentation is added for cpu_operations.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-10-24 19:30:16 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Secondary entry point that jumps straight into the kernel. Only to
|
|
|
|
* be used where CPUs are brought online dynamically by the kernel.
|
|
|
|
*/
|
|
|
|
ENTRY(secondary_entry)
|
|
|
|
bl el2_setup // Drop to EL1
|
2013-11-18 18:56:42 +00:00
|
|
|
bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
|
|
|
|
bl set_cpu_boot_mode_flag
|
arm64: factor out spin-table boot method
The arm64 kernel has an internal holding pen, which is necessary for
some systems where we can't bring CPUs online individually and must hold
multiple CPUs in a safe area until the kernel is able to handle them.
The current SMP infrastructure for arm64 is closely coupled to this
holding pen, and alternative boot methods must launch CPUs into the pen,
where they sit before they are launched into the kernel proper.
With PSCI (and possibly other future boot methods), we can bring CPUs
online individually, and need not perform the secondary_holding_pen
dance. Instead, this patch factors the holding pen management code out
to the spin-table boot method code, as it is the only boot method
requiring the pen.
A new entry point for secondaries, secondary_entry is added for other
boot methods to use, which bypasses the holding pen and its associated
overhead when bringing CPUs online. The smp.pen.text section is also
removed, as the pen can live in head.text without problem.
The cpu_operations structure is extended with two new functions,
cpu_boot and cpu_postboot, for bringing a cpu into the kernel and
performing any post-boot cleanup required by a bootmethod (e.g.
resetting the secondary_holding_pen_release to INVALID_HWID).
Documentation is added for cpu_operations.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-10-24 19:30:16 +00:00
|
|
|
b secondary_startup
|
|
|
|
ENDPROC(secondary_entry)
|
2012-03-05 11:49:27 +00:00
|
|
|
|
|
|
|
ENTRY(secondary_startup)
|
|
|
|
/*
|
|
|
|
* Common entry point for secondary CPUs.
|
|
|
|
*/
|
|
|
|
mrs x22, midr_el1 // x22=cpuid
|
|
|
|
mov x0, x22
|
|
|
|
bl lookup_processor_type
|
|
|
|
mov x23, x0 // x23=current cpu_table
|
|
|
|
cbz x23, __error_p // invalid processor (x23=0)?
|
|
|
|
|
|
|
|
pgtbl x25, x26, x24 // x25=TTBR0, x26=TTBR1
|
|
|
|
ldr x12, [x23, #CPU_INFO_SETUP]
|
|
|
|
add x12, x12, x28 // __virt_to_phys
|
|
|
|
blr x12 // initialise processor
|
|
|
|
|
|
|
|
ldr x21, =secondary_data
|
|
|
|
ldr x27, =__secondary_switched // address to jump to after enabling the MMU
|
|
|
|
b __enable_mmu
|
|
|
|
ENDPROC(secondary_startup)
|
|
|
|
|
|
|
|
ENTRY(__secondary_switched)
|
|
|
|
ldr x0, [x21] // get secondary_data.stack
|
|
|
|
mov sp, x0
|
|
|
|
mov x29, #0
|
|
|
|
b secondary_start_kernel
|
|
|
|
ENDPROC(__secondary_switched)
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Setup common bits before finally enabling the MMU. Essentially this is just
|
|
|
|
* loading the page table pointer and vector base registers.
|
|
|
|
*
|
|
|
|
* On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
|
|
|
|
* the MMU.
|
|
|
|
*/
|
|
|
|
__enable_mmu:
|
|
|
|
ldr x5, =vectors
|
|
|
|
msr vbar_el1, x5
|
|
|
|
msr ttbr0_el1, x25 // load TTBR0
|
|
|
|
msr ttbr1_el1, x26 // load TTBR1
|
|
|
|
isb
|
|
|
|
b __turn_mmu_on
|
|
|
|
ENDPROC(__enable_mmu)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable the MMU. This completely changes the structure of the visible memory
|
|
|
|
* space. You will not be able to trace execution through this.
|
|
|
|
*
|
|
|
|
* x0 = system control register
|
|
|
|
* x27 = *virtual* address to jump to upon completion
|
|
|
|
*
|
|
|
|
* other registers depend on the function called upon completion
|
|
|
|
*/
|
|
|
|
.align 6
|
|
|
|
__turn_mmu_on:
|
|
|
|
msr sctlr_el1, x0
|
|
|
|
isb
|
|
|
|
br x27
|
|
|
|
ENDPROC(__turn_mmu_on)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Calculate the start of physical memory.
|
|
|
|
*/
|
|
|
|
__calc_phys_offset:
|
|
|
|
adr x0, 1f
|
|
|
|
ldp x1, x2, [x0]
|
|
|
|
sub x28, x0, x1 // x28 = PHYS_OFFSET - PAGE_OFFSET
|
|
|
|
add x24, x2, x28 // x24 = PHYS_OFFSET
|
|
|
|
ret
|
|
|
|
ENDPROC(__calc_phys_offset)
|
|
|
|
|
|
|
|
.align 3
|
|
|
|
1: .quad .
|
|
|
|
.quad PAGE_OFFSET
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Macro to populate the PGD for the corresponding block entry in the next
|
|
|
|
* level (tbl) for the given virtual address.
|
|
|
|
*
|
|
|
|
* Preserves: pgd, tbl, virt
|
|
|
|
* Corrupts: tmp1, tmp2
|
|
|
|
*/
|
|
|
|
.macro create_pgd_entry, pgd, tbl, virt, tmp1, tmp2
|
|
|
|
lsr \tmp1, \virt, #PGDIR_SHIFT
|
|
|
|
and \tmp1, \tmp1, #PTRS_PER_PGD - 1 // PGD index
|
|
|
|
orr \tmp2, \tbl, #3 // PGD entry table type
|
|
|
|
str \tmp2, [\pgd, \tmp1, lsl #3]
|
|
|
|
.endm
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Macro to populate block entries in the page table for the start..end
|
|
|
|
* virtual range (inclusive).
|
|
|
|
*
|
|
|
|
* Preserves: tbl, flags
|
|
|
|
* Corrupts: phys, start, end, pstate
|
|
|
|
*/
|
2014-02-17 12:03:25 +00:00
|
|
|
.macro create_block_map, tbl, flags, phys, start, end
|
2012-03-05 11:49:27 +00:00
|
|
|
lsr \phys, \phys, #BLOCK_SHIFT
|
|
|
|
lsr \start, \start, #BLOCK_SHIFT
|
|
|
|
and \start, \start, #PTRS_PER_PTE - 1 // table index
|
|
|
|
orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry
|
|
|
|
lsr \end, \end, #BLOCK_SHIFT
|
|
|
|
and \end, \end, #PTRS_PER_PTE - 1 // table end index
|
|
|
|
9999: str \phys, [\tbl, \start, lsl #3] // store the entry
|
|
|
|
add \start, \start, #1 // next entry
|
|
|
|
add \phys, \phys, #BLOCK_SIZE // next block
|
|
|
|
cmp \start, \end
|
|
|
|
b.ls 9999b
|
|
|
|
.endm
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Setup the initial page tables. We only setup the barest amount which is
|
|
|
|
* required to get the kernel running. The following sections are required:
|
|
|
|
* - identity mapping to enable the MMU (low address, TTBR0)
|
|
|
|
* - first few MB of the kernel linear mapping to jump to once the MMU has
|
|
|
|
* been enabled, including the FDT blob (TTBR1)
|
2014-04-07 22:39:52 +00:00
|
|
|
* - pgd entry for fixed mappings (TTBR1)
|
2012-03-05 11:49:27 +00:00
|
|
|
*/
|
|
|
|
__create_page_tables:
|
|
|
|
pgtbl x25, x26, x24 // idmap_pg_dir and swapper_pg_dir addresses
|
2014-03-26 18:25:55 +00:00
|
|
|
mov x27, lr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Invalidate the idmap and swapper page tables to avoid potential
|
|
|
|
* dirty cache lines being evicted.
|
|
|
|
*/
|
|
|
|
mov x0, x25
|
|
|
|
add x1, x26, #SWAPPER_DIR_SIZE
|
|
|
|
bl __inval_cache_range
|
2012-03-05 11:49:27 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear the idmap and swapper page tables.
|
|
|
|
*/
|
|
|
|
mov x0, x25
|
|
|
|
add x6, x26, #SWAPPER_DIR_SIZE
|
|
|
|
1: stp xzr, xzr, [x0], #16
|
|
|
|
stp xzr, xzr, [x0], #16
|
|
|
|
stp xzr, xzr, [x0], #16
|
|
|
|
stp xzr, xzr, [x0], #16
|
|
|
|
cmp x0, x6
|
|
|
|
b.lo 1b
|
|
|
|
|
|
|
|
ldr x7, =MM_MMUFLAGS
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Create the identity mapping.
|
|
|
|
*/
|
|
|
|
add x0, x25, #PAGE_SIZE // section table address
|
2014-02-17 12:03:25 +00:00
|
|
|
ldr x3, =KERNEL_START
|
|
|
|
add x3, x3, x28 // __pa(KERNEL_START)
|
2012-03-05 11:49:27 +00:00
|
|
|
create_pgd_entry x25, x0, x3, x5, x6
|
2014-02-17 12:03:25 +00:00
|
|
|
ldr x6, =KERNEL_END
|
|
|
|
mov x5, x3 // __pa(KERNEL_START)
|
|
|
|
add x6, x6, x28 // __pa(KERNEL_END)
|
|
|
|
create_block_map x0, x7, x3, x5, x6
|
2012-03-05 11:49:27 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Map the kernel image (starting with PHYS_OFFSET).
|
|
|
|
*/
|
|
|
|
add x0, x26, #PAGE_SIZE // section table address
|
|
|
|
mov x5, #PAGE_OFFSET
|
|
|
|
create_pgd_entry x26, x0, x5, x3, x6
|
2014-02-17 12:03:25 +00:00
|
|
|
ldr x6, =KERNEL_END
|
2012-03-05 11:49:27 +00:00
|
|
|
mov x3, x24 // phys offset
|
|
|
|
create_block_map x0, x7, x3, x5, x6
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Map the FDT blob (maximum 2MB; must be within 512MB of
|
|
|
|
* PHYS_OFFSET).
|
|
|
|
*/
|
|
|
|
mov x3, x21 // FDT phys address
|
|
|
|
and x3, x3, #~((1 << 21) - 1) // 2MB aligned
|
|
|
|
mov x6, #PAGE_OFFSET
|
|
|
|
sub x5, x3, x24 // subtract PHYS_OFFSET
|
|
|
|
tst x5, #~((1 << 29) - 1) // within 512MB?
|
|
|
|
csel x21, xzr, x21, ne // zero the FDT pointer
|
|
|
|
b.ne 1f
|
|
|
|
add x5, x5, x6 // __va(FDT blob)
|
|
|
|
add x6, x5, #1 << 21 // 2MB for the FDT blob
|
|
|
|
sub x6, x6, #1 // inclusive range
|
|
|
|
create_block_map x0, x7, x3, x5, x6
|
|
|
|
1:
|
2012-10-23 13:55:08 +00:00
|
|
|
/*
|
2014-04-07 22:39:52 +00:00
|
|
|
* Create the pgd entry for the fixed mappings.
|
2012-10-23 13:55:08 +00:00
|
|
|
*/
|
2014-04-07 22:39:52 +00:00
|
|
|
ldr x5, =FIXADDR_TOP // Fixed mapping virtual address
|
2012-10-23 13:55:08 +00:00
|
|
|
add x0, x26, #2 * PAGE_SIZE // section table address
|
|
|
|
create_pgd_entry x26, x0, x5, x6, x7
|
2014-03-26 18:25:55 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Since the page tables have been populated with non-cacheable
|
|
|
|
* accesses (MMU disabled), invalidate the idmap and swapper page
|
|
|
|
* tables again to remove any speculatively loaded cache lines.
|
|
|
|
*/
|
|
|
|
mov x0, x25
|
|
|
|
add x1, x26, #SWAPPER_DIR_SIZE
|
|
|
|
bl __inval_cache_range
|
|
|
|
|
|
|
|
mov lr, x27
|
2012-03-05 11:49:27 +00:00
|
|
|
ret
|
|
|
|
ENDPROC(__create_page_tables)
|
|
|
|
.ltorg
|
|
|
|
|
|
|
|
.align 3
|
|
|
|
.type __switch_data, %object
|
|
|
|
__switch_data:
|
|
|
|
.quad __mmap_switched
|
|
|
|
.quad __bss_start // x6
|
|
|
|
.quad _end // x7
|
|
|
|
.quad processor_id // x4
|
|
|
|
.quad __fdt_pointer // x5
|
|
|
|
.quad memstart_addr // x6
|
|
|
|
.quad init_thread_union + THREAD_START_SP // sp
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The following fragment of code is executed with the MMU on in MMU mode, and
|
|
|
|
* uses absolute addresses; this is not position independent.
|
|
|
|
*/
|
|
|
|
__mmap_switched:
|
|
|
|
adr x3, __switch_data + 8
|
|
|
|
|
|
|
|
ldp x6, x7, [x3], #16
|
|
|
|
1: cmp x6, x7
|
|
|
|
b.hs 2f
|
|
|
|
str xzr, [x6], #8 // Clear BSS
|
|
|
|
b 1b
|
|
|
|
2:
|
|
|
|
ldp x4, x5, [x3], #16
|
|
|
|
ldr x6, [x3], #8
|
|
|
|
ldr x16, [x3]
|
|
|
|
mov sp, x16
|
|
|
|
str x22, [x4] // Save processor ID
|
|
|
|
str x21, [x5] // Save FDT pointer
|
|
|
|
str x24, [x6] // Save PHYS_OFFSET
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|
mov x29, #0
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|
|
b start_kernel
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|
|
ENDPROC(__mmap_switched)
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|
|
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|
|
|
/*
|
|
|
|
* Exception handling. Something went wrong and we can't proceed. We ought to
|
|
|
|
* tell the user, but since we don't have any guarantee that we're even
|
|
|
|
* running on the right architecture, we do virtually nothing.
|
|
|
|
*/
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|
|
|
__error_p:
|
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|
ENDPROC(__error_p)
|
|
|
|
|
|
|
|
__error:
|
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|
|
1: nop
|
|
|
|
b 1b
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|
|
|
ENDPROC(__error)
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|
|
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|
|
|
/*
|
|
|
|
* This function gets the processor ID in w0 and searches the cpu_table[] for
|
|
|
|
* a match. It returns a pointer to the struct cpu_info it found. The
|
|
|
|
* cpu_table[] must end with an empty (all zeros) structure.
|
|
|
|
*
|
|
|
|
* This routine can be called via C code and it needs to work with the MMU
|
|
|
|
* both disabled and enabled (the offset is calculated automatically).
|
|
|
|
*/
|
|
|
|
ENTRY(lookup_processor_type)
|
|
|
|
adr x1, __lookup_processor_type_data
|
|
|
|
ldp x2, x3, [x1]
|
|
|
|
sub x1, x1, x2 // get offset between VA and PA
|
|
|
|
add x3, x3, x1 // convert VA to PA
|
|
|
|
1:
|
|
|
|
ldp w5, w6, [x3] // load cpu_id_val and cpu_id_mask
|
|
|
|
cbz w5, 2f // end of list?
|
|
|
|
and w6, w6, w0
|
|
|
|
cmp w5, w6
|
|
|
|
b.eq 3f
|
|
|
|
add x3, x3, #CPU_INFO_SZ
|
|
|
|
b 1b
|
|
|
|
2:
|
|
|
|
mov x3, #0 // unknown processor
|
|
|
|
3:
|
|
|
|
mov x0, x3
|
|
|
|
ret
|
|
|
|
ENDPROC(lookup_processor_type)
|
|
|
|
|
|
|
|
.align 3
|
|
|
|
.type __lookup_processor_type_data, %object
|
|
|
|
__lookup_processor_type_data:
|
|
|
|
.quad .
|
|
|
|
.quad cpu_table
|
|
|
|
.size __lookup_processor_type_data, . - __lookup_processor_type_data
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Determine validity of the x21 FDT pointer.
|
|
|
|
* The dtb must be 8-byte aligned and live in the first 512M of memory.
|
|
|
|
*/
|
|
|
|
__vet_fdt:
|
|
|
|
tst x21, #0x7
|
|
|
|
b.ne 1f
|
|
|
|
cmp x21, x24
|
|
|
|
b.lt 1f
|
|
|
|
mov x0, #(1 << 29)
|
|
|
|
add x0, x0, x24
|
|
|
|
cmp x21, x0
|
|
|
|
b.ge 1f
|
|
|
|
ret
|
|
|
|
1:
|
|
|
|
mov x21, #0
|
|
|
|
ret
|
|
|
|
ENDPROC(__vet_fdt)
|