2019-05-27 06:55:05 +00:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2006-05-21 10:53:06 +00:00
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/*
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* Copyright (C) NEC Electronics Corporation 2004-2006
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*
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* This file is based on the arch/mips/pci/ops-vr41xx.c
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*
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* Copyright 2001 MontaVista Software Inc.
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*/
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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2008-10-23 16:30:20 +00:00
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#include <asm/emma/emma2rh.h>
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2006-05-21 10:53:06 +00:00
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#define RTABORT (0x1<<9)
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#define RMABORT (0x1<<10)
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#define EMMA2RH_PCI_SLOT_NUM 9 /* 0000:09.0 is final PCI device */
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/*
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* access config space
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*/
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static int check_args(struct pci_bus *bus, u32 devfn, u32 * bus_num)
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{
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/* check if the bus is top-level */
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2015-07-13 16:14:21 +00:00
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if (bus->parent != NULL)
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2006-05-21 10:53:06 +00:00
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*bus_num = bus->number;
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2015-07-13 16:14:21 +00:00
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else
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2006-05-21 10:53:06 +00:00
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*bus_num = 0;
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if (*bus_num == 0) {
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/* Type 0 */
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if (PCI_SLOT(devfn) >= 10)
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return PCIBIOS_DEVICE_NOT_FOUND;
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} else {
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/* Type 1 */
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if ((*bus_num >= 64) || (PCI_SLOT(devfn) >= 16))
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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return 0;
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}
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static inline int set_pci_configuration_address(unsigned char bus_num,
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unsigned int devfn, int where)
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{
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u32 config_win0;
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emma2rh_out32(EMMA2RH_PCI_INT, ~RMABORT);
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if (bus_num == 0)
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/*
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* Type 0 configuration
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*/
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config_win0 = (1 << (22 + PCI_SLOT(devfn))) | (5 << 9);
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else
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/*
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* Type 1 configuration
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*/
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config_win0 = (bus_num << 26) | (PCI_SLOT(devfn) << 22) |
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(1 << 15) | (5 << 9);
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emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, config_win0);
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return 0;
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}
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static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t * val)
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{
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u32 bus_num;
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u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE);
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u32 backup_win0;
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u32 data;
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*val = 0xffffffffU;
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if (check_args(bus, devfn, &bus_num) == PCIBIOS_DEVICE_NOT_FOUND)
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return PCIBIOS_DEVICE_NOT_FOUND;
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backup_win0 = emma2rh_in32(EMMA2RH_PCI_IWIN0_CTR);
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if (set_pci_configuration_address(bus_num, devfn, where) < 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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data =
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*(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
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(where & 0xfffffffc));
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switch (size) {
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case 1:
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*val = (data >> ((where & 3) << 3)) & 0xffU;
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break;
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case 2:
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*val = (data >> ((where & 2) << 3)) & 0xffffU;
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break;
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case 4:
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*val = data;
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break;
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default:
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emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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}
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emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
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if (emma2rh_in32(EMMA2RH_PCI_INT) & RMABORT)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 val)
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{
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u32 bus_num;
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u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE);
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u32 backup_win0;
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u32 data;
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int shift;
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if (check_args(bus, devfn, &bus_num) == PCIBIOS_DEVICE_NOT_FOUND)
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return PCIBIOS_DEVICE_NOT_FOUND;
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backup_win0 = emma2rh_in32(EMMA2RH_PCI_IWIN0_CTR);
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if (set_pci_configuration_address(bus_num, devfn, where) < 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* read modify write */
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data =
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*(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
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(where & 0xfffffffc));
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switch (size) {
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case 1:
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shift = (where & 3) << 3;
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data &= ~(0xffU << shift);
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data |= ((val & 0xffU) << shift);
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break;
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case 2:
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shift = (where & 2) << 3;
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data &= ~(0xffffU << shift);
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data |= ((val & 0xffffU) << shift);
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break;
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case 4:
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data = val;
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break;
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default:
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emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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}
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*(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
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(where & 0xfffffffc)) = data;
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emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
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if (emma2rh_in32(EMMA2RH_PCI_INT) & RMABORT)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops emma2rh_pci_ops = {
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.read = pci_config_read,
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.write = pci_config_write,
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};
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