2012-11-23 12:44:39 +00:00
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Atmel SPI device
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Required properties:
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- compatible : should be "atmel,at91rm9200-spi".
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- reg: Address and length of the register set for the device
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- interrupts: Should contain spi interrupt
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spi: atmel: update DT bindings documentation
- add new property "atmel,fifo-size"
- change "cs-gpios" to optional for SPI controller version >= 2.
Please be aware that the VERSION register can not be used to guess the
size of FIFOs. Indeed, for a given hardware version, the SPI controller
can be integrated on Atmel SoCs with different FIFO sizes. Also the
"atmel,fifo-size" property is optional as older SPI controllers don't
embed FIFO at all.
Besides, the FIFO size can not be read or guessed from other registers:
When designing the FIFO feature, no dedicated registers were added to
store this size. Unused spaces in the I/O register range are limited and
better reserved for future usages. Instead, the FIFO size of each
peripheral is documented in the programmer datasheet.
Finally, on a given SoC, there can be several instances of the SPI
controller with different FIFO sizes. This explain why we'd rather use a
dedicated DT property than use the "compatible" property.
For instance, sama5d2x SoCs come with some SPI controllers, the ones
inside Flexcoms, integrating 32 data FIFOs whereas other SPI controllers
use 16 data FIFOs. All these SPI controllers share the same IP version.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 10:09:30 +00:00
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- cs-gpios: chipselects (optional for SPI controller version >= 2 with the
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Chip Select Active After Transfer feature).
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2013-12-17 11:01:34 +00:00
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- clock-names: tuple listing input clock names.
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Required elements: "spi_clk"
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- clocks: phandles to input clocks.
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2012-11-23 12:44:39 +00:00
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spi: atmel: update DT bindings documentation
- add new property "atmel,fifo-size"
- change "cs-gpios" to optional for SPI controller version >= 2.
Please be aware that the VERSION register can not be used to guess the
size of FIFOs. Indeed, for a given hardware version, the SPI controller
can be integrated on Atmel SoCs with different FIFO sizes. Also the
"atmel,fifo-size" property is optional as older SPI controllers don't
embed FIFO at all.
Besides, the FIFO size can not be read or guessed from other registers:
When designing the FIFO feature, no dedicated registers were added to
store this size. Unused spaces in the I/O register range are limited and
better reserved for future usages. Instead, the FIFO size of each
peripheral is documented in the programmer datasheet.
Finally, on a given SoC, there can be several instances of the SPI
controller with different FIFO sizes. This explain why we'd rather use a
dedicated DT property than use the "compatible" property.
For instance, sama5d2x SoCs come with some SPI controllers, the ones
inside Flexcoms, integrating 32 data FIFOs whereas other SPI controllers
use 16 data FIFOs. All these SPI controllers share the same IP version.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 10:09:30 +00:00
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Optional properties:
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- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
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capable SPI controllers.
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2012-11-23 12:44:39 +00:00
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Example:
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spi1: spi@fffcc000 {
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compatible = "atmel,at91rm9200-spi";
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reg = <0xfffcc000 0x4000>;
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interrupts = <13 4 5>;
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#address-cells = <1>;
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#size-cells = <0>;
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2013-12-17 11:01:34 +00:00
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clocks = <&spi1_clk>;
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clock-names = "spi_clk";
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2012-11-23 12:44:39 +00:00
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cs-gpios = <&pioB 3 0>;
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spi: atmel: update DT bindings documentation
- add new property "atmel,fifo-size"
- change "cs-gpios" to optional for SPI controller version >= 2.
Please be aware that the VERSION register can not be used to guess the
size of FIFOs. Indeed, for a given hardware version, the SPI controller
can be integrated on Atmel SoCs with different FIFO sizes. Also the
"atmel,fifo-size" property is optional as older SPI controllers don't
embed FIFO at all.
Besides, the FIFO size can not be read or guessed from other registers:
When designing the FIFO feature, no dedicated registers were added to
store this size. Unused spaces in the I/O register range are limited and
better reserved for future usages. Instead, the FIFO size of each
peripheral is documented in the programmer datasheet.
Finally, on a given SoC, there can be several instances of the SPI
controller with different FIFO sizes. This explain why we'd rather use a
dedicated DT property than use the "compatible" property.
For instance, sama5d2x SoCs come with some SPI controllers, the ones
inside Flexcoms, integrating 32 data FIFOs whereas other SPI controllers
use 16 data FIFOs. All these SPI controllers share the same IP version.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 10:09:30 +00:00
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atmel,fifo-size = <32>;
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2012-11-23 12:44:39 +00:00
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status = "okay";
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mmc-slot@0 {
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compatible = "mmc-spi-slot";
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reg = <0>;
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gpios = <&pioC 4 0>; /* CD */
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spi-max-frequency = <25000000>;
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};
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};
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