2006-01-17 06:14:14 +00:00
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/*
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* arch/sh/kernel/cpu/irq/pint.c - Interrupt handling for PINT-based IRQs.
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/machvec.h>
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2007-04-26 02:51:00 +00:00
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#if defined(CONFIG_CPU_SUBTYPE_SH7705)
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#define INTC_INTER 0xA4000014UL
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#define INTC_IPRD 0xA4000018UL
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#define INTC_ICR2 0xA4000012UL
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/* PFC */
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#define PORT_PACR 0xA4000100UL
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#define PORT_PBCR 0xA4000102UL
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#define PORT_PCCR 0xA4000104UL
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#define PORT_PDCR 0xA4000106UL
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#define PORT_PECR 0xA4000108UL
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#define PORT_PFCR 0xA400010AUL
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#define PORT_PGCR 0xA400010CUL
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#define PORT_PHCR 0xA400010EUL
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#define PORT_PJCR 0xA4000110UL
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#define PORT_PKCR 0xA4000112UL
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#define PORT_PLCR 0xA4000114UL
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#define PORT_PMCR 0xA4000118UL
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#define PORT_PNCR 0xA400011AUL
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#define PORT_PECR2 0xA4050148UL
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#define PORT_PFCR2 0xA405014AUL
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#define PORT_PNCR2 0xA405015AUL
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/* I/O port */
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#define PORT_PADR 0xA4000120UL
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#define PORT_PBDR 0xA4000122UL
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#define PORT_PCDR 0xA4000124UL
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#define PORT_PDDR 0xA4000126UL
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#define PORT_PEDR 0xA4000128UL
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#define PORT_PFDR 0xA400012AUL
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#define PORT_PGDR 0xA400012CUL
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#define PORT_PHDR 0xA400012EUL
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#define PORT_PJDR 0xA4000130UL
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#define PORT_PKDR 0xA4000132UL
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#define PORT_PLDR 0xA4000134UL
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#define PORT_PMDR 0xA4000138UL
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#define PORT_PNDR 0xA400013AUL
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#define PINT0_IRQ 40
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#define PINT8_IRQ 41
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#define PINT_IRQ_BASE 86
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#define PINT0_IPR_ADDR INTC_IPRD
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#define PINT0_IPR_POS 3
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#define PINT0_PRIORITY 2
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#define PINT8_IPR_ADDR INTC_IPRD
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#define PINT8_IPR_POS 2
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#define PINT8_PRIORITY 2
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#endif /* CONFIG_CPU_SUBTYPE_SH7705 */
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2006-01-17 06:14:14 +00:00
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static unsigned char pint_map[256];
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static unsigned long portcr_mask;
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static void enable_pint_irq(unsigned int irq);
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static void disable_pint_irq(unsigned int irq);
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/* shutdown is same as "disable" */
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#define shutdown_pint_irq disable_pint_irq
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static void mask_and_ack_pint(unsigned int);
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static void end_pint_irq(unsigned int irq);
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static unsigned int startup_pint_irq(unsigned int irq)
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{
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enable_pint_irq(irq);
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return 0; /* never anything pending */
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}
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static struct hw_interrupt_type pint_irq_type = {
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.typename = "PINT-IRQ",
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.startup = startup_pint_irq,
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.shutdown = shutdown_pint_irq,
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.enable = enable_pint_irq,
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.disable = disable_pint_irq,
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.ack = mask_and_ack_pint,
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.end = end_pint_irq
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};
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static void disable_pint_irq(unsigned int irq)
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{
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2006-09-27 09:03:34 +00:00
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unsigned long val;
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2006-01-17 06:14:14 +00:00
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val = ctrl_inw(INTC_INTER);
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val &= ~(1 << (irq - PINT_IRQ_BASE));
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ctrl_outw(val, INTC_INTER); /* disable PINTn */
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portcr_mask &= ~(3 << (irq - PINT_IRQ_BASE)*2);
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}
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static void enable_pint_irq(unsigned int irq)
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{
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2006-09-27 09:03:34 +00:00
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unsigned long val;
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2006-01-17 06:14:14 +00:00
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val = ctrl_inw(INTC_INTER);
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val |= 1 << (irq - PINT_IRQ_BASE);
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ctrl_outw(val, INTC_INTER); /* enable PINTn */
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portcr_mask |= 3 << (irq - PINT_IRQ_BASE)*2;
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}
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static void mask_and_ack_pint(unsigned int irq)
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{
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disable_pint_irq(irq);
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}
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static void end_pint_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_pint_irq(irq);
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}
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void make_pint_irq(unsigned int irq)
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{
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disable_irq_nosync(irq);
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[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 09:24:36 +00:00
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irq_desc[irq].chip = &pint_irq_type;
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2006-01-17 06:14:14 +00:00
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disable_pint_irq(irq);
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}
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2006-10-31 03:35:02 +00:00
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static struct ipr_data pint_ipr_map[] = {
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{ PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY },
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{ PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY },
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};
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2006-01-17 06:14:14 +00:00
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void __init init_IRQ_pint(void)
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{
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int i;
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2006-10-31 03:35:02 +00:00
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make_ipr_irq(pint_ipr_map, ARRAY_SIZE(pint_ipr_map));
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2006-01-17 06:14:14 +00:00
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enable_irq(PINT0_IRQ);
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enable_irq(PINT8_IRQ);
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for(i = 0; i < 16; i++)
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make_pint_irq(PINT_IRQ_BASE + i);
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for(i = 0; i < 256; i++) {
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if (i & 1)
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pint_map[i] = 0;
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else if (i & 2)
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pint_map[i] = 1;
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else if (i & 4)
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pint_map[i] = 2;
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else if (i & 8)
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pint_map[i] = 3;
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else if (i & 0x10)
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pint_map[i] = 4;
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else if (i & 0x20)
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pint_map[i] = 5;
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else if (i & 0x40)
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pint_map[i] = 6;
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else if (i & 0x80)
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pint_map[i] = 7;
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}
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}
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int ipr_irq_demux(int irq)
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{
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unsigned long creg, dreg, d, sav;
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if (irq == PINT0_IRQ) {
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2007-04-26 02:51:00 +00:00
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7707)
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2006-01-17 06:14:14 +00:00
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creg = PORT_PACR;
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dreg = PORT_PADR;
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#else
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creg = PORT_PCCR;
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dreg = PORT_PCDR;
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#endif
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sav = ctrl_inw(creg);
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ctrl_outw(sav | portcr_mask, creg);
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d = (~ctrl_inb(dreg) ^ ctrl_inw(INTC_ICR2)) &
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ctrl_inw(INTC_INTER) & 0xff;
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ctrl_outw(sav, creg);
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if (d == 0)
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return irq;
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return PINT_IRQ_BASE + pint_map[d];
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} else if (irq == PINT8_IRQ) {
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2007-04-26 02:51:00 +00:00
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7707)
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2006-01-17 06:14:14 +00:00
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creg = PORT_PBCR;
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dreg = PORT_PBDR;
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#else
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creg = PORT_PFCR;
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dreg = PORT_PFDR;
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#endif
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sav = ctrl_inw(creg);
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ctrl_outw(sav | (portcr_mask >> 16), creg);
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d = (~ctrl_inb(dreg) ^ (ctrl_inw(INTC_ICR2) >> 8)) &
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(ctrl_inw(INTC_INTER) >> 8) & 0xff;
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ctrl_outw(sav, creg);
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if (d == 0)
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return irq;
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return PINT_IRQ_BASE + 8 + pint_map[d];
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}
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return irq;
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}
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