2011-01-07 02:19:31 +00:00
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/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include <linux/firmware.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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2011-08-30 15:04:30 +00:00
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#include <linux/module.h>
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2011-01-07 02:19:31 +00:00
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#include "drmP.h"
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "radeon_drm.h"
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#include "nid.h"
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#include "atom.h"
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#include "ni_reg.h"
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2011-03-03 01:07:31 +00:00
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#include "cayman_blit_shaders.h"
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2011-01-07 02:19:31 +00:00
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2011-03-03 01:07:33 +00:00
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extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
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extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
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extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
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2011-03-03 01:07:34 +00:00
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extern void evergreen_mc_program(struct radeon_device *rdev);
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extern void evergreen_irq_suspend(struct radeon_device *rdev);
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extern int evergreen_mc_init(struct radeon_device *rdev);
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2011-09-01 17:46:15 +00:00
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extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
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2011-09-20 14:22:58 +00:00
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extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
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2012-03-20 21:18:39 +00:00
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extern void si_rlc_fini(struct radeon_device *rdev);
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extern int si_rlc_init(struct radeon_device *rdev);
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2011-03-03 01:07:33 +00:00
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2011-01-07 02:19:31 +00:00
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#define EVERGREEN_PFP_UCODE_SIZE 1120
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#define EVERGREEN_PM4_UCODE_SIZE 1376
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#define EVERGREEN_RLC_UCODE_SIZE 768
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#define BTC_MC_UCODE_SIZE 6024
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2011-03-03 01:07:28 +00:00
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#define CAYMAN_PFP_UCODE_SIZE 2176
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#define CAYMAN_PM4_UCODE_SIZE 2176
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#define CAYMAN_RLC_UCODE_SIZE 1024
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#define CAYMAN_MC_UCODE_SIZE 6037
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2012-03-20 21:18:39 +00:00
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#define ARUBA_RLC_UCODE_SIZE 1536
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2011-01-07 02:19:31 +00:00
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/* Firmware Names */
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MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
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MODULE_FIRMWARE("radeon/BARTS_me.bin");
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MODULE_FIRMWARE("radeon/BARTS_mc.bin");
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MODULE_FIRMWARE("radeon/BTC_rlc.bin");
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MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
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MODULE_FIRMWARE("radeon/TURKS_me.bin");
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MODULE_FIRMWARE("radeon/TURKS_mc.bin");
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MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
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MODULE_FIRMWARE("radeon/CAICOS_me.bin");
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MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
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2011-03-03 01:07:28 +00:00
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MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
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MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
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MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
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MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
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2012-03-20 21:18:39 +00:00
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MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
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MODULE_FIRMWARE("radeon/ARUBA_me.bin");
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MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
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2011-01-07 02:19:31 +00:00
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#define BTC_IO_MC_REGS_SIZE 29
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static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
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{0x00000077, 0xff010100},
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{0x00000078, 0x00000000},
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{0x00000079, 0x00001434},
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{0x0000007a, 0xcc08ec08},
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{0x0000007b, 0x00040000},
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{0x0000007c, 0x000080c0},
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{0x0000007d, 0x09000000},
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{0x0000007e, 0x00210404},
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{0x00000081, 0x08a8e800},
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{0x00000082, 0x00030444},
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{0x00000083, 0x00000000},
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{0x00000085, 0x00000001},
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{0x00000086, 0x00000002},
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{0x00000087, 0x48490000},
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{0x00000088, 0x20244647},
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{0x00000089, 0x00000005},
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{0x0000008b, 0x66030000},
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{0x0000008c, 0x00006603},
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{0x0000008d, 0x00000100},
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{0x0000008f, 0x00001c0a},
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{0x00000090, 0xff000001},
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{0x00000094, 0x00101101},
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{0x00000095, 0x00000fff},
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{0x00000096, 0x00116fff},
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{0x00000097, 0x60010000},
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{0x00000098, 0x10010000},
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{0x00000099, 0x00006000},
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{0x0000009a, 0x00001000},
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{0x0000009f, 0x00946a00}
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};
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static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
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{0x00000077, 0xff010100},
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{0x00000078, 0x00000000},
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{0x00000079, 0x00001434},
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{0x0000007a, 0xcc08ec08},
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{0x0000007b, 0x00040000},
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{0x0000007c, 0x000080c0},
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{0x0000007d, 0x09000000},
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{0x0000007e, 0x00210404},
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{0x00000081, 0x08a8e800},
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{0x00000082, 0x00030444},
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{0x00000083, 0x00000000},
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{0x00000085, 0x00000001},
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{0x00000086, 0x00000002},
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{0x00000087, 0x48490000},
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{0x00000088, 0x20244647},
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{0x00000089, 0x00000005},
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{0x0000008b, 0x66030000},
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{0x0000008c, 0x00006603},
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{0x0000008d, 0x00000100},
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{0x0000008f, 0x00001c0a},
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{0x00000090, 0xff000001},
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{0x00000094, 0x00101101},
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{0x00000095, 0x00000fff},
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{0x00000096, 0x00116fff},
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{0x00000097, 0x60010000},
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{0x00000098, 0x10010000},
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{0x00000099, 0x00006000},
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{0x0000009a, 0x00001000},
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{0x0000009f, 0x00936a00}
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};
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static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
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{0x00000077, 0xff010100},
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{0x00000078, 0x00000000},
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{0x00000079, 0x00001434},
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{0x0000007a, 0xcc08ec08},
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{0x0000007b, 0x00040000},
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{0x0000007c, 0x000080c0},
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{0x0000007d, 0x09000000},
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{0x0000007e, 0x00210404},
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{0x00000081, 0x08a8e800},
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{0x00000082, 0x00030444},
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{0x00000083, 0x00000000},
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{0x00000085, 0x00000001},
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{0x00000086, 0x00000002},
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{0x00000087, 0x48490000},
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{0x00000088, 0x20244647},
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{0x00000089, 0x00000005},
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{0x0000008b, 0x66030000},
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{0x0000008c, 0x00006603},
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{0x0000008d, 0x00000100},
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{0x0000008f, 0x00001c0a},
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{0x00000090, 0xff000001},
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{0x00000094, 0x00101101},
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{0x00000095, 0x00000fff},
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{0x00000096, 0x00116fff},
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{0x00000097, 0x60010000},
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{0x00000098, 0x10010000},
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{0x00000099, 0x00006000},
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{0x0000009a, 0x00001000},
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{0x0000009f, 0x00916a00}
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};
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2011-03-03 01:07:28 +00:00
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static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
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{0x00000077, 0xff010100},
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{0x00000078, 0x00000000},
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{0x00000079, 0x00001434},
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{0x0000007a, 0xcc08ec08},
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{0x0000007b, 0x00040000},
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{0x0000007c, 0x000080c0},
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{0x0000007d, 0x09000000},
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{0x0000007e, 0x00210404},
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{0x00000081, 0x08a8e800},
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{0x00000082, 0x00030444},
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{0x00000083, 0x00000000},
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{0x00000085, 0x00000001},
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{0x00000086, 0x00000002},
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{0x00000087, 0x48490000},
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{0x00000088, 0x20244647},
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{0x00000089, 0x00000005},
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{0x0000008b, 0x66030000},
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{0x0000008c, 0x00006603},
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{0x0000008d, 0x00000100},
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{0x0000008f, 0x00001c0a},
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{0x00000090, 0xff000001},
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{0x00000094, 0x00101101},
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{0x00000095, 0x00000fff},
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{0x00000096, 0x00116fff},
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{0x00000097, 0x60010000},
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{0x00000098, 0x10010000},
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{0x00000099, 0x00006000},
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{0x0000009a, 0x00001000},
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{0x0000009f, 0x00976b00}
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};
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2011-03-03 01:07:34 +00:00
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int ni_mc_load_microcode(struct radeon_device *rdev)
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2011-01-07 02:19:31 +00:00
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{
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const __be32 *fw_data;
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u32 mem_type, running, blackout = 0;
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u32 *io_mc_regs;
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2011-03-03 01:07:28 +00:00
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int i, ucode_size, regs_size;
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2011-01-07 02:19:31 +00:00
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if (!rdev->mc_fw)
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return -EINVAL;
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switch (rdev->family) {
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case CHIP_BARTS:
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io_mc_regs = (u32 *)&barts_io_mc_regs;
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2011-03-03 01:07:28 +00:00
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ucode_size = BTC_MC_UCODE_SIZE;
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regs_size = BTC_IO_MC_REGS_SIZE;
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2011-01-07 02:19:31 +00:00
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break;
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case CHIP_TURKS:
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io_mc_regs = (u32 *)&turks_io_mc_regs;
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2011-03-03 01:07:28 +00:00
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ucode_size = BTC_MC_UCODE_SIZE;
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regs_size = BTC_IO_MC_REGS_SIZE;
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2011-01-07 02:19:31 +00:00
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break;
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case CHIP_CAICOS:
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default:
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io_mc_regs = (u32 *)&caicos_io_mc_regs;
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2011-03-03 01:07:28 +00:00
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ucode_size = BTC_MC_UCODE_SIZE;
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regs_size = BTC_IO_MC_REGS_SIZE;
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break;
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case CHIP_CAYMAN:
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io_mc_regs = (u32 *)&cayman_io_mc_regs;
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ucode_size = CAYMAN_MC_UCODE_SIZE;
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regs_size = BTC_IO_MC_REGS_SIZE;
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2011-01-07 02:19:31 +00:00
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break;
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}
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mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
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running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
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if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
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if (running) {
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blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
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WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
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}
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/* reset the engine and set to writable */
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WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
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WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
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/* load mc io regs */
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2011-03-03 01:07:28 +00:00
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for (i = 0; i < regs_size; i++) {
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2011-01-07 02:19:31 +00:00
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WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
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WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
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}
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/* load the MC ucode */
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fw_data = (const __be32 *)rdev->mc_fw->data;
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2011-03-03 01:07:28 +00:00
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for (i = 0; i < ucode_size; i++)
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2011-01-07 02:19:31 +00:00
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WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
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/* put the engine back into the active state */
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WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
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WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
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WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
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/* wait for training to complete */
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2011-11-02 22:08:25 +00:00
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for (i = 0; i < rdev->usec_timeout; i++) {
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if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
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break;
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udelay(1);
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}
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2011-01-07 02:19:31 +00:00
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if (running)
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WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
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}
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return 0;
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}
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int ni_init_microcode(struct radeon_device *rdev)
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{
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struct platform_device *pdev;
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const char *chip_name;
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const char *rlc_chip_name;
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size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
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char fw_name[30];
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int err;
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DRM_DEBUG("\n");
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pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
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err = IS_ERR(pdev);
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if (err) {
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|
|
printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (rdev->family) {
|
|
|
|
case CHIP_BARTS:
|
|
|
|
chip_name = "BARTS";
|
|
|
|
rlc_chip_name = "BTC";
|
2011-03-03 01:07:28 +00:00
|
|
|
pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
|
|
|
|
me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
|
|
|
|
rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
|
|
|
|
mc_req_size = BTC_MC_UCODE_SIZE * 4;
|
2011-01-07 02:19:31 +00:00
|
|
|
break;
|
|
|
|
case CHIP_TURKS:
|
|
|
|
chip_name = "TURKS";
|
|
|
|
rlc_chip_name = "BTC";
|
2011-03-03 01:07:28 +00:00
|
|
|
pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
|
|
|
|
me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
|
|
|
|
rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
|
|
|
|
mc_req_size = BTC_MC_UCODE_SIZE * 4;
|
2011-01-07 02:19:31 +00:00
|
|
|
break;
|
|
|
|
case CHIP_CAICOS:
|
|
|
|
chip_name = "CAICOS";
|
|
|
|
rlc_chip_name = "BTC";
|
2011-03-03 01:07:28 +00:00
|
|
|
pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
|
|
|
|
me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
|
|
|
|
rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
|
|
|
|
mc_req_size = BTC_MC_UCODE_SIZE * 4;
|
|
|
|
break;
|
|
|
|
case CHIP_CAYMAN:
|
|
|
|
chip_name = "CAYMAN";
|
|
|
|
rlc_chip_name = "CAYMAN";
|
|
|
|
pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
|
|
|
|
me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
|
|
|
|
rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
|
|
|
|
mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
|
2011-01-07 02:19:31 +00:00
|
|
|
break;
|
2012-03-20 21:18:39 +00:00
|
|
|
case CHIP_ARUBA:
|
|
|
|
chip_name = "ARUBA";
|
|
|
|
rlc_chip_name = "ARUBA";
|
|
|
|
/* pfp/me same size as CAYMAN */
|
|
|
|
pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
|
|
|
|
me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
|
|
|
|
rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
|
|
|
|
mc_req_size = 0;
|
|
|
|
break;
|
2011-01-07 02:19:31 +00:00
|
|
|
default: BUG();
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_INFO("Loading %s Microcode\n", chip_name);
|
|
|
|
|
|
|
|
snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
|
|
|
|
err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
|
|
|
if (rdev->pfp_fw->size != pfp_req_size) {
|
|
|
|
printk(KERN_ERR
|
|
|
|
"ni_cp: Bogus length %zu in firmware \"%s\"\n",
|
|
|
|
rdev->pfp_fw->size, fw_name);
|
|
|
|
err = -EINVAL;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
|
|
|
|
err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
|
|
|
if (rdev->me_fw->size != me_req_size) {
|
|
|
|
printk(KERN_ERR
|
|
|
|
"ni_cp: Bogus length %zu in firmware \"%s\"\n",
|
|
|
|
rdev->me_fw->size, fw_name);
|
|
|
|
err = -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
|
|
|
|
err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
|
|
|
if (rdev->rlc_fw->size != rlc_req_size) {
|
|
|
|
printk(KERN_ERR
|
|
|
|
"ni_rlc: Bogus length %zu in firmware \"%s\"\n",
|
|
|
|
rdev->rlc_fw->size, fw_name);
|
|
|
|
err = -EINVAL;
|
|
|
|
}
|
|
|
|
|
2012-03-20 21:18:39 +00:00
|
|
|
/* no MC ucode on TN */
|
|
|
|
if (!(rdev->flags & RADEON_IS_IGP)) {
|
|
|
|
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
|
|
|
|
err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
|
|
|
if (rdev->mc_fw->size != mc_req_size) {
|
|
|
|
printk(KERN_ERR
|
|
|
|
"ni_mc: Bogus length %zu in firmware \"%s\"\n",
|
|
|
|
rdev->mc_fw->size, fw_name);
|
|
|
|
err = -EINVAL;
|
|
|
|
}
|
2011-01-07 02:19:31 +00:00
|
|
|
}
|
|
|
|
out:
|
|
|
|
platform_device_unregister(pdev);
|
|
|
|
|
|
|
|
if (err) {
|
|
|
|
if (err != -EINVAL)
|
|
|
|
printk(KERN_ERR
|
|
|
|
"ni_cp: Failed to load firmware \"%s\"\n",
|
|
|
|
fw_name);
|
|
|
|
release_firmware(rdev->pfp_fw);
|
|
|
|
rdev->pfp_fw = NULL;
|
|
|
|
release_firmware(rdev->me_fw);
|
|
|
|
rdev->me_fw = NULL;
|
|
|
|
release_firmware(rdev->rlc_fw);
|
|
|
|
rdev->rlc_fw = NULL;
|
|
|
|
release_firmware(rdev->mc_fw);
|
|
|
|
rdev->mc_fw = NULL;
|
|
|
|
}
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2011-03-03 01:07:29 +00:00
|
|
|
/*
|
|
|
|
* Core functions
|
|
|
|
*/
|
|
|
|
static void cayman_gpu_init(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
u32 gb_addr_config = 0;
|
|
|
|
u32 mc_shared_chmap, mc_arb_ramcfg;
|
|
|
|
u32 cgts_tcc_disable;
|
|
|
|
u32 sx_debug_1;
|
|
|
|
u32 smx_dc_ctl0;
|
|
|
|
u32 cgts_sm_ctrl_reg;
|
|
|
|
u32 hdp_host_path_cntl;
|
|
|
|
u32 tmp;
|
2012-05-31 23:00:25 +00:00
|
|
|
u32 disabled_rb_mask;
|
2011-03-03 01:07:29 +00:00
|
|
|
int i, j;
|
|
|
|
|
|
|
|
switch (rdev->family) {
|
|
|
|
case CHIP_CAYMAN:
|
|
|
|
rdev->config.cayman.max_shader_engines = 2;
|
|
|
|
rdev->config.cayman.max_pipes_per_simd = 4;
|
|
|
|
rdev->config.cayman.max_tile_pipes = 8;
|
|
|
|
rdev->config.cayman.max_simds_per_se = 12;
|
|
|
|
rdev->config.cayman.max_backends_per_se = 4;
|
|
|
|
rdev->config.cayman.max_texture_channel_caches = 8;
|
|
|
|
rdev->config.cayman.max_gprs = 256;
|
|
|
|
rdev->config.cayman.max_threads = 256;
|
|
|
|
rdev->config.cayman.max_gs_threads = 32;
|
|
|
|
rdev->config.cayman.max_stack_entries = 512;
|
|
|
|
rdev->config.cayman.sx_num_of_sets = 8;
|
|
|
|
rdev->config.cayman.sx_max_export_size = 256;
|
|
|
|
rdev->config.cayman.sx_max_export_pos_size = 64;
|
|
|
|
rdev->config.cayman.sx_max_export_smx_size = 192;
|
|
|
|
rdev->config.cayman.max_hw_contexts = 8;
|
|
|
|
rdev->config.cayman.sq_num_cf_insts = 2;
|
|
|
|
|
|
|
|
rdev->config.cayman.sc_prim_fifo_size = 0x100;
|
|
|
|
rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
|
|
|
|
rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
|
2012-05-31 23:00:25 +00:00
|
|
|
gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
|
2011-03-03 01:07:29 +00:00
|
|
|
break;
|
2012-03-20 21:18:36 +00:00
|
|
|
case CHIP_ARUBA:
|
|
|
|
default:
|
|
|
|
rdev->config.cayman.max_shader_engines = 1;
|
|
|
|
rdev->config.cayman.max_pipes_per_simd = 4;
|
|
|
|
rdev->config.cayman.max_tile_pipes = 2;
|
|
|
|
if ((rdev->pdev->device == 0x9900) ||
|
2012-06-05 13:50:28 +00:00
|
|
|
(rdev->pdev->device == 0x9901) ||
|
|
|
|
(rdev->pdev->device == 0x9905) ||
|
|
|
|
(rdev->pdev->device == 0x9906) ||
|
|
|
|
(rdev->pdev->device == 0x9907) ||
|
|
|
|
(rdev->pdev->device == 0x9908) ||
|
|
|
|
(rdev->pdev->device == 0x9909) ||
|
|
|
|
(rdev->pdev->device == 0x9910) ||
|
|
|
|
(rdev->pdev->device == 0x9917)) {
|
2012-03-20 21:18:36 +00:00
|
|
|
rdev->config.cayman.max_simds_per_se = 6;
|
|
|
|
rdev->config.cayman.max_backends_per_se = 2;
|
|
|
|
} else if ((rdev->pdev->device == 0x9903) ||
|
2012-06-05 13:50:28 +00:00
|
|
|
(rdev->pdev->device == 0x9904) ||
|
|
|
|
(rdev->pdev->device == 0x990A) ||
|
|
|
|
(rdev->pdev->device == 0x9913) ||
|
|
|
|
(rdev->pdev->device == 0x9918)) {
|
2012-03-20 21:18:36 +00:00
|
|
|
rdev->config.cayman.max_simds_per_se = 4;
|
|
|
|
rdev->config.cayman.max_backends_per_se = 2;
|
2012-06-05 13:50:28 +00:00
|
|
|
} else if ((rdev->pdev->device == 0x9919) ||
|
|
|
|
(rdev->pdev->device == 0x9990) ||
|
|
|
|
(rdev->pdev->device == 0x9991) ||
|
|
|
|
(rdev->pdev->device == 0x9994) ||
|
|
|
|
(rdev->pdev->device == 0x99A0)) {
|
2012-03-20 21:18:36 +00:00
|
|
|
rdev->config.cayman.max_simds_per_se = 3;
|
|
|
|
rdev->config.cayman.max_backends_per_se = 1;
|
|
|
|
} else {
|
|
|
|
rdev->config.cayman.max_simds_per_se = 2;
|
|
|
|
rdev->config.cayman.max_backends_per_se = 1;
|
|
|
|
}
|
|
|
|
rdev->config.cayman.max_texture_channel_caches = 2;
|
|
|
|
rdev->config.cayman.max_gprs = 256;
|
|
|
|
rdev->config.cayman.max_threads = 256;
|
|
|
|
rdev->config.cayman.max_gs_threads = 32;
|
|
|
|
rdev->config.cayman.max_stack_entries = 512;
|
|
|
|
rdev->config.cayman.sx_num_of_sets = 8;
|
|
|
|
rdev->config.cayman.sx_max_export_size = 256;
|
|
|
|
rdev->config.cayman.sx_max_export_pos_size = 64;
|
|
|
|
rdev->config.cayman.sx_max_export_smx_size = 192;
|
|
|
|
rdev->config.cayman.max_hw_contexts = 8;
|
|
|
|
rdev->config.cayman.sq_num_cf_insts = 2;
|
|
|
|
|
|
|
|
rdev->config.cayman.sc_prim_fifo_size = 0x40;
|
|
|
|
rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
|
|
|
|
rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
|
2012-05-31 23:00:25 +00:00
|
|
|
gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
|
2012-03-20 21:18:36 +00:00
|
|
|
break;
|
2011-03-03 01:07:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize HDP */
|
|
|
|
for (i = 0, j = 0; i < 32; i++, j += 0x18) {
|
|
|
|
WREG32((0x2c14 + j), 0x00000000);
|
|
|
|
WREG32((0x2c18 + j), 0x00000000);
|
|
|
|
WREG32((0x2c1c + j), 0x00000000);
|
|
|
|
WREG32((0x2c20 + j), 0x00000000);
|
|
|
|
WREG32((0x2c24 + j), 0x00000000);
|
|
|
|
}
|
|
|
|
|
|
|
|
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
|
|
|
|
|
2011-09-01 17:46:15 +00:00
|
|
|
evergreen_fix_pci_max_read_req_size(rdev);
|
|
|
|
|
2011-03-03 01:07:29 +00:00
|
|
|
mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
|
|
|
|
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
|
|
|
|
|
|
|
|
tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
|
|
|
|
rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
|
|
|
|
if (rdev->config.cayman.mem_row_size_in_kb > 4)
|
|
|
|
rdev->config.cayman.mem_row_size_in_kb = 4;
|
|
|
|
/* XXX use MC settings? */
|
|
|
|
rdev->config.cayman.shader_engine_tile_size = 32;
|
|
|
|
rdev->config.cayman.num_gpus = 1;
|
|
|
|
rdev->config.cayman.multi_gpu_tile_size = 64;
|
|
|
|
|
|
|
|
tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
|
|
|
|
rdev->config.cayman.num_tile_pipes = (1 << tmp);
|
|
|
|
tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
|
|
|
|
rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
|
|
|
|
tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
|
|
|
|
rdev->config.cayman.num_shader_engines = tmp + 1;
|
|
|
|
tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
|
|
|
|
rdev->config.cayman.num_gpus = tmp + 1;
|
|
|
|
tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
|
|
|
|
rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
|
|
|
|
tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
|
|
|
|
rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
|
|
|
|
|
2012-05-31 23:00:25 +00:00
|
|
|
|
2011-03-03 01:07:29 +00:00
|
|
|
/* setup tiling info dword. gb_addr_config is not adequate since it does
|
|
|
|
* not have bank info, so create a custom tiling dword.
|
|
|
|
* bits 3:0 num_pipes
|
|
|
|
* bits 7:4 num_banks
|
|
|
|
* bits 11:8 group_size
|
|
|
|
* bits 15:12 row_size
|
|
|
|
*/
|
|
|
|
rdev->config.cayman.tile_config = 0;
|
|
|
|
switch (rdev->config.cayman.num_tile_pipes) {
|
|
|
|
case 1:
|
|
|
|
default:
|
|
|
|
rdev->config.cayman.tile_config |= (0 << 0);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
rdev->config.cayman.tile_config |= (1 << 0);
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
rdev->config.cayman.tile_config |= (2 << 0);
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
rdev->config.cayman.tile_config |= (3 << 0);
|
|
|
|
break;
|
|
|
|
}
|
2012-03-20 21:18:36 +00:00
|
|
|
|
|
|
|
/* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
|
|
|
|
if (rdev->flags & RADEON_IS_IGP)
|
2012-05-25 02:55:15 +00:00
|
|
|
rdev->config.cayman.tile_config |= 1 << 4;
|
2012-05-31 22:53:36 +00:00
|
|
|
else {
|
|
|
|
if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
|
|
|
|
rdev->config.cayman.tile_config |= 1 << 4;
|
|
|
|
else
|
|
|
|
rdev->config.cayman.tile_config |= 0 << 4;
|
|
|
|
}
|
2011-03-03 01:07:29 +00:00
|
|
|
rdev->config.cayman.tile_config |=
|
2011-05-19 04:14:41 +00:00
|
|
|
((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
|
2011-03-03 01:07:29 +00:00
|
|
|
rdev->config.cayman.tile_config |=
|
|
|
|
((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
|
|
|
|
|
2012-05-31 23:00:25 +00:00
|
|
|
tmp = 0;
|
|
|
|
for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
|
|
|
|
u32 rb_disable_bitmap;
|
|
|
|
|
|
|
|
WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
|
|
|
|
WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
|
|
|
|
rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
|
|
|
|
tmp <<= 4;
|
|
|
|
tmp |= rb_disable_bitmap;
|
|
|
|
}
|
|
|
|
/* enabled rb are just the one not disabled :) */
|
|
|
|
disabled_rb_mask = tmp;
|
|
|
|
|
|
|
|
WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
|
|
|
|
WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
|
|
|
|
|
2011-03-03 01:07:29 +00:00
|
|
|
WREG32(GB_ADDR_CONFIG, gb_addr_config);
|
|
|
|
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
|
|
|
|
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
|
|
|
|
|
2012-05-31 23:00:25 +00:00
|
|
|
tmp = gb_addr_config & NUM_PIPES_MASK;
|
|
|
|
tmp = r6xx_remap_render_backend(rdev, tmp,
|
|
|
|
rdev->config.cayman.max_backends_per_se *
|
|
|
|
rdev->config.cayman.max_shader_engines,
|
|
|
|
CAYMAN_MAX_BACKENDS, disabled_rb_mask);
|
|
|
|
WREG32(GB_BACKEND_MAP, tmp);
|
2011-03-03 01:07:29 +00:00
|
|
|
|
2012-05-31 23:00:25 +00:00
|
|
|
cgts_tcc_disable = 0xffff0000;
|
|
|
|
for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
|
|
|
|
cgts_tcc_disable &= ~(1 << (16 + i));
|
2011-03-03 01:07:29 +00:00
|
|
|
WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
|
|
|
|
WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
|
|
|
|
WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
|
|
|
|
WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
|
|
|
|
|
|
|
|
/* reprogram the shader complex */
|
|
|
|
cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
|
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
|
|
|
|
WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
|
|
|
|
|
|
|
|
/* set HW defaults for 3D engine */
|
|
|
|
WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
|
|
|
|
|
|
|
|
sx_debug_1 = RREG32(SX_DEBUG_1);
|
|
|
|
sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
|
|
|
|
WREG32(SX_DEBUG_1, sx_debug_1);
|
|
|
|
|
|
|
|
smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
|
|
|
|
smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
|
2011-05-09 04:54:33 +00:00
|
|
|
smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
|
2011-03-03 01:07:29 +00:00
|
|
|
WREG32(SMX_DC_CTL0, smx_dc_ctl0);
|
|
|
|
|
|
|
|
WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
|
|
|
|
|
|
|
|
/* need to be explicitly zero-ed */
|
|
|
|
WREG32(VGT_OFFCHIP_LDS_BASE, 0);
|
|
|
|
WREG32(SQ_LSTMP_RING_BASE, 0);
|
|
|
|
WREG32(SQ_HSTMP_RING_BASE, 0);
|
|
|
|
WREG32(SQ_ESTMP_RING_BASE, 0);
|
|
|
|
WREG32(SQ_GSTMP_RING_BASE, 0);
|
|
|
|
WREG32(SQ_VSTMP_RING_BASE, 0);
|
|
|
|
WREG32(SQ_PSTMP_RING_BASE, 0);
|
|
|
|
|
|
|
|
WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
|
|
|
|
|
2011-05-09 04:54:33 +00:00
|
|
|
WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
|
|
|
|
POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
|
|
|
|
SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
|
2011-03-03 01:07:29 +00:00
|
|
|
|
2011-05-09 04:54:33 +00:00
|
|
|
WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
|
|
|
|
SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
|
|
|
|
SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
|
2011-03-03 01:07:29 +00:00
|
|
|
|
|
|
|
|
|
|
|
WREG32(VGT_NUM_INSTANCES, 1);
|
|
|
|
|
|
|
|
WREG32(CP_PERFMON_CNTL, 0);
|
|
|
|
|
2011-05-09 04:54:33 +00:00
|
|
|
WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
|
2011-03-03 01:07:29 +00:00
|
|
|
FETCH_FIFO_HIWATER(0x4) |
|
|
|
|
DONE_FIFO_HIWATER(0xe0) |
|
|
|
|
ALU_UPDATE_FIFO_HIWATER(0x8)));
|
|
|
|
|
|
|
|
WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
|
|
|
|
WREG32(SQ_CONFIG, (VC_ENABLE |
|
|
|
|
EXPORT_SRC_C |
|
|
|
|
GFX_PRIO(0) |
|
|
|
|
CS1_PRIO(0) |
|
|
|
|
CS2_PRIO(1)));
|
|
|
|
WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
|
|
|
|
|
|
|
|
WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
|
|
|
|
FORCE_EOV_MAX_REZ_CNT(255)));
|
|
|
|
|
|
|
|
WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
|
|
|
|
AUTO_INVLD_EN(ES_AND_GS_AUTO));
|
|
|
|
|
|
|
|
WREG32(VGT_GS_VERTEX_REUSE, 16);
|
|
|
|
WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
|
|
|
|
|
|
|
|
WREG32(CB_PERF_CTR0_SEL_0, 0);
|
|
|
|
WREG32(CB_PERF_CTR0_SEL_1, 0);
|
|
|
|
WREG32(CB_PERF_CTR1_SEL_0, 0);
|
|
|
|
WREG32(CB_PERF_CTR1_SEL_1, 0);
|
|
|
|
WREG32(CB_PERF_CTR2_SEL_0, 0);
|
|
|
|
WREG32(CB_PERF_CTR2_SEL_1, 0);
|
|
|
|
WREG32(CB_PERF_CTR3_SEL_0, 0);
|
|
|
|
WREG32(CB_PERF_CTR3_SEL_1, 0);
|
|
|
|
|
2011-05-19 04:14:42 +00:00
|
|
|
tmp = RREG32(HDP_MISC_CNTL);
|
|
|
|
tmp |= HDP_FLUSH_INVALIDATE_CACHE;
|
|
|
|
WREG32(HDP_MISC_CNTL, tmp);
|
|
|
|
|
2011-03-03 01:07:29 +00:00
|
|
|
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
|
|
|
|
WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
|
|
|
|
|
|
|
|
WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
|
|
|
|
|
|
|
|
udelay(50);
|
|
|
|
}
|
|
|
|
|
2011-03-03 01:07:30 +00:00
|
|
|
/*
|
|
|
|
* GART
|
|
|
|
*/
|
|
|
|
void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
/* flush hdp cache */
|
|
|
|
WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
|
|
|
|
|
|
|
|
/* bits 0-7 are the VM contexts0-7 */
|
|
|
|
WREG32(VM_INVALIDATE_REQUEST, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
int cayman_pcie_gart_enable(struct radeon_device *rdev)
|
|
|
|
{
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
int i, r;
|
2011-03-03 01:07:30 +00:00
|
|
|
|
2011-11-03 15:16:49 +00:00
|
|
|
if (rdev->gart.robj == NULL) {
|
2011-03-03 01:07:30 +00:00
|
|
|
dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
r = radeon_gart_table_vram_pin(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
radeon_gart_restore(rdev);
|
|
|
|
/* Setup TLB control */
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
WREG32(MC_VM_MX_L1_TLB_CNTL,
|
|
|
|
(0xA << 7) |
|
|
|
|
ENABLE_L1_TLB |
|
2011-03-03 01:07:30 +00:00
|
|
|
ENABLE_L1_FRAGMENT_PROCESSING |
|
|
|
|
SYSTEM_ACCESS_MODE_NOT_IN_SYS |
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
ENABLE_ADVANCED_DRIVER_MODEL |
|
2011-03-03 01:07:30 +00:00
|
|
|
SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
|
|
|
|
/* Setup L2 cache */
|
|
|
|
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
|
|
|
|
ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
|
|
|
|
ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
|
|
|
|
EFFECTIVE_L2_QUEUE_SIZE(7) |
|
|
|
|
CONTEXT1_IDENTITY_ACCESS_MODE(1));
|
|
|
|
WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
|
|
|
|
WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
|
|
|
|
L2_CACHE_BIGK_FRAGMENT_SIZE(6));
|
|
|
|
/* setup context0 */
|
|
|
|
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
|
|
|
|
WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
|
|
|
|
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
|
|
|
|
WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
|
|
|
|
(u32)(rdev->dummy_page.addr >> 12));
|
|
|
|
WREG32(VM_CONTEXT0_CNTL2, 0);
|
|
|
|
WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
|
|
|
|
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
|
|
|
|
WREG32(0x15D4, 0);
|
|
|
|
WREG32(0x15D8, 0);
|
|
|
|
WREG32(0x15DC, 0);
|
|
|
|
|
|
|
|
/* empty context1-7 */
|
|
|
|
for (i = 1; i < 8; i++) {
|
|
|
|
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
|
|
|
|
WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0);
|
|
|
|
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
|
|
|
|
rdev->gart.table_addr >> 12);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* enable context1-7 */
|
|
|
|
WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
|
|
|
|
(u32)(rdev->dummy_page.addr >> 12));
|
2011-03-03 01:07:30 +00:00
|
|
|
WREG32(VM_CONTEXT1_CNTL2, 0);
|
|
|
|
WREG32(VM_CONTEXT1_CNTL, 0);
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
|
|
|
|
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
|
2011-03-03 01:07:30 +00:00
|
|
|
|
|
|
|
cayman_pcie_gart_tlb_flush(rdev);
|
2011-08-31 21:54:07 +00:00
|
|
|
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
|
|
|
|
(unsigned)(rdev->mc.gtt_size >> 20),
|
|
|
|
(unsigned long long)rdev->gart.table_addr);
|
2011-03-03 01:07:30 +00:00
|
|
|
rdev->gart.ready = true;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void cayman_pcie_gart_disable(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
/* Disable all tables */
|
|
|
|
WREG32(VM_CONTEXT0_CNTL, 0);
|
|
|
|
WREG32(VM_CONTEXT1_CNTL, 0);
|
|
|
|
/* Setup TLB control */
|
|
|
|
WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
|
|
|
|
SYSTEM_ACCESS_MODE_NOT_IN_SYS |
|
|
|
|
SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
|
|
|
|
/* Setup L2 cache */
|
|
|
|
WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
|
|
|
|
ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
|
|
|
|
EFFECTIVE_L2_QUEUE_SIZE(7) |
|
|
|
|
CONTEXT1_IDENTITY_ACCESS_MODE(1));
|
|
|
|
WREG32(VM_L2_CNTL2, 0);
|
|
|
|
WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
|
|
|
|
L2_CACHE_BIGK_FRAGMENT_SIZE(6));
|
2011-11-03 15:16:49 +00:00
|
|
|
radeon_gart_table_vram_unpin(rdev);
|
2011-03-03 01:07:30 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void cayman_pcie_gart_fini(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
cayman_pcie_gart_disable(rdev);
|
|
|
|
radeon_gart_table_vram_free(rdev);
|
|
|
|
radeon_gart_fini(rdev);
|
|
|
|
}
|
|
|
|
|
2011-11-18 01:13:28 +00:00
|
|
|
void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
|
|
|
|
int ring, u32 cp_int_cntl)
|
|
|
|
{
|
|
|
|
u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
|
|
|
|
|
|
|
|
WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
|
|
|
|
WREG32(CP_INT_CNTL, cp_int_cntl);
|
|
|
|
}
|
|
|
|
|
2011-03-03 01:07:31 +00:00
|
|
|
/*
|
|
|
|
* CP.
|
|
|
|
*/
|
2011-11-17 19:57:50 +00:00
|
|
|
void cayman_fence_ring_emit(struct radeon_device *rdev,
|
|
|
|
struct radeon_fence *fence)
|
|
|
|
{
|
|
|
|
struct radeon_ring *ring = &rdev->ring[fence->ring];
|
|
|
|
u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
|
|
|
|
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
/* flush read cache over gart for this vmid */
|
|
|
|
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
|
|
|
|
radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
|
|
|
|
radeon_ring_write(ring, 0);
|
2011-11-17 19:57:50 +00:00
|
|
|
radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
|
|
|
|
radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
|
|
|
|
radeon_ring_write(ring, 0xFFFFFFFF);
|
|
|
|
radeon_ring_write(ring, 0);
|
|
|
|
radeon_ring_write(ring, 10); /* poll interval */
|
|
|
|
/* EVENT_WRITE_EOP - flush caches, send int */
|
|
|
|
radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
|
|
|
|
radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
|
|
|
|
radeon_ring_write(ring, addr & 0xffffffff);
|
|
|
|
radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
|
|
|
|
radeon_ring_write(ring, fence->seq);
|
|
|
|
radeon_ring_write(ring, 0);
|
|
|
|
}
|
|
|
|
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
|
|
|
|
{
|
2012-05-08 12:24:01 +00:00
|
|
|
struct radeon_ring *ring = &rdev->ring[ib->ring];
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
|
|
|
|
/* set to DX10/11 mode */
|
|
|
|
radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
|
|
|
|
radeon_ring_write(ring, 1);
|
2012-07-06 14:22:55 +00:00
|
|
|
|
|
|
|
if (ring->rptr_save_reg) {
|
|
|
|
uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
|
|
|
|
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
|
|
|
|
radeon_ring_write(ring, ((ring->rptr_save_reg -
|
|
|
|
PACKET3_SET_CONFIG_REG_START) >> 2));
|
|
|
|
radeon_ring_write(ring, next_rptr);
|
|
|
|
}
|
|
|
|
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
|
|
|
|
radeon_ring_write(ring,
|
|
|
|
#ifdef __BIG_ENDIAN
|
|
|
|
(2 << 0) |
|
|
|
|
#endif
|
|
|
|
(ib->gpu_addr & 0xFFFFFFFC));
|
|
|
|
radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
|
|
|
|
radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
|
|
|
|
|
|
|
|
/* flush read cache over gart for this vmid */
|
|
|
|
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
|
|
|
|
radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
|
|
|
|
radeon_ring_write(ring, ib->vm_id);
|
|
|
|
radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
|
|
|
|
radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
|
|
|
|
radeon_ring_write(ring, 0xFFFFFFFF);
|
|
|
|
radeon_ring_write(ring, 0);
|
|
|
|
radeon_ring_write(ring, 10); /* poll interval */
|
|
|
|
}
|
|
|
|
|
2011-03-03 01:07:31 +00:00
|
|
|
static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
|
|
|
|
{
|
|
|
|
if (enable)
|
|
|
|
WREG32(CP_ME_CNTL, 0);
|
|
|
|
else {
|
2011-03-16 01:34:41 +00:00
|
|
|
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
|
2011-03-03 01:07:31 +00:00
|
|
|
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
|
|
|
|
WREG32(SCRATCH_UMSK, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cayman_cp_load_microcode(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
const __be32 *fw_data;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!rdev->me_fw || !rdev->pfp_fw)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
cayman_cp_enable(rdev, false);
|
|
|
|
|
|
|
|
fw_data = (const __be32 *)rdev->pfp_fw->data;
|
|
|
|
WREG32(CP_PFP_UCODE_ADDR, 0);
|
|
|
|
for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
|
|
|
|
WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
|
|
|
|
WREG32(CP_PFP_UCODE_ADDR, 0);
|
|
|
|
|
|
|
|
fw_data = (const __be32 *)rdev->me_fw->data;
|
|
|
|
WREG32(CP_ME_RAM_WADDR, 0);
|
|
|
|
for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
|
|
|
|
WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
|
|
|
|
|
|
|
|
WREG32(CP_PFP_UCODE_ADDR, 0);
|
|
|
|
WREG32(CP_ME_RAM_WADDR, 0);
|
|
|
|
WREG32(CP_ME_RAM_RADDR, 0);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cayman_cp_start(struct radeon_device *rdev)
|
|
|
|
{
|
2011-10-23 10:56:27 +00:00
|
|
|
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
2011-03-03 01:07:31 +00:00
|
|
|
int r, i;
|
|
|
|
|
2011-10-23 10:56:27 +00:00
|
|
|
r = radeon_ring_lock(rdev, ring, 7);
|
2011-03-03 01:07:31 +00:00
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
|
|
|
|
return r;
|
|
|
|
}
|
2011-10-23 10:56:27 +00:00
|
|
|
radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
|
|
|
|
radeon_ring_write(ring, 0x1);
|
|
|
|
radeon_ring_write(ring, 0x0);
|
|
|
|
radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
|
|
|
|
radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
|
|
|
|
radeon_ring_write(ring, 0);
|
|
|
|
radeon_ring_write(ring, 0);
|
|
|
|
radeon_ring_unlock_commit(rdev, ring);
|
2011-03-03 01:07:31 +00:00
|
|
|
|
|
|
|
cayman_cp_enable(rdev, true);
|
|
|
|
|
2011-10-23 10:56:27 +00:00
|
|
|
r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
|
2011-03-03 01:07:31 +00:00
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* setup clear context state */
|
2011-10-23 10:56:27 +00:00
|
|
|
radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
|
|
|
|
radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
|
2011-03-03 01:07:31 +00:00
|
|
|
|
|
|
|
for (i = 0; i < cayman_default_size; i++)
|
2011-10-23 10:56:27 +00:00
|
|
|
radeon_ring_write(ring, cayman_default_state[i]);
|
2011-03-03 01:07:31 +00:00
|
|
|
|
2011-10-23 10:56:27 +00:00
|
|
|
radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
|
|
|
|
radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
|
2011-03-03 01:07:31 +00:00
|
|
|
|
|
|
|
/* set clear context state */
|
2011-10-23 10:56:27 +00:00
|
|
|
radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
|
|
|
|
radeon_ring_write(ring, 0);
|
2011-03-03 01:07:31 +00:00
|
|
|
|
|
|
|
/* SQ_VTX_BASE_VTX_LOC */
|
2011-10-23 10:56:27 +00:00
|
|
|
radeon_ring_write(ring, 0xc0026f00);
|
|
|
|
radeon_ring_write(ring, 0x00000000);
|
|
|
|
radeon_ring_write(ring, 0x00000000);
|
|
|
|
radeon_ring_write(ring, 0x00000000);
|
2011-03-03 01:07:31 +00:00
|
|
|
|
|
|
|
/* Clear consts */
|
2011-10-23 10:56:27 +00:00
|
|
|
radeon_ring_write(ring, 0xc0036f00);
|
|
|
|
radeon_ring_write(ring, 0x00000bc4);
|
|
|
|
radeon_ring_write(ring, 0xffffffff);
|
|
|
|
radeon_ring_write(ring, 0xffffffff);
|
|
|
|
radeon_ring_write(ring, 0xffffffff);
|
2011-03-03 01:07:31 +00:00
|
|
|
|
2011-10-23 10:56:27 +00:00
|
|
|
radeon_ring_write(ring, 0xc0026900);
|
|
|
|
radeon_ring_write(ring, 0x00000316);
|
|
|
|
radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
|
|
|
|
radeon_ring_write(ring, 0x00000010); /* */
|
2011-03-03 01:07:39 +00:00
|
|
|
|
2011-10-23 10:56:27 +00:00
|
|
|
radeon_ring_unlock_commit(rdev, ring);
|
2011-03-03 01:07:31 +00:00
|
|
|
|
|
|
|
/* XXX init other rings */
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-03-03 01:07:34 +00:00
|
|
|
static void cayman_cp_fini(struct radeon_device *rdev)
|
|
|
|
{
|
2012-07-06 14:22:55 +00:00
|
|
|
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
2011-03-03 01:07:34 +00:00
|
|
|
cayman_cp_enable(rdev, false);
|
2012-07-06 14:22:55 +00:00
|
|
|
radeon_ring_fini(rdev, ring);
|
|
|
|
radeon_scratch_free(rdev, ring->rptr_save_reg);
|
2011-03-03 01:07:34 +00:00
|
|
|
}
|
|
|
|
|
2011-03-03 01:07:31 +00:00
|
|
|
int cayman_cp_resume(struct radeon_device *rdev)
|
|
|
|
{
|
2012-07-04 19:36:53 +00:00
|
|
|
static const int ridx[] = {
|
|
|
|
RADEON_RING_TYPE_GFX_INDEX,
|
|
|
|
CAYMAN_RING_TYPE_CP1_INDEX,
|
|
|
|
CAYMAN_RING_TYPE_CP2_INDEX
|
|
|
|
};
|
|
|
|
static const unsigned cp_rb_cntl[] = {
|
|
|
|
CP_RB0_CNTL,
|
|
|
|
CP_RB1_CNTL,
|
|
|
|
CP_RB2_CNTL,
|
|
|
|
};
|
|
|
|
static const unsigned cp_rb_rptr_addr[] = {
|
|
|
|
CP_RB0_RPTR_ADDR,
|
|
|
|
CP_RB1_RPTR_ADDR,
|
|
|
|
CP_RB2_RPTR_ADDR
|
|
|
|
};
|
|
|
|
static const unsigned cp_rb_rptr_addr_hi[] = {
|
|
|
|
CP_RB0_RPTR_ADDR_HI,
|
|
|
|
CP_RB1_RPTR_ADDR_HI,
|
|
|
|
CP_RB2_RPTR_ADDR_HI
|
|
|
|
};
|
|
|
|
static const unsigned cp_rb_base[] = {
|
|
|
|
CP_RB0_BASE,
|
|
|
|
CP_RB1_BASE,
|
|
|
|
CP_RB2_BASE
|
|
|
|
};
|
2011-10-23 10:56:27 +00:00
|
|
|
struct radeon_ring *ring;
|
2012-07-04 19:36:53 +00:00
|
|
|
int i, r;
|
2011-03-03 01:07:31 +00:00
|
|
|
|
|
|
|
/* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
|
|
|
|
WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
|
|
|
|
SOFT_RESET_PA |
|
|
|
|
SOFT_RESET_SH |
|
|
|
|
SOFT_RESET_VGT |
|
2011-08-24 20:00:17 +00:00
|
|
|
SOFT_RESET_SPI |
|
2011-03-03 01:07:31 +00:00
|
|
|
SOFT_RESET_SX));
|
|
|
|
RREG32(GRBM_SOFT_RESET);
|
|
|
|
mdelay(15);
|
|
|
|
WREG32(GRBM_SOFT_RESET, 0);
|
|
|
|
RREG32(GRBM_SOFT_RESET);
|
|
|
|
|
2011-09-15 17:02:22 +00:00
|
|
|
WREG32(CP_SEM_WAIT_TIMER, 0x0);
|
2012-01-20 19:47:43 +00:00
|
|
|
WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
|
2011-03-03 01:07:31 +00:00
|
|
|
|
|
|
|
/* Set the write pointer delay */
|
|
|
|
WREG32(CP_RB_WPTR_DELAY, 0);
|
|
|
|
|
|
|
|
WREG32(CP_DEBUG, (1 << 27));
|
|
|
|
|
|
|
|
/* set the wb address wether it's enabled or not */
|
|
|
|
WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
|
2012-07-04 19:36:53 +00:00
|
|
|
WREG32(SCRATCH_UMSK, 0xff);
|
2011-03-03 01:07:31 +00:00
|
|
|
|
2012-07-04 19:36:53 +00:00
|
|
|
for (i = 0; i < 3; ++i) {
|
|
|
|
uint32_t rb_cntl;
|
|
|
|
uint64_t addr;
|
2011-03-03 01:07:31 +00:00
|
|
|
|
2012-07-04 19:36:53 +00:00
|
|
|
/* Set ring buffer size */
|
|
|
|
ring = &rdev->ring[ridx[i]];
|
|
|
|
rb_cntl = drm_order(ring->ring_size / 8);
|
|
|
|
rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8;
|
2011-03-03 01:07:31 +00:00
|
|
|
#ifdef __BIG_ENDIAN
|
2012-07-04 19:36:53 +00:00
|
|
|
rb_cntl |= BUF_SWAP_32BIT;
|
2011-03-03 01:07:31 +00:00
|
|
|
#endif
|
2012-07-04 19:36:53 +00:00
|
|
|
WREG32(cp_rb_cntl[i], rb_cntl);
|
2011-03-03 01:07:31 +00:00
|
|
|
|
2012-07-04 19:36:53 +00:00
|
|
|
/* set the wb address wether it's enabled or not */
|
|
|
|
addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
|
|
|
|
WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
|
|
|
|
WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
|
|
|
|
}
|
2011-03-03 01:07:31 +00:00
|
|
|
|
2012-07-04 19:36:53 +00:00
|
|
|
/* set the rb base addr, this causes an internal reset of ALL rings */
|
|
|
|
for (i = 0; i < 3; ++i) {
|
|
|
|
ring = &rdev->ring[ridx[i]];
|
|
|
|
WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
|
|
|
|
}
|
2011-03-03 01:07:31 +00:00
|
|
|
|
2012-07-04 19:36:53 +00:00
|
|
|
for (i = 0; i < 3; ++i) {
|
|
|
|
/* Initialize the ring buffer's read and write pointers */
|
|
|
|
ring = &rdev->ring[ridx[i]];
|
|
|
|
WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
|
2011-03-03 01:07:31 +00:00
|
|
|
|
2012-07-04 19:36:53 +00:00
|
|
|
ring->rptr = ring->wptr = 0;
|
|
|
|
WREG32(ring->rptr_reg, ring->rptr);
|
|
|
|
WREG32(ring->wptr_reg, ring->wptr);
|
2011-03-03 01:07:31 +00:00
|
|
|
|
2012-07-04 19:36:53 +00:00
|
|
|
mdelay(1);
|
|
|
|
WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
|
|
|
|
}
|
2011-03-03 01:07:31 +00:00
|
|
|
|
|
|
|
/* start the rings */
|
|
|
|
cayman_cp_start(rdev);
|
2011-10-23 10:56:27 +00:00
|
|
|
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
|
|
|
|
rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
|
|
|
|
rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
|
2011-03-03 01:07:31 +00:00
|
|
|
/* this only test cp0 */
|
2012-02-23 22:53:45 +00:00
|
|
|
r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
|
2011-03-03 01:07:31 +00:00
|
|
|
if (r) {
|
2011-10-23 10:56:27 +00:00
|
|
|
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
|
|
|
|
rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
|
|
|
|
rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
|
2011-03-03 01:07:31 +00:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-03-03 01:07:33 +00:00
|
|
|
static int cayman_gpu_soft_reset(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
struct evergreen_mc_save save;
|
|
|
|
u32 grbm_reset = 0;
|
|
|
|
|
|
|
|
if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
dev_info(rdev->dev, "GPU softreset \n");
|
|
|
|
dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
|
|
|
|
RREG32(GRBM_STATUS));
|
|
|
|
dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
|
|
|
|
RREG32(GRBM_STATUS_SE0));
|
|
|
|
dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
|
|
|
|
RREG32(GRBM_STATUS_SE1));
|
|
|
|
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
|
|
|
|
RREG32(SRBM_STATUS));
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
|
|
|
|
RREG32(0x14F8));
|
|
|
|
dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
|
|
|
|
RREG32(0x14D8));
|
|
|
|
dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
|
|
|
|
RREG32(0x14FC));
|
|
|
|
dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
|
|
|
|
RREG32(0x14DC));
|
|
|
|
|
2011-03-03 01:07:33 +00:00
|
|
|
evergreen_mc_stop(rdev, &save);
|
|
|
|
if (evergreen_mc_wait_for_idle(rdev)) {
|
|
|
|
dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
|
|
|
|
}
|
|
|
|
/* Disable CP parsing/prefetching */
|
|
|
|
WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
|
|
|
|
|
|
|
|
/* reset all the gfx blocks */
|
|
|
|
grbm_reset = (SOFT_RESET_CP |
|
|
|
|
SOFT_RESET_CB |
|
|
|
|
SOFT_RESET_DB |
|
|
|
|
SOFT_RESET_GDS |
|
|
|
|
SOFT_RESET_PA |
|
|
|
|
SOFT_RESET_SC |
|
|
|
|
SOFT_RESET_SPI |
|
|
|
|
SOFT_RESET_SH |
|
|
|
|
SOFT_RESET_SX |
|
|
|
|
SOFT_RESET_TC |
|
|
|
|
SOFT_RESET_TA |
|
|
|
|
SOFT_RESET_VGT |
|
|
|
|
SOFT_RESET_IA);
|
|
|
|
|
|
|
|
dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
|
|
|
|
WREG32(GRBM_SOFT_RESET, grbm_reset);
|
|
|
|
(void)RREG32(GRBM_SOFT_RESET);
|
|
|
|
udelay(50);
|
|
|
|
WREG32(GRBM_SOFT_RESET, 0);
|
|
|
|
(void)RREG32(GRBM_SOFT_RESET);
|
|
|
|
/* Wait a little for things to settle down */
|
|
|
|
udelay(50);
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
|
2011-03-03 01:07:33 +00:00
|
|
|
dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
|
|
|
|
RREG32(GRBM_STATUS));
|
|
|
|
dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
|
|
|
|
RREG32(GRBM_STATUS_SE0));
|
|
|
|
dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
|
|
|
|
RREG32(GRBM_STATUS_SE1));
|
|
|
|
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
|
|
|
|
RREG32(SRBM_STATUS));
|
|
|
|
evergreen_mc_resume(rdev, &save);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int cayman_asic_reset(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
return cayman_gpu_soft_reset(rdev);
|
|
|
|
}
|
|
|
|
|
2011-03-03 01:07:34 +00:00
|
|
|
static int cayman_startup(struct radeon_device *rdev)
|
|
|
|
{
|
2011-10-23 10:56:27 +00:00
|
|
|
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
2011-03-03 01:07:34 +00:00
|
|
|
int r;
|
|
|
|
|
2011-09-20 14:22:58 +00:00
|
|
|
/* enable pcie gen2 link */
|
|
|
|
evergreen_pcie_gen2_enable(rdev);
|
|
|
|
|
2012-03-20 21:18:39 +00:00
|
|
|
if (rdev->flags & RADEON_IS_IGP) {
|
|
|
|
if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
|
|
|
|
r = ni_init_microcode(rdev);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to load firmware!\n");
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
|
|
|
|
r = ni_init_microcode(rdev);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to load firmware!\n");
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
r = ni_mc_load_microcode(rdev);
|
2011-03-03 01:07:34 +00:00
|
|
|
if (r) {
|
2012-03-20 21:18:39 +00:00
|
|
|
DRM_ERROR("Failed to load MC firmware!\n");
|
2011-03-03 01:07:34 +00:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-10-28 14:30:02 +00:00
|
|
|
r = r600_vram_scratch_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
2011-03-03 01:07:34 +00:00
|
|
|
evergreen_mc_program(rdev);
|
|
|
|
r = cayman_pcie_gart_enable(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
cayman_gpu_init(rdev);
|
|
|
|
|
2011-05-25 20:39:00 +00:00
|
|
|
r = evergreen_blit_init(rdev);
|
2011-03-03 01:07:34 +00:00
|
|
|
if (r) {
|
2011-10-13 03:29:41 +00:00
|
|
|
r600_blit_fini(rdev);
|
2012-02-23 22:53:42 +00:00
|
|
|
rdev->asic->copy.copy = NULL;
|
2011-03-03 01:07:34 +00:00
|
|
|
dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
|
|
|
|
}
|
|
|
|
|
2012-03-20 21:18:39 +00:00
|
|
|
/* allocate rlc buffers */
|
|
|
|
if (rdev->flags & RADEON_IS_IGP) {
|
|
|
|
r = si_rlc_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to init rlc BOs!\n");
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-03-03 01:07:34 +00:00
|
|
|
/* allocate wb buffer */
|
|
|
|
r = radeon_wb_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
2011-11-20 20:45:34 +00:00
|
|
|
r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
|
|
|
|
if (r) {
|
|
|
|
dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
|
|
|
|
if (r) {
|
|
|
|
dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
|
|
|
|
if (r) {
|
|
|
|
dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2011-03-03 01:07:34 +00:00
|
|
|
/* Enable IRQ */
|
|
|
|
r = r600_irq_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("radeon: IH init failed (%d).\n", r);
|
|
|
|
radeon_irq_kms_fini(rdev);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
evergreen_irq_set(rdev);
|
|
|
|
|
2011-10-23 10:56:27 +00:00
|
|
|
r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
|
2011-11-17 19:25:56 +00:00
|
|
|
CP_RB0_RPTR, CP_RB0_WPTR,
|
|
|
|
0, 0xfffff, RADEON_CP_PACKET2);
|
2011-03-03 01:07:34 +00:00
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
r = cayman_cp_load_microcode(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
r = cayman_cp_resume(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
2012-07-05 09:55:34 +00:00
|
|
|
r = radeon_ib_pool_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
|
drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-15 16:48:34 +00:00
|
|
|
return r;
|
2012-07-05 09:55:34 +00:00
|
|
|
}
|
drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-15 16:48:34 +00:00
|
|
|
|
2012-07-05 12:32:00 +00:00
|
|
|
r = radeon_vm_manager_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
return r;
|
2012-07-05 12:32:00 +00:00
|
|
|
}
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
|
2012-06-11 10:34:01 +00:00
|
|
|
r = r600_audio_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
2011-03-03 01:07:34 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int cayman_resume(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
int r;
|
|
|
|
|
|
|
|
/* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
|
|
|
|
* posting will perform necessary task to bring back GPU into good
|
|
|
|
* shape.
|
|
|
|
*/
|
|
|
|
/* post card */
|
|
|
|
atom_asic_init(rdev->mode_info.atom_context);
|
|
|
|
|
drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-15 16:48:34 +00:00
|
|
|
rdev->accel_working = true;
|
2011-03-03 01:07:34 +00:00
|
|
|
r = cayman_startup(rdev);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("cayman startup failed on resume\n");
|
2012-02-20 22:57:20 +00:00
|
|
|
rdev->accel_working = false;
|
2011-03-03 01:07:34 +00:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
int cayman_suspend(struct radeon_device *rdev)
|
|
|
|
{
|
2012-06-11 10:34:01 +00:00
|
|
|
r600_audio_fini(rdev);
|
2011-03-03 01:07:34 +00:00
|
|
|
cayman_cp_enable(rdev, false);
|
2011-10-23 10:56:27 +00:00
|
|
|
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
|
2011-03-03 01:07:34 +00:00
|
|
|
evergreen_irq_suspend(rdev);
|
|
|
|
radeon_wb_disable(rdev);
|
|
|
|
cayman_pcie_gart_disable(rdev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Plan is to move initialization in that function and use
|
|
|
|
* helper function so that radeon_device_init pretty much
|
|
|
|
* do nothing more than calling asic specific function. This
|
|
|
|
* should also allow to remove a bunch of callback function
|
|
|
|
* like vram_info.
|
|
|
|
*/
|
|
|
|
int cayman_init(struct radeon_device *rdev)
|
|
|
|
{
|
2011-10-23 10:56:27 +00:00
|
|
|
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
2011-03-03 01:07:34 +00:00
|
|
|
int r;
|
|
|
|
|
|
|
|
/* Read BIOS */
|
|
|
|
if (!radeon_get_bios(rdev)) {
|
|
|
|
if (ASIC_IS_AVIVO(rdev))
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
/* Must be an ATOMBIOS */
|
|
|
|
if (!rdev->is_atom_bios) {
|
|
|
|
dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
r = radeon_atombios_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
|
|
|
/* Post card if necessary */
|
|
|
|
if (!radeon_card_posted(rdev)) {
|
|
|
|
if (!rdev->bios) {
|
|
|
|
dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
DRM_INFO("GPU not posted. posting now...\n");
|
|
|
|
atom_asic_init(rdev->mode_info.atom_context);
|
|
|
|
}
|
|
|
|
/* Initialize scratch registers */
|
|
|
|
r600_scratch_init(rdev);
|
|
|
|
/* Initialize surface registers */
|
|
|
|
radeon_surface_init(rdev);
|
|
|
|
/* Initialize clocks */
|
|
|
|
radeon_get_clock_info(rdev->ddev);
|
|
|
|
/* Fence driver */
|
2011-11-20 20:45:34 +00:00
|
|
|
r = radeon_fence_driver_init(rdev);
|
2011-03-03 01:07:34 +00:00
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
/* initialize memory controller */
|
|
|
|
r = evergreen_mc_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
/* Memory manager */
|
|
|
|
r = radeon_bo_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
|
|
|
r = radeon_irq_kms_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
2011-10-23 10:56:27 +00:00
|
|
|
ring->ring_obj = NULL;
|
|
|
|
r600_ring_init(rdev, ring, 1024 * 1024);
|
2011-03-03 01:07:34 +00:00
|
|
|
|
|
|
|
rdev->ih.ring_obj = NULL;
|
|
|
|
r600_ih_ring_init(rdev, 64 * 1024);
|
|
|
|
|
|
|
|
r = r600_pcie_gart_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
|
|
|
rdev->accel_working = true;
|
|
|
|
r = cayman_startup(rdev);
|
|
|
|
if (r) {
|
|
|
|
dev_err(rdev->dev, "disabling GPU acceleration\n");
|
|
|
|
cayman_cp_fini(rdev);
|
|
|
|
r600_irq_fini(rdev);
|
2012-03-20 21:18:39 +00:00
|
|
|
if (rdev->flags & RADEON_IS_IGP)
|
|
|
|
si_rlc_fini(rdev);
|
2011-03-03 01:07:34 +00:00
|
|
|
radeon_wb_fini(rdev);
|
2012-07-05 09:55:34 +00:00
|
|
|
radeon_ib_pool_fini(rdev);
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
radeon_vm_manager_fini(rdev);
|
2011-03-03 01:07:34 +00:00
|
|
|
radeon_irq_kms_fini(rdev);
|
|
|
|
cayman_pcie_gart_fini(rdev);
|
|
|
|
rdev->accel_working = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Don't start up if the MC ucode is missing.
|
|
|
|
* The default clocks and voltages before the MC ucode
|
|
|
|
* is loaded are not suffient for advanced operations.
|
2012-03-20 21:18:39 +00:00
|
|
|
*
|
|
|
|
* We can skip this check for TN, because there is no MC
|
|
|
|
* ucode.
|
2011-03-03 01:07:34 +00:00
|
|
|
*/
|
2012-03-20 21:18:39 +00:00
|
|
|
if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
|
2011-03-03 01:07:34 +00:00
|
|
|
DRM_ERROR("radeon: MC ucode required for NI+.\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void cayman_fini(struct radeon_device *rdev)
|
|
|
|
{
|
2011-10-13 03:29:41 +00:00
|
|
|
r600_blit_fini(rdev);
|
2011-03-03 01:07:34 +00:00
|
|
|
cayman_cp_fini(rdev);
|
|
|
|
r600_irq_fini(rdev);
|
2012-03-20 21:18:39 +00:00
|
|
|
if (rdev->flags & RADEON_IS_IGP)
|
|
|
|
si_rlc_fini(rdev);
|
2011-03-03 01:07:34 +00:00
|
|
|
radeon_wb_fini(rdev);
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
radeon_vm_manager_fini(rdev);
|
2012-07-05 09:55:34 +00:00
|
|
|
radeon_ib_pool_fini(rdev);
|
2011-03-03 01:07:34 +00:00
|
|
|
radeon_irq_kms_fini(rdev);
|
|
|
|
cayman_pcie_gart_fini(rdev);
|
2011-10-28 14:30:02 +00:00
|
|
|
r600_vram_scratch_fini(rdev);
|
2011-03-03 01:07:34 +00:00
|
|
|
radeon_gem_fini(rdev);
|
|
|
|
radeon_fence_driver_fini(rdev);
|
|
|
|
radeon_bo_fini(rdev);
|
|
|
|
radeon_atombios_fini(rdev);
|
|
|
|
kfree(rdev->bios);
|
|
|
|
rdev->bios = NULL;
|
|
|
|
}
|
|
|
|
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
/*
|
|
|
|
* vm
|
|
|
|
*/
|
|
|
|
int cayman_vm_init(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
/* number of VMs */
|
|
|
|
rdev->vm_manager.nvm = 8;
|
|
|
|
/* base offset of vram pages */
|
2012-03-20 21:18:38 +00:00
|
|
|
if (rdev->flags & RADEON_IS_IGP) {
|
|
|
|
u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
|
|
|
|
tmp <<= 22;
|
|
|
|
rdev->vm_manager.vram_base_offset = tmp;
|
|
|
|
} else
|
|
|
|
rdev->vm_manager.vram_base_offset = 0;
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 03:11:05 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void cayman_vm_fini(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
|
|
|
|
{
|
|
|
|
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (id << 2), 0);
|
|
|
|
WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (id << 2), vm->last_pfn);
|
|
|
|
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
|
|
|
|
/* flush hdp cache */
|
|
|
|
WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
|
|
|
|
/* bits 0-7 are the VM contexts0-7 */
|
|
|
|
WREG32(VM_INVALIDATE_REQUEST, 1 << id);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
|
|
|
|
{
|
|
|
|
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (vm->id << 2), 0);
|
|
|
|
WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (vm->id << 2), 0);
|
|
|
|
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
|
|
|
|
/* flush hdp cache */
|
|
|
|
WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
|
|
|
|
/* bits 0-7 are the VM contexts0-7 */
|
|
|
|
WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
|
|
|
|
{
|
|
|
|
if (vm->id == -1)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* flush hdp cache */
|
|
|
|
WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
|
|
|
|
/* bits 0-7 are the VM contexts0-7 */
|
|
|
|
WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define R600_PTE_VALID (1 << 0)
|
|
|
|
#define R600_PTE_SYSTEM (1 << 1)
|
|
|
|
#define R600_PTE_SNOOPED (1 << 2)
|
|
|
|
#define R600_PTE_READABLE (1 << 5)
|
|
|
|
#define R600_PTE_WRITEABLE (1 << 6)
|
|
|
|
|
|
|
|
uint32_t cayman_vm_page_flags(struct radeon_device *rdev,
|
|
|
|
struct radeon_vm *vm,
|
|
|
|
uint32_t flags)
|
|
|
|
{
|
|
|
|
uint32_t r600_flags = 0;
|
|
|
|
|
|
|
|
r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
|
|
|
|
r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
|
|
|
|
r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
|
|
|
|
if (flags & RADEON_VM_PAGE_SYSTEM) {
|
|
|
|
r600_flags |= R600_PTE_SYSTEM;
|
|
|
|
r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
|
|
|
|
}
|
|
|
|
return r600_flags;
|
|
|
|
}
|
|
|
|
|
|
|
|
void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm,
|
|
|
|
unsigned pfn, uint64_t addr, uint32_t flags)
|
|
|
|
{
|
|
|
|
void __iomem *ptr = (void *)vm->pt;
|
|
|
|
|
|
|
|
addr = addr & 0xFFFFFFFFFFFFF000ULL;
|
|
|
|
addr |= flags;
|
|
|
|
writeq(addr, ptr + (pfn * 8));
|
|
|
|
}
|