forked from Minki/linux
649 lines
16 KiB
C
649 lines
16 KiB
C
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include "clk.h"
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#define PLL_BASE_BYPASS BIT(31)
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#define PLL_BASE_ENABLE BIT(30)
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#define PLL_BASE_REF_ENABLE BIT(29)
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#define PLL_BASE_OVERRIDE BIT(28)
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#define PLL_BASE_DIVP_SHIFT 20
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#define PLL_BASE_DIVP_WIDTH 3
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#define PLL_BASE_DIVN_SHIFT 8
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#define PLL_BASE_DIVN_WIDTH 10
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#define PLL_BASE_DIVM_SHIFT 0
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#define PLL_BASE_DIVM_WIDTH 5
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#define PLLU_POST_DIVP_MASK 0x1
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#define PLL_MISC_DCCON_SHIFT 20
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#define PLL_MISC_CPCON_SHIFT 8
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#define PLL_MISC_CPCON_WIDTH 4
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#define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
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#define PLL_MISC_LFCON_SHIFT 4
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#define PLL_MISC_LFCON_WIDTH 4
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#define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
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#define PLL_MISC_VCOCON_SHIFT 0
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#define PLL_MISC_VCOCON_WIDTH 4
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#define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
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#define OUT_OF_TABLE_CPCON 8
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#define PMC_PLLP_WB0_OVERRIDE 0xf8
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#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
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#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
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#define PLL_POST_LOCK_DELAY 50
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#define PLLDU_LFCON_SET_DIVN 600
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#define PLLE_BASE_DIVCML_SHIFT 24
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#define PLLE_BASE_DIVCML_WIDTH 4
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#define PLLE_BASE_DIVP_SHIFT 16
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#define PLLE_BASE_DIVP_WIDTH 7
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#define PLLE_BASE_DIVN_SHIFT 8
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#define PLLE_BASE_DIVN_WIDTH 8
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#define PLLE_BASE_DIVM_SHIFT 0
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#define PLLE_BASE_DIVM_WIDTH 8
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#define PLLE_MISC_SETUP_BASE_SHIFT 16
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#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
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#define PLLE_MISC_LOCK_ENABLE BIT(9)
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#define PLLE_MISC_READY BIT(15)
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#define PLLE_MISC_SETUP_EX_SHIFT 2
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#define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
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#define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
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PLLE_MISC_SETUP_EX_MASK)
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#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
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#define PLLE_SS_CTRL 0x68
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#define PLLE_SS_DISABLE (7 << 10)
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#define PMC_SATA_PWRGT 0x1ac
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#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
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#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
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#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
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#define pll_readl_base(p) pll_readl(p->params->base_reg, p)
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#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
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#define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
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#define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
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#define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
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#define mask(w) ((1 << (w)) - 1)
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#define divm_mask(p) mask(p->divm_width)
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#define divn_mask(p) mask(p->divn_width)
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#define divp_mask(p) (p->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK : \
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mask(p->divp_width))
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#define divm_max(p) (divm_mask(p))
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#define divn_max(p) (divn_mask(p))
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#define divp_max(p) (1 << (divp_mask(p)))
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static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
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{
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u32 val;
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if (!(pll->flags & TEGRA_PLL_USE_LOCK))
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return;
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val = pll_readl_misc(pll);
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val |= BIT(pll->params->lock_enable_bit_idx);
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pll_writel_misc(val, pll);
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}
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static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
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void __iomem *lock_addr, u32 lock_bit_idx)
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{
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int i;
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u32 val;
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if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
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udelay(pll->params->lock_delay);
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return 0;
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}
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for (i = 0; i < pll->params->lock_delay; i++) {
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val = readl_relaxed(lock_addr);
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if (val & BIT(lock_bit_idx)) {
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udelay(PLL_POST_LOCK_DELAY);
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return 0;
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}
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udelay(2); /* timeout = 2 * lock time */
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}
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pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
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__clk_get_name(pll->hw.clk));
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return -1;
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}
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static int clk_pll_is_enabled(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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u32 val;
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if (pll->flags & TEGRA_PLLM) {
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val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
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if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
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return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
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}
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val = pll_readl_base(pll);
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return val & PLL_BASE_ENABLE ? 1 : 0;
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}
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static int _clk_pll_enable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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u32 val;
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clk_pll_enable_lock(pll);
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val = pll_readl_base(pll);
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val &= ~PLL_BASE_BYPASS;
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val |= PLL_BASE_ENABLE;
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pll_writel_base(val, pll);
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if (pll->flags & TEGRA_PLLM) {
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val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
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val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
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writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
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}
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clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->base_reg,
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pll->params->lock_bit_idx);
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return 0;
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}
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static void _clk_pll_disable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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u32 val;
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val = pll_readl_base(pll);
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val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
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pll_writel_base(val, pll);
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if (pll->flags & TEGRA_PLLM) {
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val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
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val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
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writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
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}
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}
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static int clk_pll_enable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned long flags = 0;
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int ret;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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ret = _clk_pll_enable(hw);
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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return ret;
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}
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static void clk_pll_disable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned long flags = 0;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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_clk_pll_disable(hw);
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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}
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static int _get_table_rate(struct clk_hw *hw,
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struct tegra_clk_pll_freq_table *cfg,
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unsigned long rate, unsigned long parent_rate)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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struct tegra_clk_pll_freq_table *sel;
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for (sel = pll->freq_table; sel->input_rate != 0; sel++)
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if (sel->input_rate == parent_rate &&
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sel->output_rate == rate)
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break;
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if (sel->input_rate == 0)
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return -EINVAL;
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BUG_ON(sel->p < 1);
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cfg->input_rate = sel->input_rate;
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cfg->output_rate = sel->output_rate;
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cfg->m = sel->m;
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cfg->n = sel->n;
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cfg->p = sel->p;
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cfg->cpcon = sel->cpcon;
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return 0;
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}
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static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
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unsigned long rate, unsigned long parent_rate)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned long cfreq;
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u32 p_div = 0;
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switch (parent_rate) {
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case 12000000:
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case 26000000:
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cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
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break;
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case 13000000:
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cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
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break;
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case 16800000:
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case 19200000:
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cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
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break;
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case 9600000:
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case 28800000:
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/*
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* PLL_P_OUT1 rate is not listed in PLLA table
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*/
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cfreq = parent_rate/(parent_rate/1000000);
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break;
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default:
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pr_err("%s Unexpected reference rate %lu\n",
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__func__, parent_rate);
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BUG();
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}
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/* Raise VCO to guarantee 0.5% accuracy */
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for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
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cfg->output_rate <<= 1)
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p_div++;
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cfg->p = 1 << p_div;
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cfg->m = parent_rate / cfreq;
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cfg->n = cfg->output_rate / cfreq;
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cfg->cpcon = OUT_OF_TABLE_CPCON;
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if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
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cfg->p > divp_max(pll) || cfg->output_rate > pll->params->vco_max) {
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pr_err("%s: Failed to set %s rate %lu\n",
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__func__, __clk_get_name(hw->clk), rate);
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return -EINVAL;
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}
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return 0;
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}
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static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
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unsigned long rate)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned long flags = 0;
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u32 divp, val, old_base;
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int state;
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divp = __ffs(cfg->p);
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if (pll->flags & TEGRA_PLLU)
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divp ^= 1;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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old_base = val = pll_readl_base(pll);
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val &= ~((divm_mask(pll) << pll->divm_shift) |
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(divn_mask(pll) << pll->divn_shift) |
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(divp_mask(pll) << pll->divp_shift));
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val |= ((cfg->m << pll->divm_shift) |
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(cfg->n << pll->divn_shift) |
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(divp << pll->divp_shift));
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if (val == old_base) {
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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return 0;
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}
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state = clk_pll_is_enabled(hw);
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if (state) {
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_clk_pll_disable(hw);
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val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
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}
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pll_writel_base(val, pll);
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if (pll->flags & TEGRA_PLL_HAS_CPCON) {
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val = pll_readl_misc(pll);
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val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
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val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
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if (pll->flags & TEGRA_PLL_SET_LFCON) {
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val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
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if (cfg->n >= PLLDU_LFCON_SET_DIVN)
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val |= 0x1 << PLL_MISC_LFCON_SHIFT;
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} else if (pll->flags & TEGRA_PLL_SET_DCCON) {
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val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
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if (rate >= (pll->params->vco_max >> 1))
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val |= 0x1 << PLL_MISC_DCCON_SHIFT;
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}
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pll_writel_misc(val, pll);
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}
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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if (state)
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clk_pll_enable(hw);
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return 0;
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}
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static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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struct tegra_clk_pll_freq_table cfg;
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if (pll->flags & TEGRA_PLL_FIXED) {
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if (rate != pll->fixed_rate) {
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pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
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__func__, __clk_get_name(hw->clk),
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pll->fixed_rate, rate);
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return -EINVAL;
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}
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return 0;
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}
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if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
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_calc_rate(hw, &cfg, rate, parent_rate))
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return -EINVAL;
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return _program_pll(hw, &cfg, rate);
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}
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static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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struct tegra_clk_pll_freq_table cfg;
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u64 output_rate = *prate;
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if (pll->flags & TEGRA_PLL_FIXED)
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return pll->fixed_rate;
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/* PLLM is used for memory; we do not change rate */
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if (pll->flags & TEGRA_PLLM)
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return __clk_get_rate(hw->clk);
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|
||
|
if (_get_table_rate(hw, &cfg, rate, *prate) &&
|
||
|
_calc_rate(hw, &cfg, rate, *prate))
|
||
|
return -EINVAL;
|
||
|
|
||
|
output_rate *= cfg.n;
|
||
|
do_div(output_rate, cfg.m * cfg.p);
|
||
|
|
||
|
return output_rate;
|
||
|
}
|
||
|
|
||
|
static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
|
||
|
unsigned long parent_rate)
|
||
|
{
|
||
|
struct tegra_clk_pll *pll = to_clk_pll(hw);
|
||
|
u32 val = pll_readl_base(pll);
|
||
|
u32 divn = 0, divm = 0, divp = 0;
|
||
|
u64 rate = parent_rate;
|
||
|
|
||
|
if (val & PLL_BASE_BYPASS)
|
||
|
return parent_rate;
|
||
|
|
||
|
if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
|
||
|
struct tegra_clk_pll_freq_table sel;
|
||
|
if (_get_table_rate(hw, &sel, pll->fixed_rate, parent_rate)) {
|
||
|
pr_err("Clock %s has unknown fixed frequency\n",
|
||
|
__clk_get_name(hw->clk));
|
||
|
BUG();
|
||
|
}
|
||
|
return pll->fixed_rate;
|
||
|
}
|
||
|
|
||
|
divp = (val >> pll->divp_shift) & (divp_mask(pll));
|
||
|
if (pll->flags & TEGRA_PLLU)
|
||
|
divp ^= 1;
|
||
|
|
||
|
divn = (val >> pll->divn_shift) & (divn_mask(pll));
|
||
|
divm = (val >> pll->divm_shift) & (divm_mask(pll));
|
||
|
divm *= (1 << divp);
|
||
|
|
||
|
rate *= divn;
|
||
|
do_div(rate, divm);
|
||
|
return rate;
|
||
|
}
|
||
|
|
||
|
static int clk_plle_training(struct tegra_clk_pll *pll)
|
||
|
{
|
||
|
u32 val;
|
||
|
unsigned long timeout;
|
||
|
|
||
|
if (!pll->pmc)
|
||
|
return -ENOSYS;
|
||
|
|
||
|
/*
|
||
|
* PLLE is already disabled, and setup cleared;
|
||
|
* create falling edge on PLLE IDDQ input.
|
||
|
*/
|
||
|
val = readl(pll->pmc + PMC_SATA_PWRGT);
|
||
|
val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
|
||
|
writel(val, pll->pmc + PMC_SATA_PWRGT);
|
||
|
|
||
|
val = readl(pll->pmc + PMC_SATA_PWRGT);
|
||
|
val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
|
||
|
writel(val, pll->pmc + PMC_SATA_PWRGT);
|
||
|
|
||
|
val = readl(pll->pmc + PMC_SATA_PWRGT);
|
||
|
val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
|
||
|
writel(val, pll->pmc + PMC_SATA_PWRGT);
|
||
|
|
||
|
val = pll_readl_misc(pll);
|
||
|
|
||
|
timeout = jiffies + msecs_to_jiffies(100);
|
||
|
while (1) {
|
||
|
val = pll_readl_misc(pll);
|
||
|
if (val & PLLE_MISC_READY)
|
||
|
break;
|
||
|
if (time_after(jiffies, timeout)) {
|
||
|
pr_err("%s: timeout waiting for PLLE\n", __func__);
|
||
|
return -EBUSY;
|
||
|
}
|
||
|
udelay(300);
|
||
|
}
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int clk_plle_enable(struct clk_hw *hw)
|
||
|
{
|
||
|
struct tegra_clk_pll *pll = to_clk_pll(hw);
|
||
|
unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
|
||
|
struct tegra_clk_pll_freq_table sel;
|
||
|
u32 val;
|
||
|
int err;
|
||
|
|
||
|
if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
|
||
|
return -EINVAL;
|
||
|
|
||
|
clk_pll_disable(hw);
|
||
|
|
||
|
val = pll_readl_misc(pll);
|
||
|
val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
|
||
|
pll_writel_misc(val, pll);
|
||
|
|
||
|
val = pll_readl_misc(pll);
|
||
|
if (!(val & PLLE_MISC_READY)) {
|
||
|
err = clk_plle_training(pll);
|
||
|
if (err)
|
||
|
return err;
|
||
|
}
|
||
|
|
||
|
if (pll->flags & TEGRA_PLLE_CONFIGURE) {
|
||
|
/* configure dividers */
|
||
|
val = pll_readl_base(pll);
|
||
|
val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
|
||
|
val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
|
||
|
val |= sel.m << pll->divm_shift;
|
||
|
val |= sel.n << pll->divn_shift;
|
||
|
val |= sel.p << pll->divp_shift;
|
||
|
val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
|
||
|
pll_writel_base(val, pll);
|
||
|
}
|
||
|
|
||
|
val = pll_readl_misc(pll);
|
||
|
val |= PLLE_MISC_SETUP_VALUE;
|
||
|
val |= PLLE_MISC_LOCK_ENABLE;
|
||
|
pll_writel_misc(val, pll);
|
||
|
|
||
|
val = readl(pll->clk_base + PLLE_SS_CTRL);
|
||
|
val |= PLLE_SS_DISABLE;
|
||
|
writel(val, pll->clk_base + PLLE_SS_CTRL);
|
||
|
|
||
|
val |= pll_readl_base(pll);
|
||
|
val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
|
||
|
pll_writel_base(val, pll);
|
||
|
|
||
|
clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->misc_reg,
|
||
|
pll->params->lock_bit_idx);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
|
||
|
unsigned long parent_rate)
|
||
|
{
|
||
|
struct tegra_clk_pll *pll = to_clk_pll(hw);
|
||
|
u32 val = pll_readl_base(pll);
|
||
|
u32 divn = 0, divm = 0, divp = 0;
|
||
|
u64 rate = parent_rate;
|
||
|
|
||
|
divp = (val >> pll->divp_shift) & (divp_mask(pll));
|
||
|
divn = (val >> pll->divn_shift) & (divn_mask(pll));
|
||
|
divm = (val >> pll->divm_shift) & (divm_mask(pll));
|
||
|
divm *= divp;
|
||
|
|
||
|
rate *= divn;
|
||
|
do_div(rate, divm);
|
||
|
return rate;
|
||
|
}
|
||
|
|
||
|
const struct clk_ops tegra_clk_pll_ops = {
|
||
|
.is_enabled = clk_pll_is_enabled,
|
||
|
.enable = clk_pll_enable,
|
||
|
.disable = clk_pll_disable,
|
||
|
.recalc_rate = clk_pll_recalc_rate,
|
||
|
.round_rate = clk_pll_round_rate,
|
||
|
.set_rate = clk_pll_set_rate,
|
||
|
};
|
||
|
|
||
|
const struct clk_ops tegra_clk_plle_ops = {
|
||
|
.recalc_rate = clk_plle_recalc_rate,
|
||
|
.is_enabled = clk_pll_is_enabled,
|
||
|
.disable = clk_pll_disable,
|
||
|
.enable = clk_plle_enable,
|
||
|
};
|
||
|
|
||
|
static struct clk *_tegra_clk_register_pll(const char *name,
|
||
|
const char *parent_name, void __iomem *clk_base,
|
||
|
void __iomem *pmc, unsigned long flags,
|
||
|
unsigned long fixed_rate,
|
||
|
struct tegra_clk_pll_params *pll_params, u8 pll_flags,
|
||
|
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock,
|
||
|
const struct clk_ops *ops)
|
||
|
{
|
||
|
struct tegra_clk_pll *pll;
|
||
|
struct clk *clk;
|
||
|
struct clk_init_data init;
|
||
|
|
||
|
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||
|
if (!pll)
|
||
|
return ERR_PTR(-ENOMEM);
|
||
|
|
||
|
init.name = name;
|
||
|
init.ops = ops;
|
||
|
init.flags = flags;
|
||
|
init.parent_names = (parent_name ? &parent_name : NULL);
|
||
|
init.num_parents = (parent_name ? 1 : 0);
|
||
|
|
||
|
pll->clk_base = clk_base;
|
||
|
pll->pmc = pmc;
|
||
|
|
||
|
pll->freq_table = freq_table;
|
||
|
pll->params = pll_params;
|
||
|
pll->fixed_rate = fixed_rate;
|
||
|
pll->flags = pll_flags;
|
||
|
pll->lock = lock;
|
||
|
|
||
|
pll->divp_shift = PLL_BASE_DIVP_SHIFT;
|
||
|
pll->divp_width = PLL_BASE_DIVP_WIDTH;
|
||
|
pll->divn_shift = PLL_BASE_DIVN_SHIFT;
|
||
|
pll->divn_width = PLL_BASE_DIVN_WIDTH;
|
||
|
pll->divm_shift = PLL_BASE_DIVM_SHIFT;
|
||
|
pll->divm_width = PLL_BASE_DIVM_WIDTH;
|
||
|
|
||
|
/* Data in .init is copied by clk_register(), so stack variable OK */
|
||
|
pll->hw.init = &init;
|
||
|
|
||
|
clk = clk_register(NULL, &pll->hw);
|
||
|
if (IS_ERR(clk))
|
||
|
kfree(pll);
|
||
|
|
||
|
return clk;
|
||
|
}
|
||
|
|
||
|
struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
|
||
|
void __iomem *clk_base, void __iomem *pmc,
|
||
|
unsigned long flags, unsigned long fixed_rate,
|
||
|
struct tegra_clk_pll_params *pll_params, u8 pll_flags,
|
||
|
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
|
||
|
{
|
||
|
return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
|
||
|
flags, fixed_rate, pll_params, pll_flags, freq_table,
|
||
|
lock, &tegra_clk_pll_ops);
|
||
|
}
|
||
|
|
||
|
struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
|
||
|
void __iomem *clk_base, void __iomem *pmc,
|
||
|
unsigned long flags, unsigned long fixed_rate,
|
||
|
struct tegra_clk_pll_params *pll_params, u8 pll_flags,
|
||
|
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
|
||
|
{
|
||
|
return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
|
||
|
flags, fixed_rate, pll_params, pll_flags, freq_table,
|
||
|
lock, &tegra_clk_plle_ops);
|
||
|
}
|