linux/arch/arm/mach-hisi/Makefile

# SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for Hisilicon processors family
#

CFLAGS_platmcpm.o	:= -march=armv7-a

obj-y	+= hisilicon.o
obj-$(CONFIG_MCPM)		+= platmcpm.o
obj-$(CONFIG_SMP)		+= platsmp.o hotplug.o
treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-05-19 12:07:45 +00:00			`# SPDX-License-Identifier: GPL-2.0-only`
ARM: hi3xxx: add board support with device tree Add board support with device tree for Hisilicon Hi3620 SoC platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> [khilman: fix checkpatch errors] [khilman: fold in patch which selects GPIO in Kconfig] Signed-off-by: Kevin Hilman <khilman@linaro.org> 2013-12-11 07:54:50 +00:00			`#`
ARM: hisi: rename hi3xxx to hisi Since some new Hisilicon SoCs are not named as hi3xxx, rename mach-hi3xxx to mach-hisi instead. And the pronounciation of "hisi" is similar to the chinese pronounciation of Hisilicon. So Hisilicon guys like this name. ARCH_HI3xxx will be renamed later since other drivers are using it and they are still in linux-next git tree. So rename ARCH_HI3xxx later. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Kevin Hilman <khilman@linaro.org> 2013-12-20 02:52:56 +00:00			`# Makefile for Hisilicon processors family`
ARM: hi3xxx: add board support with device tree Add board support with device tree for Hisilicon Hi3620 SoC platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> [khilman: fix checkpatch errors] [khilman: fold in patch which selects GPIO in Kconfig] Signed-off-by: Kevin Hilman <khilman@linaro.org> 2013-12-11 07:54:50 +00:00			`#`

ARM: hisi: Fix platmcpm compilation when ARMv6 is selected When compiling with "ARCH=arm" and "allmodconfig", with commit: 9cdc99919a95e8b54c1998b65bb1bfdabd47d27b [2/7] ARM: hisi: enable MCPM implementation we will get: /tmp/cc6DjYjT.s: Assembler messages: /tmp/cc6DjYjT.s:63: Error: selected processor does not support ARM mode `ubfx r1,r0,#8,#8' /tmp/cc6DjYjT.s:761: Error: selected processor does not support ARM mode `isb ' /tmp/cc6DjYjT.s:762: Error: selected processor does not support ARM mode `dsb ' /tmp/cc6DjYjT.s:769: Error: selected processor does not support ARM mode `isb ' /tmp/cc6DjYjT.s:775: Error: selected processor does not support ARM mode `isb ' /tmp/cc6DjYjT.s:776: Error: selected processor does not support ARM mode `dsb ' /tmp/cc6DjYjT.s:795: Error: selected processor does not support ARM mode `isb ' /tmp/cc6DjYjT.s:801: Error: selected processor does not support ARM mode `isb ' /tmp/cc6DjYjT.s:802: Error: selected processor does not support ARM mode `dsb ' Fix platmcpm compilation when ARMv6 is selected. Signed-off-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Olof Johansson <olof@lixom.net> 2014-09-24 09:07:48 +00:00			`CFLAGS_platmcpm.o := -march=armv7-a`

ARM: hisi: rename hi3xxx to hisi Since some new Hisilicon SoCs are not named as hi3xxx, rename mach-hi3xxx to mach-hisi instead. And the pronounciation of "hisi" is similar to the chinese pronounciation of Hisilicon. So Hisilicon guys like this name. ARCH_HI3xxx will be renamed later since other drivers are using it and they are still in linux-next git tree. So rename ARCH_HI3xxx later. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Kevin Hilman <khilman@linaro.org> 2013-12-20 02:52:56 +00:00			`obj-y += hisilicon.o`
ARM: hisi: enable MCPM implementation Multiple CPU clusters are used in Hisilicon HiP04 SoC. Now use MCPM framework to manage power on HiP04 SoC. Changelog: v20: * Disable L2 prefetch when the whole cluster is down. * Move disabling snoop filter into power_down() after L2 prefetch disabled. * Remove delay in wait_for_power_down() after L2 prefetch disabled. * Add the sleep polling in wait_for_power_down() again since we need to wait L2 when the cluster is down. v19: * Add comments on those delay hacks. * Update on checking core enabled counts in wait_for_power_down(). v18: * Fix to release resource in probe(). * Check whether cpu is already up in the process of making cpu down. * Add udelay in power up/down sequence. * Optimize on setting relocation entry. * Optimize on polling status in wait_for_power_down(). * Add mcpm critical operations. v17: * Parse bootwrapper parameters in DTS file. * Fix to use msleep() in spinlock region. v16: * Parse bootwrapper parameters in command line instead. v13: * Restore power down operation in MCPM. * Fix disabling snoop filter issue in MCPM. v12: * Use wfi as power down state in MCPM. * Remove wait_for_powerdown() in MCPM because wfi is used now. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com> 2014-05-09 07:59:29 +00:00			`obj-$(CONFIG_MCPM) += platmcpm.o`
ARM: v7 setup function should invalidate L1 cache All ARMv5 and older CPUs invalidate their caches in the early assembly setup function, prior to enabling the MMU. This is because the L1 cache should not contain any data relevant to the execution of the kernel at this point; all data should have been flushed out to memory. This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed, these typically do not search their caches when caching is disabled (as it needs to be when the MMU is disabled) so this change should be safe. ARMv7 allows there to be CPUs which search their caches while caching is disabled, and it's permitted that the cache is uninitialised at boot; for these, the architecture reference manual requires that an implementation specific code sequence is used immediately after reset to ensure that the cache is placed into a sane state. Such functionality is definitely outside the remit of the Linux kernel, and must be done by the SoC's firmware before _any_ CPU gets to the Linux kernel. Changing the data cache clean+invalidate to a mere invalidate allows us to get rid of a lot of platform specific hacks around this issue for their secondary CPU bringup paths - some of which were buggy. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2015-05-19 16:06:44 +00:00			`obj-$(CONFIG_SMP) += platsmp.o hotplug.o`