2012-04-30 03:55:29 +00:00
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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2012-07-19 22:17:34 +00:00
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#include <core/object.h>
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#include <core/class.h>
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2012-07-04 13:44:54 +00:00
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#include <engine/fifo.h>
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2012-07-19 22:17:34 +00:00
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#include "nouveau_drm.h"
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#include "nouveau_dma.h"
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2012-04-30 03:55:29 +00:00
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#include "nouveau_fence.h"
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2012-07-31 06:16:21 +00:00
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#include "nv50_display.h"
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2012-04-30 03:55:29 +00:00
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struct nv84_fence_chan {
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struct nouveau_fence_chan base;
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};
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struct nv84_fence_priv {
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struct nouveau_fence_priv base;
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struct nouveau_gpuobj *mem;
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};
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static int
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nv84_fence_emit(struct nouveau_fence *fence)
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{
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struct nouveau_channel *chan = fence->channel;
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2012-07-19 22:17:34 +00:00
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struct nouveau_fifo_chan *fifo = (void *)chan->object;
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2012-04-30 03:55:29 +00:00
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int ret = RING_SPACE(chan, 7);
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if (ret == 0) {
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
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OUT_RING (chan, NvSema);
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BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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2012-07-19 22:17:34 +00:00
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OUT_RING (chan, upper_32_bits(fifo->chid * 16));
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OUT_RING (chan, lower_32_bits(fifo->chid * 16));
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2012-04-30 03:55:29 +00:00
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OUT_RING (chan, fence->sequence);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
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FIRE_RING (chan);
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}
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return ret;
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}
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2012-05-04 06:25:47 +00:00
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2012-04-30 03:55:29 +00:00
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static int
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2012-05-04 06:25:47 +00:00
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nv84_fence_sync(struct nouveau_fence *fence,
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struct nouveau_channel *prev, struct nouveau_channel *chan)
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2012-04-30 03:55:29 +00:00
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{
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2012-07-19 22:17:34 +00:00
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struct nouveau_fifo_chan *fifo = (void *)prev->object;
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2012-04-30 03:55:29 +00:00
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int ret = RING_SPACE(chan, 7);
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if (ret == 0) {
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
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OUT_RING (chan, NvSema);
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BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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2012-07-19 22:17:34 +00:00
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OUT_RING (chan, upper_32_bits(fifo->chid * 16));
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OUT_RING (chan, lower_32_bits(fifo->chid * 16));
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2012-04-30 03:55:29 +00:00
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OUT_RING (chan, fence->sequence);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
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FIRE_RING (chan);
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}
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return ret;
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}
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static u32
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nv84_fence_read(struct nouveau_channel *chan)
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{
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2012-07-19 22:17:34 +00:00
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struct nouveau_fifo_chan *fifo = (void *)chan->object;
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struct nv84_fence_priv *priv = chan->drm->fence;
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return nv_ro32(priv->mem, fifo->chid * 16);
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2012-04-30 03:55:29 +00:00
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}
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static void
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2012-07-19 00:51:42 +00:00
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nv84_fence_context_del(struct nouveau_channel *chan)
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2012-04-30 03:55:29 +00:00
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{
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2012-07-19 00:51:42 +00:00
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struct nv84_fence_chan *fctx = chan->fence;
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2012-04-30 03:55:29 +00:00
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nouveau_fence_context_del(&fctx->base);
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2012-07-19 00:51:42 +00:00
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chan->fence = NULL;
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2012-04-30 03:55:29 +00:00
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kfree(fctx);
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}
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static int
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2012-07-19 00:51:42 +00:00
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nv84_fence_context_new(struct nouveau_channel *chan)
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2012-04-30 03:55:29 +00:00
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{
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2012-07-31 06:16:21 +00:00
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struct drm_device *dev = chan->drm->dev;
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2012-07-19 22:17:34 +00:00
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struct nouveau_fifo_chan *fifo = (void *)chan->object;
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struct nv84_fence_priv *priv = chan->drm->fence;
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2012-04-30 03:55:29 +00:00
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struct nv84_fence_chan *fctx;
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2012-07-19 22:17:34 +00:00
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struct nouveau_object *object;
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2012-07-22 01:55:54 +00:00
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int ret, i;
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2012-04-30 03:55:29 +00:00
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2012-07-19 00:51:42 +00:00
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fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
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2012-04-30 03:55:29 +00:00
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if (!fctx)
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return -ENOMEM;
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nouveau_fence_context_new(&fctx->base);
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2012-07-19 22:17:34 +00:00
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ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
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NvSema, 0x0002,
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&(struct nv_dma_class) {
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.flags = NV_DMA_TARGET_VRAM |
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NV_DMA_ACCESS_RDWR,
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.start = priv->mem->addr,
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.limit = priv->mem->addr +
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priv->mem->size - 1,
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}, sizeof(struct nv_dma_class),
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&object);
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2012-04-30 03:55:29 +00:00
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2012-07-22 01:55:54 +00:00
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/* dma objects for display sync channel semaphore blocks */
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2012-07-31 06:16:21 +00:00
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for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
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struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
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2012-07-19 22:17:34 +00:00
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ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
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NvEvoSema0 + i, 0x003d,
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&(struct nv_dma_class) {
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.flags = NV_DMA_TARGET_VRAM |
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NV_DMA_ACCESS_RDWR,
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.start = bo->bo.offset,
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.limit = bo->bo.offset + 0xfff,
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}, sizeof(struct nv_dma_class),
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&object);
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2012-07-22 01:55:54 +00:00
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}
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2012-04-30 03:55:29 +00:00
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if (ret)
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2012-07-19 00:51:42 +00:00
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nv84_fence_context_del(chan);
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2012-07-19 22:17:34 +00:00
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nv_wo32(priv->mem, fifo->chid * 16, 0x00000000);
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2012-04-30 03:55:29 +00:00
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return ret;
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}
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static void
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2012-07-19 22:17:34 +00:00
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nv84_fence_destroy(struct nouveau_drm *drm)
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2012-04-30 03:55:29 +00:00
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{
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2012-07-19 22:17:34 +00:00
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struct nv84_fence_priv *priv = drm->fence;
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2012-04-30 03:55:29 +00:00
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nouveau_gpuobj_ref(NULL, &priv->mem);
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2012-07-19 22:17:34 +00:00
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drm->fence = NULL;
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2012-04-30 03:55:29 +00:00
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kfree(priv);
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}
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int
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2012-07-19 22:17:34 +00:00
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nv84_fence_create(struct nouveau_drm *drm)
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2012-04-30 03:55:29 +00:00
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{
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2012-07-19 22:17:34 +00:00
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struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
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2012-04-30 03:55:29 +00:00
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struct nv84_fence_priv *priv;
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2012-07-19 22:17:34 +00:00
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u32 chan = pfifo->max + 1;
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2012-04-30 03:55:29 +00:00
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int ret;
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2012-07-19 22:17:34 +00:00
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priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
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2012-04-30 03:55:29 +00:00
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if (!priv)
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return -ENOMEM;
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2012-07-19 00:51:42 +00:00
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priv->base.dtor = nv84_fence_destroy;
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priv->base.context_new = nv84_fence_context_new;
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priv->base.context_del = nv84_fence_context_del;
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2012-04-30 03:55:29 +00:00
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priv->base.emit = nv84_fence_emit;
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priv->base.sync = nv84_fence_sync;
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priv->base.read = nv84_fence_read;
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2012-07-19 22:17:34 +00:00
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ret = nouveau_gpuobj_new(drm->device, NULL, chan * 16, 0x1000, 0,
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&priv->mem);
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2012-04-30 03:55:29 +00:00
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if (ret)
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2012-07-19 22:17:34 +00:00
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nv84_fence_destroy(drm);
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2012-04-30 03:55:29 +00:00
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return ret;
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}
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