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linux/arch/arm/boot/dts/qcom-msm8660-surf.dts

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ARM: msm: Add devicetree support for msm8660-surf Adds support for booting via device tree with a simple serial console. Change-Id: I7f175b8db21928cd13e0fb49f3eed74966a2696f Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-08-04 09:01:02 +00:00
/dts-v1/;
/include/ "skeleton.dtsi"
/ {
model = "Qualcomm MSM8660 SURF";
compatible = "qcom,msm8660-surf", "qcom,msm8660";
interrupt-parent = <&intc>;
ARM: msm: Move 8660 to DT timer Add the timer entry and point the machine descriptor to the device tree based msm timer. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [davidb@codeaurora.org: Remove leading zeros] Signed-off-by: David Brown <davidb@codeaurora.org>
2012-09-05 19:28:54 +00:00
intc: interrupt-controller@2080000 {
ARM: msm: Add devicetree support for msm8660-surf Adds support for booting via device tree with a simple serial console. Change-Id: I7f175b8db21928cd13e0fb49f3eed74966a2696f Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-08-04 09:01:02 +00:00
compatible = "qcom,msm-8660-qgic";
interrupt-controller;
ARM: msm: Fix gic irqdomain support As of commit 75294957be1dee7d22dd7d90bd31334ba410e836 Author: Grant Likely <grant.likely@secretlab.ca> Date: Tue Feb 14 14:06:57 2012 -0700 irq_domain: Remove 'new' irq_domain in favour of the ppc one the ARM gic controller uses proper irq domains. Fix the MSM gic initialization and DT so that it works again. Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Grant Likely <grant.likely@secretlab.ca>
2012-04-23 22:34:20 +00:00
#interrupt-cells = <3>;
ARM: msm: Add devicetree support for msm8660-surf Adds support for booting via device tree with a simple serial console. Change-Id: I7f175b8db21928cd13e0fb49f3eed74966a2696f Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-08-04 09:01:02 +00:00
reg = < 0x02080000 0x1000 >,
< 0x02081000 0x1000 >;
};
ARM: dts: msm: Fix bad register addresses Some bad copy/paste got in as well as too many zeroes. Fix everything up so that the registers after the @ sign are consistent with the first reg property. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-05-21 00:50:37 +00:00
timer@2000000 {
ARM: msm: Rework timer binding to be more general The msm timer binding I wrote is bad. First off, the clock frequency in the binding for the dgt is wrong. Software divides down the input rate by 4 to achieve the rate listed in the binding. We also treat each individual timer as a separate hardware component, when in reality there is one timer block (that may be duplicated per cpu) with multiple timers within it. Depending on the version of the hardware there can be one or two general purpose timers, status and divider control registers, and an entirely different register layout. In the next patch we'll need to know about the different register layouts so that we can properly check the status register after clearing the count. The current binding makes this complicated because the general purpose timer's reg property doesn't indicate where that status register is, and in fact it is beyond the size of the reg property. Clean all this up by just having one node for the timer hardware, and describe all the interrupts and clock frequencies supported while having one reg property that covers the entire timer register region. We'll use the compatible field in the future to determine different register layouts and if we should read the status registers, etc. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-03-15 03:31:38 +00:00
compatible = "qcom,scss-timer", "qcom,msm-timer";
interrupts = <1 0 0x301>,
<1 1 0x301>,
<1 2 0x301>;
reg = <0x02000000 0x100>;
clock-frequency = <27000000>,
<32768>;
ARM: msm: Move 8660 to DT timer Add the timer entry and point the machine descriptor to the device tree based msm timer. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [davidb@codeaurora.org: Remove leading zeros] Signed-off-by: David Brown <davidb@codeaurora.org>
2012-09-05 19:28:54 +00:00
cpu-offset = <0x40000>;
};
gpio: msm: Add device tree and irqdomain support for gpio-msm-v2 This cleans up the gpio-msm-v2 driver of all the global define usage. The number of gpios are now defined in the device tree. This enables adding irqdomain support as well. Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> Acked-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-06-10 22:50:21 +00:00
msmgpio: gpio@800000 {
compatible = "qcom,msm-gpio";
ARM: dts: msm: Fix gpio interrupt and reg length The summary interrupt is #16 in the SPI space. Unfortunately, when this device was translated from board files to DT we forgot to subtract 16 from the interrupt number to translate it into a SPI interrupt. Also, the register space is larger than 4k, increase it appropriately so that the gpio driver doesn't try to access registers outside of its mapping. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-12-10 23:14:43 +00:00
reg = <0x00800000 0x4000>;
gpio: msm: Add device tree and irqdomain support for gpio-msm-v2 This cleans up the gpio-msm-v2 driver of all the global define usage. The number of gpios are now defined in the device tree. This enables adding irqdomain support as well. Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> Acked-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-06-10 22:50:21 +00:00
gpio-controller;
#gpio-cells = <2>;
ngpio = <173>;
ARM: dts: msm: Fix gpio interrupt and reg length The summary interrupt is #16 in the SPI space. Unfortunately, when this device was translated from board files to DT we forgot to subtract 16 from the interrupt number to translate it into a SPI interrupt. Also, the register space is larger than 4k, increase it appropriately so that the gpio driver doesn't try to access registers outside of its mapping. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-12-10 23:14:43 +00:00
interrupts = <0 16 0x4>;
gpio: msm: Add device tree and irqdomain support for gpio-msm-v2 This cleans up the gpio-msm-v2 driver of all the global define usage. The number of gpios are now defined in the device tree. This enables adding irqdomain support as well. Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> Acked-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-06-10 22:50:21 +00:00
interrupt-controller;
#interrupt-cells = <2>;
};
ARM: dts: msm: Fix bad register addresses Some bad copy/paste got in as well as too many zeroes. Fix everything up so that the registers after the @ sign are consistent with the first reg property. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-05-21 00:50:37 +00:00
serial@19c40000 {
ARM: dts: msm: Update uartdm compatible strings Let's follow the ratified DT binding and use uartdm instead of hsuart. This does break backwards compatibility but this shouldn't be a problem because the uart driver isn't probing on these devices without adding clock support (which isn't merged so far). Cc: David Brown <davidb@codeaurora.org> Acked-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-08-28 20:32:41 +00:00
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
ARM: msm: Add devicetree support for msm8660-surf Adds support for booting via device tree with a simple serial console. Change-Id: I7f175b8db21928cd13e0fb49f3eed74966a2696f Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-08-04 09:01:02 +00:00
reg = <0x19c40000 0x1000>,
<0x19c00000 0x1000>;
ARM: msm: Fix gic irqdomain support As of commit 75294957be1dee7d22dd7d90bd31334ba410e836 Author: Grant Likely <grant.likely@secretlab.ca> Date: Tue Feb 14 14:06:57 2012 -0700 irq_domain: Remove 'new' irq_domain in favour of the ppc one the ARM gic controller uses proper irq domains. Fix the MSM gic initialization and DT so that it works again. Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Grant Likely <grant.likely@secretlab.ca>
2012-04-23 22:34:20 +00:00
interrupts = <0 195 0x0>;
ARM: msm: Add devicetree support for msm8660-surf Adds support for booting via device tree with a simple serial console. Change-Id: I7f175b8db21928cd13e0fb49f3eed74966a2696f Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-08-04 09:01:02 +00:00
};
SSBI: Convert SSBI to device tree The SSBI bus is exclusive to the Qualcomm MSM targets, and all SoCs using it will be using device tree. Convert this driver to indentify with device tree. This makes the bus probing a good bit simpler, since the attaching of child nodes can be represented directly in the devicetree, rather than having to be inferred by name. Signed-off-by: David Brown <davidb@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-03-12 18:41:50 +00:00
qcom,ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
};
ARM: msm: Add devicetree support for msm8660-surf Adds support for booting via device tree with a simple serial console. Change-Id: I7f175b8db21928cd13e0fb49f3eed74966a2696f Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-08-04 09:01:02 +00:00
};
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