forked from Minki/linux
185 lines
4.1 KiB
C
185 lines
4.1 KiB
C
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/*
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mv_64xx.c - Marvell 88SE6440 SAS/SATA support
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Copyright 2007 Red Hat, Inc.
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Copyright 2008 Marvell. <kewei@marvell.com>
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2,
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or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty
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of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public
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License along with this program; see the file COPYING. If not,
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write to the Free Software Foundation, 675 Mass Ave, Cambridge,
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MA 02139, USA.
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*/
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#include "mv_sas.h"
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#include "mv_64xx.h"
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#include "mv_chips.h"
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void mvs_detect_porttype(struct mvs_info *mvi, int i)
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{
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void __iomem *regs = mvi->regs;
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u32 reg;
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struct mvs_phy *phy = &mvi->phy[i];
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/* TODO check & save device type */
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reg = mr32(GBL_PORT_TYPE);
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if (reg & MODE_SAS_SATA & (1 << i))
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phy->phy_type |= PORT_TYPE_SAS;
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else
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phy->phy_type |= PORT_TYPE_SATA;
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}
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void mvs_enable_xmt(struct mvs_info *mvi, int PhyId)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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tmp = mr32(PCS);
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if (mvi->chip->n_phy <= 4)
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tmp |= 1 << (PhyId + PCS_EN_PORT_XMT_SHIFT);
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else
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tmp |= 1 << (PhyId + PCS_EN_PORT_XMT_SHIFT2);
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mw32(PCS, tmp);
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}
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void __devinit mvs_phy_hacks(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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/* workaround for SATA R-ERR, to ignore phy glitch */
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tmp = mvs_cr32(regs, CMD_PHY_TIMER);
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tmp &= ~(1 << 9);
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tmp |= (1 << 10);
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mvs_cw32(regs, CMD_PHY_TIMER, tmp);
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/* enable retry 127 times */
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mvs_cw32(regs, CMD_SAS_CTL1, 0x7f7f);
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/* extend open frame timeout to max */
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tmp = mvs_cr32(regs, CMD_SAS_CTL0);
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tmp &= ~0xffff;
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tmp |= 0x3fff;
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mvs_cw32(regs, CMD_SAS_CTL0, tmp);
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/* workaround for WDTIMEOUT , set to 550 ms */
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mvs_cw32(regs, CMD_WD_TIMER, 0x86470);
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/* not to halt for different port op during wideport link change */
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mvs_cw32(regs, CMD_APP_ERR_CONFIG, 0xffefbf7d);
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/* workaround for Seagate disk not-found OOB sequence, recv
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* COMINIT before sending out COMWAKE */
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tmp = mvs_cr32(regs, CMD_PHY_MODE_21);
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tmp &= 0x0000ffff;
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tmp |= 0x00fa0000;
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mvs_cw32(regs, CMD_PHY_MODE_21, tmp);
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tmp = mvs_cr32(regs, CMD_PHY_TIMER);
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tmp &= 0x1fffffff;
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tmp |= (2U << 29); /* 8 ms retry */
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mvs_cw32(regs, CMD_PHY_TIMER, tmp);
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/* TEST - for phy decoding error, adjust voltage levels */
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mw32(P0_VSR_ADDR + 0, 0x8);
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mw32(P0_VSR_DATA + 0, 0x2F0);
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mw32(P0_VSR_ADDR + 8, 0x8);
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mw32(P0_VSR_DATA + 8, 0x2F0);
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mw32(P0_VSR_ADDR + 16, 0x8);
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mw32(P0_VSR_DATA + 16, 0x2F0);
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mw32(P0_VSR_ADDR + 24, 0x8);
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mw32(P0_VSR_DATA + 24, 0x2F0);
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}
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void mvs_hba_interrupt_enable(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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tmp = mr32(GBL_CTL);
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mw32(GBL_CTL, tmp | INT_EN);
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}
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void mvs_hba_interrupt_disable(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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tmp = mr32(GBL_CTL);
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mw32(GBL_CTL, tmp & ~INT_EN);
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}
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void mvs_free_reg_set(struct mvs_info *mvi, struct mvs_port *port)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp, offs;
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u8 *tfs = &port->taskfileset;
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if (*tfs == MVS_ID_NOT_MAPPED)
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return;
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offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT);
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if (*tfs < 16) {
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tmp = mr32(PCS);
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mw32(PCS, tmp & ~offs);
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} else {
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tmp = mr32(CTL);
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mw32(CTL, tmp & ~offs);
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}
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tmp = mr32(INT_STAT_SRS) & (1U << *tfs);
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if (tmp)
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mw32(INT_STAT_SRS, tmp);
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*tfs = MVS_ID_NOT_MAPPED;
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}
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u8 mvs_assign_reg_set(struct mvs_info *mvi, struct mvs_port *port)
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{
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int i;
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u32 tmp, offs;
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void __iomem *regs = mvi->regs;
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if (port->taskfileset != MVS_ID_NOT_MAPPED)
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return 0;
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tmp = mr32(PCS);
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for (i = 0; i < mvi->chip->srs_sz; i++) {
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if (i == 16)
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tmp = mr32(CTL);
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offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT);
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if (!(tmp & offs)) {
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port->taskfileset = i;
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if (i < 16)
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mw32(PCS, tmp | offs);
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else
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mw32(CTL, tmp | offs);
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tmp = mr32(INT_STAT_SRS) & (1U << i);
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if (tmp)
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mw32(INT_STAT_SRS, tmp);
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return 0;
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}
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}
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return MVS_ID_NOT_MAPPED;
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}
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