2014-01-23 20:44:44 +00:00
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Broadcom BCM281xx Pin Controller
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2013-12-21 02:13:34 +00:00
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This is a pin controller for the Broadcom BCM281xx SoC family, which includes
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BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs.
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=== Pin Controller Node ===
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Required Properties:
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2014-01-23 20:44:44 +00:00
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- compatible: Must be "brcm,bcm11351-pinctrl"
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2013-12-21 02:13:34 +00:00
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- reg: Base address of the PAD Controller register block and the size
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of the block.
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For example, the following is the bare minimum node:
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pinctrl@35004800 {
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2014-01-23 20:44:44 +00:00
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compatible = "brcm,bcm11351-pinctrl";
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2013-12-21 02:13:34 +00:00
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reg = <0x35004800 0x430>;
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};
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As a pin controller device, in addition to the required properties, this node
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should also contain the pin configuration nodes that client devices reference,
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if any.
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=== Pin Configuration Node ===
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Each pin configuration node is a sub-node of the pin controller node and is a
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container of an arbitrary number of subnodes, called pin group nodes in this
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document.
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Please refer to the pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the definition of a
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"pin configuration node".
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=== Pin Group Node ===
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A pin group node specifies the desired pin mux and/or pin configuration for an
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arbitrary number of pins. The name of the pin group node is optional and not
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used.
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A pin group node only affects the properties specified in the node, and has no
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effect on any properties that are omitted.
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The pin group node accepts a subset of the generic pin config properties. For
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details generic pin config properties, please refer to pinctrl-bindings.txt
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and <include/linux/pinctrl/pinconfig-generic.h>.
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Each pin controlled by this pin controller belong to one of three types:
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Standard, I2C, and HDMI. Each type accepts a different set of pin config
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properties. A list of pins and their types is provided below.
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Required Properties (applicable to all pins):
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- pins: Multiple strings. Specifies the name(s) of one or more pins to
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be configured by this node.
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Optional Properties (for standard pins):
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- function: String. Specifies the pin mux selection. Values
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must be one of: "alt1", "alt2", "alt3", "alt4"
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- input-schmitt-enable: No arguments. Enable schmitt-trigger mode.
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- input-schmitt-disable: No arguments. Disable schmitt-trigger mode.
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- bias-pull-up: No arguments. Pull up on pin.
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- bias-pull-down: No arguments. Pull down on pin.
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- bias-disable: No arguments. Disable pin bias.
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- slew-rate: Integer. Meaning depends on configured pin mux:
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*_SCL or *_SDA:
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0: Standard(100kbps)& Fast(400kbps) mode
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1: Highspeed (3.4Mbps) mode
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IC_DM or IC_DP:
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0: normal slew rate
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1: fast slew rate
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Otherwise:
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0: fast slew rate
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1: normal slew rate
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2014-04-05 02:31:00 +00:00
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- input-enable: No arguments. Enable input (does not affect
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2013-12-21 02:13:34 +00:00
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output.)
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2014-04-05 02:31:00 +00:00
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- input-disable: No arguments. Disable input (does not affect
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2013-12-21 02:13:34 +00:00
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output.)
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- drive-strength: Integer. Drive strength in mA. Valid values are
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2, 4, 6, 8, 10, 12, 14, 16 mA.
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Optional Properties (for I2C pins):
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- function: String. Specifies the pin mux selection. Values
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must be one of: "alt1", "alt2", "alt3", "alt4"
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- bias-pull-up: Integer. Pull up strength in Ohm. There are 3
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pull-up resisitors (1.2k, 1.8k, 2.7k) available
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in parallel for I2C pins, so the valid values
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are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm.
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- bias-disable: No arguments. Disable pin bias.
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- slew-rate: Integer. Meaning depends on configured pin mux:
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*_SCL or *_SDA:
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0: Standard(100kbps)& Fast(400kbps) mode
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1: Highspeed (3.4Mbps) mode
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IC_DM or IC_DP:
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0: normal slew rate
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1: fast slew rate
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Otherwise:
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0: fast slew rate
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1: normal slew rate
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2014-04-05 02:31:00 +00:00
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- input-enable: No arguments. Enable input (does not affect
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2013-12-21 02:13:34 +00:00
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output.)
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2014-04-05 02:31:00 +00:00
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- input-disable: No arguments. Disable input (does not affect
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2013-12-21 02:13:34 +00:00
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output.)
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Optional Properties (for HDMI pins):
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- function: String. Specifies the pin mux selection. Values
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must be one of: "alt1", "alt2", "alt3", "alt4"
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- slew-rate: Integer. Controls slew rate.
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0: Standard(100kbps)& Fast(400kbps) mode
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1: Highspeed (3.4Mbps) mode
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2014-04-05 02:31:00 +00:00
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- input-enable: No arguments. Enable input (does not affect
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2013-12-21 02:13:34 +00:00
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output.)
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2014-04-05 02:31:00 +00:00
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- input-disable: No arguments. Disable input (does not affect
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2013-12-21 02:13:34 +00:00
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output.)
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Example:
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// pin controller node
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pinctrl@35004800 {
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2014-04-02 22:40:39 +00:00
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compatible = "brcm,bcm11351-pinctrl";
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2013-12-21 02:13:34 +00:00
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reg = <0x35004800 0x430>;
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// pin configuration node
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dev_a_default: dev_a_active {
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//group node defining 1 standard pin
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grp_1 {
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pins = "std_pin1";
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function = "alt1";
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input-schmitt-enable;
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bias-disable;
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slew-rate = <1>;
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drive-strength = <4>;
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};
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// group node defining 2 I2C pins
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grp_2 {
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pins = "i2c_pin1", "i2c_pin2";
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function = "alt2";
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bias-pull-up = <720>;
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input-enable;
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};
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// group node defining 2 HDMI pins
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grp_3 {
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pins = "hdmi_pin1", "hdmi_pin2";
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function = "alt3";
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slew-rate = <1>;
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};
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// other pin group nodes
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...
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};
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// other pin configuration nodes
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...
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};
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In the example above, "dev_a_active" is a pin configuration node with a number
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of sub-nodes. In the pin group node "grp_1", one pin, "std_pin1", is defined in
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the "pins" property. Thus, the remaining properties in the "grp_1" node applies
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only to this pin, including the following settings:
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- setting pinmux to "alt1"
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- enabling schmitt-trigger (hystersis) mode
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- disabling pin bias
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- setting the slew-rate to 1
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- setting the drive strength to 4 mA
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Note that neither "input-enable" nor "input-disable" was specified - the pinctrl
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subsystem will therefore leave this property unchanged from whatever state it
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was in before applying these changes.
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The "pins" property in the pin group node "grp_2" specifies two pins -
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"i2c_pin1" and "i2c_pin2"; the remaining properties in this pin group node,
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therefore, applies to both of these pins. The properties include:
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- setting pinmux to "alt2"
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- setting pull-up resistance to 720 Ohm (ie. enabling 1.2k and 1.8k resistors
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in parallel)
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- enabling both pins' input
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"slew-rate" is not specified in this pin group node, so the slew-rate for these
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pins are left as-is.
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Finally, "grp_3" defines two HDMI pins. The following properties are applied to
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both pins:
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- setting pinmux to "alt3"
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- setting slew-rate to 1; for HDMI pins, this corresponds to the 3.4 Mbps
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Highspeed mode
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The input is neither enabled or disabled, and is left untouched.
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=== Pin Names and Type ===
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The following are valid pin names and their pin types:
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"adcsync", Standard
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"bat_rm", Standard
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"bsc1_scl", I2C
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"bsc1_sda", I2C
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"bsc2_scl", I2C
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"bsc2_sda", I2C
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"classgpwr", Standard
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"clk_cx8", Standard
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"clkout_0", Standard
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"clkout_1", Standard
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"clkout_2", Standard
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"clkout_3", Standard
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"clkreq_in_0", Standard
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"clkreq_in_1", Standard
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"cws_sys_req1", Standard
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"cws_sys_req2", Standard
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"cws_sys_req3", Standard
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"digmic1_clk", Standard
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"digmic1_dq", Standard
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"digmic2_clk", Standard
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"digmic2_dq", Standard
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"gpen13", Standard
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"gpen14", Standard
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"gpen15", Standard
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"gpio00", Standard
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"gpio01", Standard
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"gpio02", Standard
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"gpio03", Standard
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"gpio04", Standard
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"gpio05", Standard
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"gpio06", Standard
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"gpio07", Standard
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"gpio08", Standard
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"gpio09", Standard
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"gpio10", Standard
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"gpio11", Standard
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"gpio12", Standard
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"gpio13", Standard
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"gpio14", Standard
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"gps_pablank", Standard
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"gps_tmark", Standard
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"hdmi_scl", HDMI
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"hdmi_sda", HDMI
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"ic_dm", Standard
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"ic_dp", Standard
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"kp_col_ip_0", Standard
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"kp_col_ip_1", Standard
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"kp_col_ip_2", Standard
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"kp_col_ip_3", Standard
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"kp_row_op_0", Standard
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"kp_row_op_1", Standard
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"kp_row_op_2", Standard
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"kp_row_op_3", Standard
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"lcd_b_0", Standard
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"lcd_b_1", Standard
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"lcd_b_2", Standard
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"lcd_b_3", Standard
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"lcd_b_4", Standard
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"lcd_b_5", Standard
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"lcd_b_6", Standard
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"lcd_b_7", Standard
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"lcd_g_0", Standard
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"lcd_g_1", Standard
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"lcd_g_2", Standard
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"lcd_g_3", Standard
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"lcd_g_4", Standard
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"lcd_g_5", Standard
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"lcd_g_6", Standard
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"lcd_g_7", Standard
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"lcd_hsync", Standard
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"lcd_oe", Standard
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"lcd_pclk", Standard
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"lcd_r_0", Standard
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"lcd_r_1", Standard
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"lcd_r_2", Standard
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"lcd_r_3", Standard
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"lcd_r_4", Standard
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"lcd_r_5", Standard
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"lcd_r_6", Standard
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"lcd_r_7", Standard
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"lcd_vsync", Standard
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"mdmgpio0", Standard
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"mdmgpio1", Standard
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"mdmgpio2", Standard
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"mdmgpio3", Standard
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"mdmgpio4", Standard
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"mdmgpio5", Standard
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"mdmgpio6", Standard
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"mdmgpio7", Standard
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"mdmgpio8", Standard
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"mphi_data_0", Standard
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"mphi_data_1", Standard
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"mphi_data_2", Standard
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"mphi_data_3", Standard
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"mphi_data_4", Standard
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"mphi_data_5", Standard
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"mphi_data_6", Standard
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"mphi_data_7", Standard
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"mphi_data_8", Standard
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"mphi_data_9", Standard
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"mphi_data_10", Standard
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"mphi_data_11", Standard
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"mphi_data_12", Standard
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"mphi_data_13", Standard
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"mphi_data_14", Standard
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"mphi_data_15", Standard
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"mphi_ha0", Standard
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"mphi_hat0", Standard
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"mphi_hat1", Standard
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"mphi_hce0_n", Standard
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"mphi_hce1_n", Standard
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"mphi_hrd_n", Standard
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"mphi_hwr_n", Standard
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"mphi_run0", Standard
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"mphi_run1", Standard
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"mtx_scan_clk", Standard
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"mtx_scan_data", Standard
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"nand_ad_0", Standard
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"nand_ad_1", Standard
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"nand_ad_2", Standard
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"nand_ad_3", Standard
|
|
|
|
|
"nand_ad_4", Standard
|
|
|
|
|
"nand_ad_5", Standard
|
|
|
|
|
"nand_ad_6", Standard
|
|
|
|
|
"nand_ad_7", Standard
|
|
|
|
|
"nand_ale", Standard
|
|
|
|
|
"nand_cen_0", Standard
|
|
|
|
|
"nand_cen_1", Standard
|
|
|
|
|
"nand_cle", Standard
|
|
|
|
|
"nand_oen", Standard
|
|
|
|
|
"nand_rdy_0", Standard
|
|
|
|
|
"nand_rdy_1", Standard
|
|
|
|
|
"nand_wen", Standard
|
|
|
|
|
"nand_wp", Standard
|
|
|
|
|
"pc1", Standard
|
|
|
|
|
"pc2", Standard
|
|
|
|
|
"pmu_int", Standard
|
|
|
|
|
"pmu_scl", I2C
|
|
|
|
|
"pmu_sda", I2C
|
|
|
|
|
"rfst2g_mtsloten3g", Standard
|
|
|
|
|
"rgmii_0_rx_ctl", Standard
|
|
|
|
|
"rgmii_0_rxc", Standard
|
|
|
|
|
"rgmii_0_rxd_0", Standard
|
|
|
|
|
"rgmii_0_rxd_1", Standard
|
|
|
|
|
"rgmii_0_rxd_2", Standard
|
|
|
|
|
"rgmii_0_rxd_3", Standard
|
|
|
|
|
"rgmii_0_tx_ctl", Standard
|
|
|
|
|
"rgmii_0_txc", Standard
|
|
|
|
|
"rgmii_0_txd_0", Standard
|
|
|
|
|
"rgmii_0_txd_1", Standard
|
|
|
|
|
"rgmii_0_txd_2", Standard
|
|
|
|
|
"rgmii_0_txd_3", Standard
|
|
|
|
|
"rgmii_1_rx_ctl", Standard
|
|
|
|
|
"rgmii_1_rxc", Standard
|
|
|
|
|
"rgmii_1_rxd_0", Standard
|
|
|
|
|
"rgmii_1_rxd_1", Standard
|
|
|
|
|
"rgmii_1_rxd_2", Standard
|
|
|
|
|
"rgmii_1_rxd_3", Standard
|
|
|
|
|
"rgmii_1_tx_ctl", Standard
|
|
|
|
|
"rgmii_1_txc", Standard
|
|
|
|
|
"rgmii_1_txd_0", Standard
|
|
|
|
|
"rgmii_1_txd_1", Standard
|
|
|
|
|
"rgmii_1_txd_2", Standard
|
|
|
|
|
"rgmii_1_txd_3", Standard
|
|
|
|
|
"rgmii_gpio_0", Standard
|
|
|
|
|
"rgmii_gpio_1", Standard
|
|
|
|
|
"rgmii_gpio_2", Standard
|
|
|
|
|
"rgmii_gpio_3", Standard
|
|
|
|
|
"rtxdata2g_txdata3g1", Standard
|
|
|
|
|
"rtxen2g_txdata3g2", Standard
|
|
|
|
|
"rxdata3g0", Standard
|
|
|
|
|
"rxdata3g1", Standard
|
|
|
|
|
"rxdata3g2", Standard
|
|
|
|
|
"sdio1_clk", Standard
|
|
|
|
|
"sdio1_cmd", Standard
|
|
|
|
|
"sdio1_data_0", Standard
|
|
|
|
|
"sdio1_data_1", Standard
|
|
|
|
|
"sdio1_data_2", Standard
|
|
|
|
|
"sdio1_data_3", Standard
|
|
|
|
|
"sdio4_clk", Standard
|
|
|
|
|
"sdio4_cmd", Standard
|
|
|
|
|
"sdio4_data_0", Standard
|
|
|
|
|
"sdio4_data_1", Standard
|
|
|
|
|
"sdio4_data_2", Standard
|
|
|
|
|
"sdio4_data_3", Standard
|
|
|
|
|
"sim_clk", Standard
|
|
|
|
|
"sim_data", Standard
|
|
|
|
|
"sim_det", Standard
|
|
|
|
|
"sim_resetn", Standard
|
|
|
|
|
"sim2_clk", Standard
|
|
|
|
|
"sim2_data", Standard
|
|
|
|
|
"sim2_det", Standard
|
|
|
|
|
"sim2_resetn", Standard
|
|
|
|
|
"sri_c", Standard
|
|
|
|
|
"sri_d", Standard
|
|
|
|
|
"sri_e", Standard
|
|
|
|
|
"ssp_extclk", Standard
|
|
|
|
|
"ssp0_clk", Standard
|
|
|
|
|
"ssp0_fs", Standard
|
|
|
|
|
"ssp0_rxd", Standard
|
|
|
|
|
"ssp0_txd", Standard
|
|
|
|
|
"ssp2_clk", Standard
|
|
|
|
|
"ssp2_fs_0", Standard
|
|
|
|
|
"ssp2_fs_1", Standard
|
|
|
|
|
"ssp2_fs_2", Standard
|
|
|
|
|
"ssp2_fs_3", Standard
|
|
|
|
|
"ssp2_rxd_0", Standard
|
|
|
|
|
"ssp2_rxd_1", Standard
|
|
|
|
|
"ssp2_txd_0", Standard
|
|
|
|
|
"ssp2_txd_1", Standard
|
|
|
|
|
"ssp3_clk", Standard
|
|
|
|
|
"ssp3_fs", Standard
|
|
|
|
|
"ssp3_rxd", Standard
|
|
|
|
|
"ssp3_txd", Standard
|
|
|
|
|
"ssp4_clk", Standard
|
|
|
|
|
"ssp4_fs", Standard
|
|
|
|
|
"ssp4_rxd", Standard
|
|
|
|
|
"ssp4_txd", Standard
|
|
|
|
|
"ssp5_clk", Standard
|
|
|
|
|
"ssp5_fs", Standard
|
|
|
|
|
"ssp5_rxd", Standard
|
|
|
|
|
"ssp5_txd", Standard
|
|
|
|
|
"ssp6_clk", Standard
|
|
|
|
|
"ssp6_fs", Standard
|
|
|
|
|
"ssp6_rxd", Standard
|
|
|
|
|
"ssp6_txd", Standard
|
|
|
|
|
"stat_1", Standard
|
|
|
|
|
"stat_2", Standard
|
|
|
|
|
"sysclken", Standard
|
|
|
|
|
"traceclk", Standard
|
|
|
|
|
"tracedt00", Standard
|
|
|
|
|
"tracedt01", Standard
|
|
|
|
|
"tracedt02", Standard
|
|
|
|
|
"tracedt03", Standard
|
|
|
|
|
"tracedt04", Standard
|
|
|
|
|
"tracedt05", Standard
|
|
|
|
|
"tracedt06", Standard
|
|
|
|
|
"tracedt07", Standard
|
|
|
|
|
"tracedt08", Standard
|
|
|
|
|
"tracedt09", Standard
|
|
|
|
|
"tracedt10", Standard
|
|
|
|
|
"tracedt11", Standard
|
|
|
|
|
"tracedt12", Standard
|
|
|
|
|
"tracedt13", Standard
|
|
|
|
|
"tracedt14", Standard
|
|
|
|
|
"tracedt15", Standard
|
|
|
|
|
"txdata3g0", Standard
|
|
|
|
|
"txpwrind", Standard
|
|
|
|
|
"uartb1_ucts", Standard
|
|
|
|
|
"uartb1_urts", Standard
|
|
|
|
|
"uartb1_urxd", Standard
|
|
|
|
|
"uartb1_utxd", Standard
|
|
|
|
|
"uartb2_urxd", Standard
|
|
|
|
|
"uartb2_utxd", Standard
|
|
|
|
|
"uartb3_ucts", Standard
|
|
|
|
|
"uartb3_urts", Standard
|
|
|
|
|
"uartb3_urxd", Standard
|
|
|
|
|
"uartb3_utxd", Standard
|
|
|
|
|
"uartb4_ucts", Standard
|
|
|
|
|
"uartb4_urts", Standard
|
|
|
|
|
"uartb4_urxd", Standard
|
|
|
|
|
"uartb4_utxd", Standard
|
|
|
|
|
"vc_cam1_scl", I2C
|
|
|
|
|
"vc_cam1_sda", I2C
|
|
|
|
|
"vc_cam2_scl", I2C
|
|
|
|
|
"vc_cam2_sda", I2C
|
|
|
|
|
"vc_cam3_scl", I2C
|
|
|
|
|
"vc_cam3_sda", I2C
|
