2015-05-13 16:34:09 +00:00
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What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Enable/disable tracing on this specific trace entiry.
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Enabling a source implies the source has been configured
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properly and a sink has been identidifed for it. The path
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of coresight components linking the source to the sink is
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configured and managed automatically by the coresight framework.
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What: /sys/bus/coresight/devices/<memory_map>.etm/cpu
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) The CPU this tracing entity is associated with.
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2015-05-13 16:34:10 +00:00
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What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of PE comparator inputs that are
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available for tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of address comparator pairs that are
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available for tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of counters that are available for
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tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates how many external inputs are implemented.
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What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of Context ID comparators that are
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available for tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of VMID comparators that are available
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for tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of sequencer states that are
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implemented.
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What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of resource selection pairs that are
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available for tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of single-shot comparator controls that
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are available for tracing.
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2015-05-13 16:34:11 +00:00
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What: /sys/bus/coresight/devices/<memory_map>.etm/reset
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (W) Cancels all configuration on a trace unit and set it back
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to its boot configuration.
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What: /sys/bus/coresight/devices/<memory_map>.etm/mode
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls various modes supported by this ETM, for example
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P0 instruction tracing, branch broadcast, cycle counting and
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context ID tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/pe
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls which PE to trace.
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What: /sys/bus/coresight/devices/<memory_map>.etm/event
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3.
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What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls the behavior of the events in bank 0 to 3.
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