linux/drivers/clk/mediatek/Makefile

obj-y += clk-mtk.o clk-pll.o clk-gate.o
obj-$(CONFIG_RESET_CONTROLLER) += reset.o
clk: mediatek: Add initial common clock support for Mediatek SoCs. This patch adds common clock support for Mediatek SoCs, including plls, muxes and clock gates. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [sboyd@codeaurora.org: Squelch checkpatch warning in clk-mtk.h] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2015-04-23 08:35:39 +00:00			`obj-y += clk-mtk.o clk-pll.o clk-gate.o`
clk: mediatek: Add reset controller support The pericfg and infracfg units also provide reset lines to several other SoC internal units. This adds a function which can be called from the pericfg and infracfg initialization functions which will register the reset controller using reset_controller_register. The reset controller will provide support for resetting the units connected to the pericfg and infracfg controller. The units resetted by this controller can use the standard reset device tree binding to gain access to the reset lines. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2015-04-23 08:35:40 +00:00			`obj-$(CONFIG_RESET_CONTROLLER) += reset.o`