2019-05-29 14:12:40 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2010-07-29 12:47:48 +00:00
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/*
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* Copyright (C) 2010 SUSE Linux Products GmbH. All rights reserved.
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2011-11-09 00:23:28 +00:00
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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2010-07-29 12:47:48 +00:00
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*
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* Authors:
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* Alexander Graf <agraf@suse.de>
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*/
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#include <linux/kvm_host.h>
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#include <linux/init.h>
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2011-05-27 14:46:24 +00:00
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#include <linux/export.h>
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2019-04-06 01:38:49 +00:00
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#include <linux/kmemleak.h>
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2010-07-29 12:47:48 +00:00
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#include <linux/kvm_para.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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2018-03-28 19:58:11 +00:00
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#include <linux/pagemap.h>
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2010-07-29 12:47:48 +00:00
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#include <asm/reg.h>
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#include <asm/sections.h>
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#include <asm/cacheflush.h>
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#include <asm/disassemble.h>
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2011-11-09 00:23:28 +00:00
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#include <asm/ppc-opcode.h>
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2012-03-15 10:52:13 +00:00
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#include <asm/epapr_hcalls.h>
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2010-07-29 12:47:48 +00:00
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2010-07-29 12:47:57 +00:00
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#define KVM_MAGIC_PAGE (-4096L)
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#define magic_var(x) KVM_MAGIC_PAGE + offsetof(struct kvm_vcpu_arch_shared, x)
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2010-07-29 12:47:59 +00:00
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#define KVM_INST_LWZ 0x80000000
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#define KVM_INST_STW 0x90000000
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#define KVM_INST_LD 0xe8000000
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#define KVM_INST_STD 0xf8000000
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#define KVM_INST_NOP 0x60000000
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#define KVM_INST_B 0x48000000
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#define KVM_INST_B_MASK 0x03ffffff
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#define KVM_INST_B_MAX 0x01ffffff
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2011-11-09 00:23:28 +00:00
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#define KVM_INST_LI 0x38000000
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2010-07-29 12:47:59 +00:00
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2010-07-29 12:47:58 +00:00
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#define KVM_MASK_RT 0x03e00000
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2010-08-05 09:26:04 +00:00
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#define KVM_RT_30 0x03c00000
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2010-08-03 08:39:35 +00:00
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#define KVM_MASK_RB 0x0000f800
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2010-07-29 12:47:59 +00:00
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#define KVM_INST_MFMSR 0x7c0000a6
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KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
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#define SPR_FROM 0
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#define SPR_TO 0x100
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#define KVM_INST_SPR(sprn, moveto) (0x7c0002a6 | \
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(((sprn) & 0x1f) << 16) | \
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(((sprn) & 0x3e0) << 6) | \
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(moveto))
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#define KVM_INST_MFSPR(sprn) KVM_INST_SPR(sprn, SPR_FROM)
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#define KVM_INST_MTSPR(sprn) KVM_INST_SPR(sprn, SPR_TO)
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2010-07-29 12:47:58 +00:00
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2010-07-29 12:48:00 +00:00
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#define KVM_INST_TLBSYNC 0x7c00046c
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2010-07-29 12:48:05 +00:00
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#define KVM_INST_MTMSRD_L0 0x7c000164
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2010-07-29 12:48:04 +00:00
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#define KVM_INST_MTMSRD_L1 0x7c010164
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2010-07-29 12:48:05 +00:00
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#define KVM_INST_MTMSR 0x7c000124
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2010-07-29 12:48:00 +00:00
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2011-11-09 00:23:28 +00:00
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#define KVM_INST_WRTEE 0x7c000106
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2010-07-29 12:48:06 +00:00
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#define KVM_INST_WRTEEI_0 0x7c000146
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#define KVM_INST_WRTEEI_1 0x7c008146
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2010-08-03 08:39:35 +00:00
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#define KVM_INST_MTSRIN 0x7c0001e4
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2010-07-29 12:47:58 +00:00
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static bool kvm_patching_worked = true;
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powerpc/kvm: Move kvm_tmp into .text, shrink to 64K
In some configurations of KVM, guests binary patch themselves to
avoid/reduce trapping into the hypervisor. For some instructions this
requires replacing one instruction with a sequence of instructions.
For those cases we need to write the sequence of instructions
somewhere and then patch the location of the original instruction to
branch to the sequence. That requires that the location of the
sequence be within 32MB of the original instruction.
The current solution for this is that we create a 1MB array in BSS,
write sequences into there, and then free the remainder of the array.
This has a few problems:
- it confuses kmemleak.
- it confuses lockdep.
- it requires mapping kvm_tmp executable, which can cause adjacent
areas to also be mapped executable if we're using 16M pages for the
linear mapping.
- the 32MB limit can be exceeded if the kernel is big enough,
especially with STRICT_KERNEL_RWX enabled, which then prevents the
patching from working at all.
We can fix all those problems by making kvm_tmp just a region of
regular .text. However currently it's 1MB in size, and we don't want
to waste 1MB of text. In practice however I only see ~30KB of kvm_tmp
being used even for an allyes_config. So shrink kvm_tmp to 64K, which
ought to be enough for everyone, and move it into .text.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20190911115746.12433-1-mpe@ellerman.id.au
2019-09-11 11:57:43 +00:00
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extern char kvm_tmp[];
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extern char kvm_tmp_end[];
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2010-07-29 12:48:01 +00:00
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static int kvm_tmp_index;
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2010-07-29 12:47:58 +00:00
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2019-09-11 11:57:45 +00:00
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static void __init kvm_patch_ins(u32 *inst, u32 new_inst)
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2010-07-29 12:47:58 +00:00
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{
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*inst = new_inst;
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flush_icache_range((ulong)inst, (ulong)inst + 4);
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}
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2019-09-11 11:57:45 +00:00
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static void __init kvm_patch_ins_ll(u32 *inst, long addr, u32 rt)
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2010-08-05 09:26:04 +00:00
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{
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#ifdef CONFIG_64BIT
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kvm_patch_ins(inst, KVM_INST_LD | rt | (addr & 0x0000fffc));
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#else
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kvm_patch_ins(inst, KVM_INST_LWZ | rt | (addr & 0x0000fffc));
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#endif
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}
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2019-09-11 11:57:45 +00:00
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static void __init kvm_patch_ins_ld(u32 *inst, long addr, u32 rt)
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2010-07-29 12:47:59 +00:00
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{
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#ifdef CONFIG_64BIT
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kvm_patch_ins(inst, KVM_INST_LD | rt | (addr & 0x0000fffc));
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#else
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kvm_patch_ins(inst, KVM_INST_LWZ | rt | ((addr + 4) & 0x0000fffc));
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#endif
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}
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2019-09-11 11:57:45 +00:00
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static void __init kvm_patch_ins_lwz(u32 *inst, long addr, u32 rt)
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2010-07-29 12:47:59 +00:00
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{
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kvm_patch_ins(inst, KVM_INST_LWZ | rt | (addr & 0x0000ffff));
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}
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2019-09-11 11:57:45 +00:00
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static void __init kvm_patch_ins_std(u32 *inst, long addr, u32 rt)
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2010-07-29 12:47:59 +00:00
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{
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#ifdef CONFIG_64BIT
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kvm_patch_ins(inst, KVM_INST_STD | rt | (addr & 0x0000fffc));
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#else
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kvm_patch_ins(inst, KVM_INST_STW | rt | ((addr + 4) & 0x0000fffc));
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#endif
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}
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2019-09-11 11:57:45 +00:00
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static void __init kvm_patch_ins_stw(u32 *inst, long addr, u32 rt)
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2010-07-29 12:47:59 +00:00
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{
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kvm_patch_ins(inst, KVM_INST_STW | rt | (addr & 0x0000fffc));
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}
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2019-09-11 11:57:45 +00:00
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static void __init kvm_patch_ins_nop(u32 *inst)
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2010-07-29 12:48:00 +00:00
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{
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kvm_patch_ins(inst, KVM_INST_NOP);
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}
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2019-09-11 11:57:45 +00:00
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static void __init kvm_patch_ins_b(u32 *inst, int addr)
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2010-07-29 12:48:02 +00:00
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{
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2010-10-18 22:35:48 +00:00
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#if defined(CONFIG_RELOCATABLE) && defined(CONFIG_PPC_BOOK3S)
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2010-07-29 12:48:02 +00:00
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/* On relocatable kernels interrupts handlers and our code
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can be in different regions, so we don't patch them */
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if ((ulong)inst < (ulong)&__end_interrupts)
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return;
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#endif
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kvm_patch_ins(inst, KVM_INST_B | (addr & KVM_INST_B_MASK));
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}
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2019-09-11 11:57:45 +00:00
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static u32 * __init kvm_alloc(int len)
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2010-07-29 12:48:01 +00:00
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{
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u32 *p;
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powerpc/kvm: Move kvm_tmp into .text, shrink to 64K
In some configurations of KVM, guests binary patch themselves to
avoid/reduce trapping into the hypervisor. For some instructions this
requires replacing one instruction with a sequence of instructions.
For those cases we need to write the sequence of instructions
somewhere and then patch the location of the original instruction to
branch to the sequence. That requires that the location of the
sequence be within 32MB of the original instruction.
The current solution for this is that we create a 1MB array in BSS,
write sequences into there, and then free the remainder of the array.
This has a few problems:
- it confuses kmemleak.
- it confuses lockdep.
- it requires mapping kvm_tmp executable, which can cause adjacent
areas to also be mapped executable if we're using 16M pages for the
linear mapping.
- the 32MB limit can be exceeded if the kernel is big enough,
especially with STRICT_KERNEL_RWX enabled, which then prevents the
patching from working at all.
We can fix all those problems by making kvm_tmp just a region of
regular .text. However currently it's 1MB in size, and we don't want
to waste 1MB of text. In practice however I only see ~30KB of kvm_tmp
being used even for an allyes_config. So shrink kvm_tmp to 64K, which
ought to be enough for everyone, and move it into .text.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20190911115746.12433-1-mpe@ellerman.id.au
2019-09-11 11:57:43 +00:00
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if ((kvm_tmp_index + len) > (kvm_tmp_end - kvm_tmp)) {
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2010-07-29 12:48:01 +00:00
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printk(KERN_ERR "KVM: No more space (%d + %d)\n",
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kvm_tmp_index, len);
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kvm_patching_worked = false;
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return NULL;
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}
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p = (void*)&kvm_tmp[kvm_tmp_index];
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kvm_tmp_index += len;
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return p;
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}
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2010-07-29 12:48:04 +00:00
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extern u32 kvm_emulate_mtmsrd_branch_offs;
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extern u32 kvm_emulate_mtmsrd_reg_offs;
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2010-08-05 13:44:41 +00:00
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extern u32 kvm_emulate_mtmsrd_orig_ins_offs;
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2010-07-29 12:48:04 +00:00
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extern u32 kvm_emulate_mtmsrd_len;
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extern u32 kvm_emulate_mtmsrd[];
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2019-09-11 11:57:45 +00:00
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static void __init kvm_patch_ins_mtmsrd(u32 *inst, u32 rt)
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2010-07-29 12:48:04 +00:00
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{
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u32 *p;
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int distance_start;
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int distance_end;
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ulong next_inst;
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p = kvm_alloc(kvm_emulate_mtmsrd_len * 4);
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if (!p)
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return;
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/* Find out where we are and put everything there */
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distance_start = (ulong)p - (ulong)inst;
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next_inst = ((ulong)inst + 4);
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distance_end = next_inst - (ulong)&p[kvm_emulate_mtmsrd_branch_offs];
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/* Make sure we only write valid b instructions */
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if (distance_start > KVM_INST_B_MAX) {
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kvm_patching_worked = false;
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return;
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}
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/* Modify the chunk to fit the invocation */
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memcpy(p, kvm_emulate_mtmsrd, kvm_emulate_mtmsrd_len * 4);
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p[kvm_emulate_mtmsrd_branch_offs] |= distance_end & KVM_INST_B_MASK;
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2010-08-05 13:44:41 +00:00
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switch (get_rt(rt)) {
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case 30:
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kvm_patch_ins_ll(&p[kvm_emulate_mtmsrd_reg_offs],
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magic_var(scratch2), KVM_RT_30);
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break;
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case 31:
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kvm_patch_ins_ll(&p[kvm_emulate_mtmsrd_reg_offs],
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magic_var(scratch1), KVM_RT_30);
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break;
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default:
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p[kvm_emulate_mtmsrd_reg_offs] |= rt;
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break;
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}
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p[kvm_emulate_mtmsrd_orig_ins_offs] = *inst;
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2010-07-29 12:48:04 +00:00
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flush_icache_range((ulong)p, (ulong)p + kvm_emulate_mtmsrd_len * 4);
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/* Patch the invocation */
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kvm_patch_ins_b(inst, distance_start);
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}
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2010-07-29 12:48:05 +00:00
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extern u32 kvm_emulate_mtmsr_branch_offs;
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extern u32 kvm_emulate_mtmsr_reg1_offs;
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extern u32 kvm_emulate_mtmsr_reg2_offs;
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extern u32 kvm_emulate_mtmsr_orig_ins_offs;
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extern u32 kvm_emulate_mtmsr_len;
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extern u32 kvm_emulate_mtmsr[];
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2019-09-11 11:57:45 +00:00
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static void __init kvm_patch_ins_mtmsr(u32 *inst, u32 rt)
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2010-07-29 12:48:05 +00:00
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{
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u32 *p;
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int distance_start;
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int distance_end;
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ulong next_inst;
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p = kvm_alloc(kvm_emulate_mtmsr_len * 4);
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if (!p)
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return;
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/* Find out where we are and put everything there */
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distance_start = (ulong)p - (ulong)inst;
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next_inst = ((ulong)inst + 4);
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distance_end = next_inst - (ulong)&p[kvm_emulate_mtmsr_branch_offs];
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/* Make sure we only write valid b instructions */
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if (distance_start > KVM_INST_B_MAX) {
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kvm_patching_worked = false;
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return;
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}
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/* Modify the chunk to fit the invocation */
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|
|
memcpy(p, kvm_emulate_mtmsr, kvm_emulate_mtmsr_len * 4);
|
|
|
|
|
p[kvm_emulate_mtmsr_branch_offs] |= distance_end & KVM_INST_B_MASK;
|
2010-08-05 09:26:04 +00:00
|
|
|
|
|
|
|
|
/* Make clobbered registers work too */
|
|
|
|
|
switch (get_rt(rt)) {
|
|
|
|
|
case 30:
|
|
|
|
|
kvm_patch_ins_ll(&p[kvm_emulate_mtmsr_reg1_offs],
|
|
|
|
|
magic_var(scratch2), KVM_RT_30);
|
|
|
|
|
kvm_patch_ins_ll(&p[kvm_emulate_mtmsr_reg2_offs],
|
|
|
|
|
magic_var(scratch2), KVM_RT_30);
|
|
|
|
|
break;
|
|
|
|
|
case 31:
|
|
|
|
|
kvm_patch_ins_ll(&p[kvm_emulate_mtmsr_reg1_offs],
|
|
|
|
|
magic_var(scratch1), KVM_RT_30);
|
|
|
|
|
kvm_patch_ins_ll(&p[kvm_emulate_mtmsr_reg2_offs],
|
|
|
|
|
magic_var(scratch1), KVM_RT_30);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
p[kvm_emulate_mtmsr_reg1_offs] |= rt;
|
|
|
|
|
p[kvm_emulate_mtmsr_reg2_offs] |= rt;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2010-07-29 12:48:05 +00:00
|
|
|
p[kvm_emulate_mtmsr_orig_ins_offs] = *inst;
|
|
|
|
|
flush_icache_range((ulong)p, (ulong)p + kvm_emulate_mtmsr_len * 4);
|
|
|
|
|
|
|
|
|
|
/* Patch the invocation */
|
|
|
|
|
kvm_patch_ins_b(inst, distance_start);
|
|
|
|
|
}
|
|
|
|
|
|
2010-07-29 12:48:06 +00:00
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
|
2011-11-09 00:23:28 +00:00
|
|
|
extern u32 kvm_emulate_wrtee_branch_offs;
|
|
|
|
|
extern u32 kvm_emulate_wrtee_reg_offs;
|
|
|
|
|
extern u32 kvm_emulate_wrtee_orig_ins_offs;
|
|
|
|
|
extern u32 kvm_emulate_wrtee_len;
|
|
|
|
|
extern u32 kvm_emulate_wrtee[];
|
2010-07-29 12:48:06 +00:00
|
|
|
|
2019-09-11 11:57:45 +00:00
|
|
|
static void __init kvm_patch_ins_wrtee(u32 *inst, u32 rt, int imm_one)
|
2010-07-29 12:48:06 +00:00
|
|
|
{
|
|
|
|
|
u32 *p;
|
|
|
|
|
int distance_start;
|
|
|
|
|
int distance_end;
|
|
|
|
|
ulong next_inst;
|
|
|
|
|
|
2011-11-09 00:23:28 +00:00
|
|
|
p = kvm_alloc(kvm_emulate_wrtee_len * 4);
|
2010-07-29 12:48:06 +00:00
|
|
|
if (!p)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/* Find out where we are and put everything there */
|
|
|
|
|
distance_start = (ulong)p - (ulong)inst;
|
|
|
|
|
next_inst = ((ulong)inst + 4);
|
2011-11-09 00:23:28 +00:00
|
|
|
distance_end = next_inst - (ulong)&p[kvm_emulate_wrtee_branch_offs];
|
2010-07-29 12:48:06 +00:00
|
|
|
|
|
|
|
|
/* Make sure we only write valid b instructions */
|
|
|
|
|
if (distance_start > KVM_INST_B_MAX) {
|
|
|
|
|
kvm_patching_worked = false;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Modify the chunk to fit the invocation */
|
2011-11-09 00:23:28 +00:00
|
|
|
memcpy(p, kvm_emulate_wrtee, kvm_emulate_wrtee_len * 4);
|
|
|
|
|
p[kvm_emulate_wrtee_branch_offs] |= distance_end & KVM_INST_B_MASK;
|
|
|
|
|
|
|
|
|
|
if (imm_one) {
|
|
|
|
|
p[kvm_emulate_wrtee_reg_offs] =
|
2012-06-25 13:33:10 +00:00
|
|
|
KVM_INST_LI | __PPC_RT(R30) | MSR_EE;
|
2011-11-09 00:23:28 +00:00
|
|
|
} else {
|
|
|
|
|
/* Make clobbered registers work too */
|
|
|
|
|
switch (get_rt(rt)) {
|
|
|
|
|
case 30:
|
|
|
|
|
kvm_patch_ins_ll(&p[kvm_emulate_wrtee_reg_offs],
|
|
|
|
|
magic_var(scratch2), KVM_RT_30);
|
|
|
|
|
break;
|
|
|
|
|
case 31:
|
|
|
|
|
kvm_patch_ins_ll(&p[kvm_emulate_wrtee_reg_offs],
|
|
|
|
|
magic_var(scratch1), KVM_RT_30);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
p[kvm_emulate_wrtee_reg_offs] |= rt;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
p[kvm_emulate_wrtee_orig_ins_offs] = *inst;
|
|
|
|
|
flush_icache_range((ulong)p, (ulong)p + kvm_emulate_wrtee_len * 4);
|
|
|
|
|
|
|
|
|
|
/* Patch the invocation */
|
|
|
|
|
kvm_patch_ins_b(inst, distance_start);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
extern u32 kvm_emulate_wrteei_0_branch_offs;
|
|
|
|
|
extern u32 kvm_emulate_wrteei_0_len;
|
|
|
|
|
extern u32 kvm_emulate_wrteei_0[];
|
|
|
|
|
|
2019-09-11 11:57:45 +00:00
|
|
|
static void __init kvm_patch_ins_wrteei_0(u32 *inst)
|
2011-11-09 00:23:28 +00:00
|
|
|
{
|
|
|
|
|
u32 *p;
|
|
|
|
|
int distance_start;
|
|
|
|
|
int distance_end;
|
|
|
|
|
ulong next_inst;
|
|
|
|
|
|
|
|
|
|
p = kvm_alloc(kvm_emulate_wrteei_0_len * 4);
|
|
|
|
|
if (!p)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/* Find out where we are and put everything there */
|
|
|
|
|
distance_start = (ulong)p - (ulong)inst;
|
|
|
|
|
next_inst = ((ulong)inst + 4);
|
|
|
|
|
distance_end = next_inst - (ulong)&p[kvm_emulate_wrteei_0_branch_offs];
|
|
|
|
|
|
|
|
|
|
/* Make sure we only write valid b instructions */
|
|
|
|
|
if (distance_start > KVM_INST_B_MAX) {
|
|
|
|
|
kvm_patching_worked = false;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
memcpy(p, kvm_emulate_wrteei_0, kvm_emulate_wrteei_0_len * 4);
|
|
|
|
|
p[kvm_emulate_wrteei_0_branch_offs] |= distance_end & KVM_INST_B_MASK;
|
|
|
|
|
flush_icache_range((ulong)p, (ulong)p + kvm_emulate_wrteei_0_len * 4);
|
2010-07-29 12:48:06 +00:00
|
|
|
|
|
|
|
|
/* Patch the invocation */
|
|
|
|
|
kvm_patch_ins_b(inst, distance_start);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
2010-08-03 08:39:35 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S_32
|
|
|
|
|
|
|
|
|
|
extern u32 kvm_emulate_mtsrin_branch_offs;
|
|
|
|
|
extern u32 kvm_emulate_mtsrin_reg1_offs;
|
|
|
|
|
extern u32 kvm_emulate_mtsrin_reg2_offs;
|
|
|
|
|
extern u32 kvm_emulate_mtsrin_orig_ins_offs;
|
|
|
|
|
extern u32 kvm_emulate_mtsrin_len;
|
|
|
|
|
extern u32 kvm_emulate_mtsrin[];
|
|
|
|
|
|
2019-09-11 11:57:45 +00:00
|
|
|
static void __init kvm_patch_ins_mtsrin(u32 *inst, u32 rt, u32 rb)
|
2010-08-03 08:39:35 +00:00
|
|
|
{
|
|
|
|
|
u32 *p;
|
|
|
|
|
int distance_start;
|
|
|
|
|
int distance_end;
|
|
|
|
|
ulong next_inst;
|
|
|
|
|
|
|
|
|
|
p = kvm_alloc(kvm_emulate_mtsrin_len * 4);
|
|
|
|
|
if (!p)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/* Find out where we are and put everything there */
|
|
|
|
|
distance_start = (ulong)p - (ulong)inst;
|
|
|
|
|
next_inst = ((ulong)inst + 4);
|
|
|
|
|
distance_end = next_inst - (ulong)&p[kvm_emulate_mtsrin_branch_offs];
|
|
|
|
|
|
|
|
|
|
/* Make sure we only write valid b instructions */
|
|
|
|
|
if (distance_start > KVM_INST_B_MAX) {
|
|
|
|
|
kvm_patching_worked = false;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Modify the chunk to fit the invocation */
|
|
|
|
|
memcpy(p, kvm_emulate_mtsrin, kvm_emulate_mtsrin_len * 4);
|
|
|
|
|
p[kvm_emulate_mtsrin_branch_offs] |= distance_end & KVM_INST_B_MASK;
|
|
|
|
|
p[kvm_emulate_mtsrin_reg1_offs] |= (rb << 10);
|
|
|
|
|
p[kvm_emulate_mtsrin_reg2_offs] |= rt;
|
|
|
|
|
p[kvm_emulate_mtsrin_orig_ins_offs] = *inst;
|
|
|
|
|
flush_icache_range((ulong)p, (ulong)p + kvm_emulate_mtsrin_len * 4);
|
|
|
|
|
|
|
|
|
|
/* Patch the invocation */
|
|
|
|
|
kvm_patch_ins_b(inst, distance_start);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
2019-09-11 11:57:45 +00:00
|
|
|
static void __init kvm_map_magic_page(void *data)
|
2010-07-29 12:47:58 +00:00
|
|
|
{
|
2010-08-03 09:32:56 +00:00
|
|
|
u32 *features = data;
|
|
|
|
|
|
2013-10-08 04:02:19 +00:00
|
|
|
ulong in[8] = {0};
|
2010-08-03 09:32:56 +00:00
|
|
|
ulong out[8];
|
|
|
|
|
|
|
|
|
|
in[0] = KVM_MAGIC_PAGE;
|
2014-05-11 23:11:55 +00:00
|
|
|
in[1] = KVM_MAGIC_PAGE | MAGIC_PAGE_FLAG_NOT_MAPPED_NX;
|
2010-08-03 09:32:56 +00:00
|
|
|
|
2013-10-08 04:02:19 +00:00
|
|
|
epapr_hypercall(in, out, KVM_HCALL_TOKEN(KVM_HC_PPC_MAP_MAGIC_PAGE));
|
2010-08-03 09:32:56 +00:00
|
|
|
|
|
|
|
|
*features = out[0];
|
2010-07-29 12:47:58 +00:00
|
|
|
}
|
|
|
|
|
|
2019-09-11 11:57:45 +00:00
|
|
|
static void __init kvm_check_ins(u32 *inst, u32 features)
|
2010-07-29 12:47:58 +00:00
|
|
|
{
|
|
|
|
|
u32 _inst = *inst;
|
|
|
|
|
u32 inst_no_rt = _inst & ~KVM_MASK_RT;
|
|
|
|
|
u32 inst_rt = _inst & KVM_MASK_RT;
|
|
|
|
|
|
|
|
|
|
switch (inst_no_rt) {
|
2010-07-29 12:47:59 +00:00
|
|
|
/* Loads */
|
|
|
|
|
case KVM_INST_MFMSR:
|
|
|
|
|
kvm_patch_ins_ld(inst, magic_var(msr), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
case KVM_INST_MFSPR(SPRN_SPRG0):
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_ld(inst, magic_var(sprg0), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
case KVM_INST_MFSPR(SPRN_SPRG1):
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_ld(inst, magic_var(sprg1), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
case KVM_INST_MFSPR(SPRN_SPRG2):
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_ld(inst, magic_var(sprg2), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
case KVM_INST_MFSPR(SPRN_SPRG3):
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_ld(inst, magic_var(sprg3), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
case KVM_INST_MFSPR(SPRN_SRR0):
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_ld(inst, magic_var(srr0), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
case KVM_INST_MFSPR(SPRN_SRR1):
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_ld(inst, magic_var(srr1), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_DEAR):
|
|
|
|
|
#else
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_DAR):
|
|
|
|
|
#endif
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_ld(inst, magic_var(dar), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
case KVM_INST_MFSPR(SPRN_DSISR):
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_lwz(inst, magic_var(dsisr), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E_MMU
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_MAS0):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_lwz(inst, magic_var(mas0), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_MAS1):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_lwz(inst, magic_var(mas1), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_MAS2):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_ld(inst, magic_var(mas2), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_MAS3):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_lwz(inst, magic_var(mas7_3) + 4, inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_MAS4):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_lwz(inst, magic_var(mas4), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_MAS6):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_lwz(inst, magic_var(mas6), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_MAS7):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_lwz(inst, magic_var(mas7_3), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
#endif /* CONFIG_PPC_BOOK3E_MMU */
|
|
|
|
|
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_SPRG4):
|
|
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_SPRG4R):
|
|
|
|
|
#endif
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_ld(inst, magic_var(sprg4), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_SPRG5):
|
|
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_SPRG5R):
|
|
|
|
|
#endif
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_ld(inst, magic_var(sprg5), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_SPRG6):
|
|
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_SPRG6R):
|
|
|
|
|
#endif
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_ld(inst, magic_var(sprg6), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_SPRG7):
|
|
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_SPRG7R):
|
|
|
|
|
#endif
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_ld(inst, magic_var(sprg7), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_ESR):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_lwz(inst, magic_var(esr), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
case KVM_INST_MFSPR(SPRN_PIR):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_lwz(inst, magic_var(pir), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
2010-07-29 12:47:59 +00:00
|
|
|
/* Stores */
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
case KVM_INST_MTSPR(SPRN_SPRG0):
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_std(inst, magic_var(sprg0), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
case KVM_INST_MTSPR(SPRN_SPRG1):
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_std(inst, magic_var(sprg1), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
case KVM_INST_MTSPR(SPRN_SPRG2):
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_std(inst, magic_var(sprg2), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
case KVM_INST_MTSPR(SPRN_SPRG3):
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_std(inst, magic_var(sprg3), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
case KVM_INST_MTSPR(SPRN_SRR0):
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_std(inst, magic_var(srr0), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
case KVM_INST_MTSPR(SPRN_SRR1):
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_std(inst, magic_var(srr1), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
case KVM_INST_MTSPR(SPRN_DEAR):
|
|
|
|
|
#else
|
|
|
|
|
case KVM_INST_MTSPR(SPRN_DAR):
|
|
|
|
|
#endif
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_std(inst, magic_var(dar), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
case KVM_INST_MTSPR(SPRN_DSISR):
|
2010-07-29 12:47:59 +00:00
|
|
|
kvm_patch_ins_stw(inst, magic_var(dsisr), inst_rt);
|
|
|
|
|
break;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E_MMU
|
|
|
|
|
case KVM_INST_MTSPR(SPRN_MAS0):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_stw(inst, magic_var(mas0), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MTSPR(SPRN_MAS1):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_stw(inst, magic_var(mas1), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MTSPR(SPRN_MAS2):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_std(inst, magic_var(mas2), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MTSPR(SPRN_MAS3):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_stw(inst, magic_var(mas7_3) + 4, inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MTSPR(SPRN_MAS4):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_stw(inst, magic_var(mas4), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MTSPR(SPRN_MAS6):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_stw(inst, magic_var(mas6), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MTSPR(SPRN_MAS7):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_stw(inst, magic_var(mas7_3), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
#endif /* CONFIG_PPC_BOOK3E_MMU */
|
|
|
|
|
|
|
|
|
|
case KVM_INST_MTSPR(SPRN_SPRG4):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_std(inst, magic_var(sprg4), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MTSPR(SPRN_SPRG5):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_std(inst, magic_var(sprg5), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MTSPR(SPRN_SPRG6):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_std(inst, magic_var(sprg6), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
case KVM_INST_MTSPR(SPRN_SPRG7):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_std(inst, magic_var(sprg7), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
case KVM_INST_MTSPR(SPRN_ESR):
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_MAS0_TO_SPRG7)
|
|
|
|
|
kvm_patch_ins_stw(inst, magic_var(esr), inst_rt);
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2010-07-29 12:48:00 +00:00
|
|
|
|
|
|
|
|
/* Nops */
|
|
|
|
|
case KVM_INST_TLBSYNC:
|
|
|
|
|
kvm_patch_ins_nop(inst);
|
|
|
|
|
break;
|
2010-07-29 12:48:04 +00:00
|
|
|
|
|
|
|
|
/* Rewrites */
|
|
|
|
|
case KVM_INST_MTMSRD_L1:
|
2010-08-05 13:44:41 +00:00
|
|
|
kvm_patch_ins_mtmsrd(inst, inst_rt);
|
2010-07-29 12:48:04 +00:00
|
|
|
break;
|
2010-07-29 12:48:05 +00:00
|
|
|
case KVM_INST_MTMSR:
|
|
|
|
|
case KVM_INST_MTMSRD_L0:
|
2010-08-05 09:26:04 +00:00
|
|
|
kvm_patch_ins_mtmsr(inst, inst_rt);
|
2010-07-29 12:48:05 +00:00
|
|
|
break;
|
2011-11-09 00:23:28 +00:00
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
case KVM_INST_WRTEE:
|
|
|
|
|
kvm_patch_ins_wrtee(inst, inst_rt, 0);
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2010-07-29 12:47:58 +00:00
|
|
|
}
|
|
|
|
|
|
2010-08-03 08:39:35 +00:00
|
|
|
switch (inst_no_rt & ~KVM_MASK_RB) {
|
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S_32
|
|
|
|
|
case KVM_INST_MTSRIN:
|
|
|
|
|
if (features & KVM_MAGIC_FEAT_SR) {
|
|
|
|
|
u32 inst_rb = _inst & KVM_MASK_RB;
|
|
|
|
|
kvm_patch_ins_mtsrin(inst, inst_rt, inst_rb);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2010-07-29 12:47:58 +00:00
|
|
|
switch (_inst) {
|
2010-07-29 12:48:06 +00:00
|
|
|
#ifdef CONFIG_BOOKE
|
|
|
|
|
case KVM_INST_WRTEEI_0:
|
2011-11-09 00:23:28 +00:00
|
|
|
kvm_patch_ins_wrteei_0(inst);
|
|
|
|
|
break;
|
|
|
|
|
|
2010-07-29 12:48:06 +00:00
|
|
|
case KVM_INST_WRTEEI_1:
|
2011-11-09 00:23:28 +00:00
|
|
|
kvm_patch_ins_wrtee(inst, 0, 1);
|
2010-07-29 12:48:06 +00:00
|
|
|
break;
|
|
|
|
|
#endif
|
2010-07-29 12:47:58 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2011-12-01 20:22:53 +00:00
|
|
|
extern u32 kvm_template_start[];
|
|
|
|
|
extern u32 kvm_template_end[];
|
|
|
|
|
|
2019-09-11 11:57:45 +00:00
|
|
|
static void __init kvm_use_magic_page(void)
|
2010-07-29 12:47:58 +00:00
|
|
|
{
|
|
|
|
|
u32 *p;
|
|
|
|
|
u32 *start, *end;
|
2010-08-03 09:32:56 +00:00
|
|
|
u32 features;
|
2010-07-29 12:47:58 +00:00
|
|
|
|
|
|
|
|
/* Tell the host to map the magic page to -4096 on all CPUs */
|
2010-08-03 09:32:56 +00:00
|
|
|
on_each_cpu(kvm_map_magic_page, &features, 1);
|
2010-07-29 12:47:58 +00:00
|
|
|
|
|
|
|
|
/* Quick self-test to see if the mapping works */
|
2018-03-28 19:58:11 +00:00
|
|
|
if (!fault_in_pages_readable((const char *)KVM_MAGIC_PAGE, sizeof(u32))) {
|
2010-07-29 12:47:58 +00:00
|
|
|
kvm_patching_worked = false;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Now loop through all code and find instructions */
|
|
|
|
|
start = (void*)_stext;
|
|
|
|
|
end = (void*)_etext;
|
|
|
|
|
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
/*
|
|
|
|
|
* Being interrupted in the middle of patching would
|
|
|
|
|
* be bad for SPRG4-7, which KVM can't keep in sync
|
|
|
|
|
* with emulated accesses because reads don't trap.
|
|
|
|
|
*/
|
|
|
|
|
local_irq_disable();
|
|
|
|
|
|
2011-12-01 20:22:53 +00:00
|
|
|
for (p = start; p < end; p++) {
|
|
|
|
|
/* Avoid patching the template code */
|
|
|
|
|
if (p >= kvm_template_start && p < kvm_template_end) {
|
|
|
|
|
p = kvm_template_end - 1;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
2010-08-03 09:32:56 +00:00
|
|
|
kvm_check_ins(p, features);
|
2011-12-01 20:22:53 +00:00
|
|
|
}
|
2010-07-29 12:47:58 +00:00
|
|
|
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 00:23:30 +00:00
|
|
|
local_irq_enable();
|
|
|
|
|
|
2010-07-29 12:47:58 +00:00
|
|
|
printk(KERN_INFO "KVM: Live patching for a fast VM %s\n",
|
|
|
|
|
kvm_patching_worked ? "worked" : "failed");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int __init kvm_guest_init(void)
|
|
|
|
|
{
|
|
|
|
|
if (!kvm_para_available())
|
powerpc/kvm: Move kvm_tmp into .text, shrink to 64K
In some configurations of KVM, guests binary patch themselves to
avoid/reduce trapping into the hypervisor. For some instructions this
requires replacing one instruction with a sequence of instructions.
For those cases we need to write the sequence of instructions
somewhere and then patch the location of the original instruction to
branch to the sequence. That requires that the location of the
sequence be within 32MB of the original instruction.
The current solution for this is that we create a 1MB array in BSS,
write sequences into there, and then free the remainder of the array.
This has a few problems:
- it confuses kmemleak.
- it confuses lockdep.
- it requires mapping kvm_tmp executable, which can cause adjacent
areas to also be mapped executable if we're using 16M pages for the
linear mapping.
- the 32MB limit can be exceeded if the kernel is big enough,
especially with STRICT_KERNEL_RWX enabled, which then prevents the
patching from working at all.
We can fix all those problems by making kvm_tmp just a region of
regular .text. However currently it's 1MB in size, and we don't want
to waste 1MB of text. In practice however I only see ~30KB of kvm_tmp
being used even for an allyes_config. So shrink kvm_tmp to 64K, which
ought to be enough for everyone, and move it into .text.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20190911115746.12433-1-mpe@ellerman.id.au
2019-09-11 11:57:43 +00:00
|
|
|
return 0;
|
2010-07-29 12:47:58 +00:00
|
|
|
|
2012-03-15 10:52:13 +00:00
|
|
|
if (!epapr_paravirt_enabled)
|
powerpc/kvm: Move kvm_tmp into .text, shrink to 64K
In some configurations of KVM, guests binary patch themselves to
avoid/reduce trapping into the hypervisor. For some instructions this
requires replacing one instruction with a sequence of instructions.
For those cases we need to write the sequence of instructions
somewhere and then patch the location of the original instruction to
branch to the sequence. That requires that the location of the
sequence be within 32MB of the original instruction.
The current solution for this is that we create a 1MB array in BSS,
write sequences into there, and then free the remainder of the array.
This has a few problems:
- it confuses kmemleak.
- it confuses lockdep.
- it requires mapping kvm_tmp executable, which can cause adjacent
areas to also be mapped executable if we're using 16M pages for the
linear mapping.
- the 32MB limit can be exceeded if the kernel is big enough,
especially with STRICT_KERNEL_RWX enabled, which then prevents the
patching from working at all.
We can fix all those problems by making kvm_tmp just a region of
regular .text. However currently it's 1MB in size, and we don't want
to waste 1MB of text. In practice however I only see ~30KB of kvm_tmp
being used even for an allyes_config. So shrink kvm_tmp to 64K, which
ought to be enough for everyone, and move it into .text.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20190911115746.12433-1-mpe@ellerman.id.au
2019-09-11 11:57:43 +00:00
|
|
|
return 0;
|
2010-07-29 12:47:58 +00:00
|
|
|
|
|
|
|
|
if (kvm_para_has_feature(KVM_FEATURE_MAGIC_PAGE))
|
|
|
|
|
kvm_use_magic_page();
|
|
|
|
|
|
2010-08-17 20:08:39 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
2010-08-17 09:41:44 +00:00
|
|
|
/* Enable napping */
|
|
|
|
|
powersave_nap = 1;
|
2010-08-17 20:08:39 +00:00
|
|
|
#endif
|
2010-08-17 09:41:44 +00:00
|
|
|
|
2010-07-29 12:47:58 +00:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
postcore_initcall(kvm_guest_init);
|
