2018-12-11 17:57:48 +00:00
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// SPDX-License-Identifier: GPL-2.0
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2013-03-20 12:00:34 +00:00
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/*
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* Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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2020-11-05 19:27:45 +00:00
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#include <linux/device.h>
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2013-03-20 12:00:34 +00:00
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#include <linux/err.h>
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#include <linux/slab.h>
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static u8 clk_composite_get_parent(struct clk_hw *hw)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *mux_ops = composite->mux_ops;
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struct clk_hw *mux_hw = composite->mux_hw;
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2015-02-12 13:58:30 +00:00
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__clk_hw_set_clk(mux_hw, hw);
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2013-03-20 12:00:34 +00:00
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return mux_ops->get_parent(mux_hw);
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}
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static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *mux_ops = composite->mux_ops;
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struct clk_hw *mux_hw = composite->mux_hw;
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2015-02-12 13:58:30 +00:00
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__clk_hw_set_clk(mux_hw, hw);
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2013-03-20 12:00:34 +00:00
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return mux_ops->set_parent(mux_hw, index);
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}
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static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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2013-04-11 18:31:36 +00:00
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const struct clk_ops *rate_ops = composite->rate_ops;
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struct clk_hw *rate_hw = composite->rate_hw;
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2013-03-20 12:00:34 +00:00
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2015-02-12 13:58:30 +00:00
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__clk_hw_set_clk(rate_hw, hw);
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2013-03-20 12:00:34 +00:00
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2013-04-11 18:31:36 +00:00
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return rate_ops->recalc_rate(rate_hw, parent_rate);
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2013-03-20 12:00:34 +00:00
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}
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2021-10-16 10:50:22 +00:00
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static int clk_composite_determine_rate_for_parent(struct clk_hw *rate_hw,
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struct clk_rate_request *req,
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struct clk_hw *parent_hw,
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const struct clk_ops *rate_ops)
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{
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long rate;
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req->best_parent_hw = parent_hw;
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req->best_parent_rate = clk_hw_get_rate(parent_hw);
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if (rate_ops->determine_rate)
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return rate_ops->determine_rate(rate_hw, req);
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rate = rate_ops->round_rate(rate_hw, req->rate,
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&req->best_parent_rate);
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if (rate < 0)
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return rate;
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req->rate = rate;
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return 0;
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}
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2015-07-07 18:48:08 +00:00
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static int clk_composite_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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2013-09-15 00:37:59 +00:00
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *rate_ops = composite->rate_ops;
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const struct clk_ops *mux_ops = composite->mux_ops;
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struct clk_hw *rate_hw = composite->rate_hw;
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struct clk_hw *mux_hw = composite->mux_hw;
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2015-07-31 00:20:57 +00:00
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struct clk_hw *parent;
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2014-07-02 23:56:45 +00:00
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unsigned long rate_diff;
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unsigned long best_rate_diff = ULONG_MAX;
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2021-10-16 10:50:22 +00:00
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unsigned long best_rate = 0;
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int i, ret;
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2013-09-15 00:37:59 +00:00
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2021-10-16 10:50:22 +00:00
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if (rate_hw && rate_ops &&
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(rate_ops->determine_rate || rate_ops->round_rate) &&
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2021-10-16 10:50:21 +00:00
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mux_hw && mux_ops && mux_ops->set_parent) {
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2015-07-07 18:48:08 +00:00
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req->best_parent_hw = NULL;
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2014-07-02 23:56:45 +00:00
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2015-06-29 23:56:30 +00:00
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
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2021-10-16 10:50:22 +00:00
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struct clk_rate_request tmp_req = *req;
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2015-07-31 00:20:57 +00:00
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parent = clk_hw_get_parent(mux_hw);
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2014-07-02 23:56:45 +00:00
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2021-10-16 10:50:22 +00:00
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ret = clk_composite_determine_rate_for_parent(rate_hw,
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&tmp_req,
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parent,
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rate_ops);
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if (ret)
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return ret;
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req->rate = tmp_req.rate;
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2021-11-03 12:24:41 +00:00
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req->best_parent_hw = tmp_req.best_parent_hw;
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2021-10-16 10:50:22 +00:00
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req->best_parent_rate = tmp_req.best_parent_rate;
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2015-07-07 18:48:08 +00:00
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return 0;
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2014-07-02 23:56:45 +00:00
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}
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2015-06-25 23:53:23 +00:00
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for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) {
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2021-10-16 10:50:22 +00:00
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struct clk_rate_request tmp_req = *req;
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2015-07-31 00:20:57 +00:00
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parent = clk_hw_get_parent_by_index(mux_hw, i);
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2014-07-02 23:56:45 +00:00
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if (!parent)
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continue;
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2021-10-16 10:50:22 +00:00
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ret = clk_composite_determine_rate_for_parent(rate_hw,
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&tmp_req,
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parent,
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rate_ops);
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if (ret)
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2014-07-02 23:56:45 +00:00
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continue;
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2021-10-16 10:50:22 +00:00
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rate_diff = abs(req->rate - tmp_req.rate);
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2014-07-02 23:56:45 +00:00
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2015-07-07 18:48:08 +00:00
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if (!rate_diff || !req->best_parent_hw
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2014-07-02 23:56:45 +00:00
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|| best_rate_diff > rate_diff) {
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2015-07-31 00:20:57 +00:00
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req->best_parent_hw = parent;
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2021-10-16 10:50:22 +00:00
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req->best_parent_rate = tmp_req.best_parent_rate;
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2014-07-02 23:56:45 +00:00
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best_rate_diff = rate_diff;
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2021-10-16 10:50:22 +00:00
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best_rate = tmp_req.rate;
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2014-07-02 23:56:45 +00:00
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}
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if (!rate_diff)
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2015-07-07 18:48:08 +00:00
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return 0;
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2014-07-02 23:56:45 +00:00
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}
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2015-07-07 18:48:08 +00:00
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req->rate = best_rate;
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return 0;
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2021-10-16 10:50:21 +00:00
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} else if (rate_hw && rate_ops && rate_ops->determine_rate) {
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__clk_hw_set_clk(rate_hw, hw);
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return rate_ops->determine_rate(rate_hw, req);
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2013-09-15 00:37:59 +00:00
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} else if (mux_hw && mux_ops && mux_ops->determine_rate) {
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2015-02-12 13:58:30 +00:00
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__clk_hw_set_clk(mux_hw, hw);
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2015-07-07 18:48:08 +00:00
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return mux_ops->determine_rate(mux_hw, req);
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2013-09-15 00:37:59 +00:00
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} else {
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pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
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2015-07-09 20:39:38 +00:00
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return -EINVAL;
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2013-09-15 00:37:59 +00:00
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}
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}
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2013-03-20 12:00:34 +00:00
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static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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2013-04-11 18:31:36 +00:00
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const struct clk_ops *rate_ops = composite->rate_ops;
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struct clk_hw *rate_hw = composite->rate_hw;
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2013-03-20 12:00:34 +00:00
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2015-02-12 13:58:30 +00:00
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__clk_hw_set_clk(rate_hw, hw);
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2013-03-20 12:00:34 +00:00
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2013-04-11 18:31:36 +00:00
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return rate_ops->round_rate(rate_hw, rate, prate);
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2013-03-20 12:00:34 +00:00
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}
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static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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2013-04-11 18:31:36 +00:00
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const struct clk_ops *rate_ops = composite->rate_ops;
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struct clk_hw *rate_hw = composite->rate_hw;
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2013-03-20 12:00:34 +00:00
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2015-02-12 13:58:30 +00:00
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__clk_hw_set_clk(rate_hw, hw);
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2013-03-20 12:00:34 +00:00
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2013-04-11 18:31:36 +00:00
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return rate_ops->set_rate(rate_hw, rate, parent_rate);
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2013-03-20 12:00:34 +00:00
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}
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2016-04-12 08:43:39 +00:00
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static int clk_composite_set_rate_and_parent(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate,
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u8 index)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *rate_ops = composite->rate_ops;
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const struct clk_ops *mux_ops = composite->mux_ops;
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struct clk_hw *rate_hw = composite->rate_hw;
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struct clk_hw *mux_hw = composite->mux_hw;
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unsigned long temp_rate;
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__clk_hw_set_clk(rate_hw, hw);
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__clk_hw_set_clk(mux_hw, hw);
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temp_rate = rate_ops->recalc_rate(rate_hw, parent_rate);
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if (temp_rate > rate) {
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rate_ops->set_rate(rate_hw, rate, parent_rate);
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mux_ops->set_parent(mux_hw, index);
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} else {
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mux_ops->set_parent(mux_hw, index);
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rate_ops->set_rate(rate_hw, rate, parent_rate);
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}
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return 0;
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}
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2013-03-20 12:00:34 +00:00
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static int clk_composite_is_enabled(struct clk_hw *hw)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *gate_ops = composite->gate_ops;
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struct clk_hw *gate_hw = composite->gate_hw;
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2015-02-12 13:58:30 +00:00
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__clk_hw_set_clk(gate_hw, hw);
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2013-03-20 12:00:34 +00:00
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return gate_ops->is_enabled(gate_hw);
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}
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static int clk_composite_enable(struct clk_hw *hw)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *gate_ops = composite->gate_ops;
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struct clk_hw *gate_hw = composite->gate_hw;
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2015-02-12 13:58:30 +00:00
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__clk_hw_set_clk(gate_hw, hw);
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2013-03-20 12:00:34 +00:00
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return gate_ops->enable(gate_hw);
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}
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static void clk_composite_disable(struct clk_hw *hw)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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const struct clk_ops *gate_ops = composite->gate_ops;
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struct clk_hw *gate_hw = composite->gate_hw;
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2015-02-12 13:58:30 +00:00
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__clk_hw_set_clk(gate_hw, hw);
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2013-03-20 12:00:34 +00:00
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gate_ops->disable(gate_hw);
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}
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2020-01-02 23:10:59 +00:00
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static struct clk_hw *__clk_hw_register_composite(struct device *dev,
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const char *name, const char * const *parent_names,
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const struct clk_parent_data *pdata, int num_parents,
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2013-03-20 12:00:34 +00:00
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struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
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2013-04-11 18:31:36 +00:00
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struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
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2013-03-20 12:00:34 +00:00
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struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
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unsigned long flags)
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{
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2016-02-07 08:20:31 +00:00
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struct clk_hw *hw;
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2019-11-15 16:28:55 +00:00
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struct clk_init_data init = {};
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2013-03-20 12:00:34 +00:00
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struct clk_composite *composite;
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struct clk_ops *clk_composite_ops;
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2016-02-07 08:20:31 +00:00
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int ret;
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2013-03-20 12:00:34 +00:00
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composite = kzalloc(sizeof(*composite), GFP_KERNEL);
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2015-05-14 23:47:10 +00:00
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if (!composite)
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2013-03-20 12:00:34 +00:00
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return ERR_PTR(-ENOMEM);
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init.name = name;
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2019-04-25 17:57:37 +00:00
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init.flags = flags;
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2020-01-02 23:10:59 +00:00
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if (parent_names)
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init.parent_names = parent_names;
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else
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init.parent_data = pdata;
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2013-03-20 12:00:34 +00:00
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init.num_parents = num_parents;
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2016-02-07 08:20:31 +00:00
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hw = &composite->hw;
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2013-03-20 12:00:34 +00:00
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clk_composite_ops = &composite->ops;
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if (mux_hw && mux_ops) {
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2014-07-02 23:57:30 +00:00
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if (!mux_ops->get_parent) {
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2016-02-07 08:20:31 +00:00
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hw = ERR_PTR(-EINVAL);
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2013-03-20 12:00:34 +00:00
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goto err;
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}
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composite->mux_hw = mux_hw;
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composite->mux_ops = mux_ops;
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clk_composite_ops->get_parent = clk_composite_get_parent;
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2014-07-02 23:57:30 +00:00
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if (mux_ops->set_parent)
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clk_composite_ops->set_parent = clk_composite_set_parent;
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2013-09-15 00:37:59 +00:00
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if (mux_ops->determine_rate)
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clk_composite_ops->determine_rate = clk_composite_determine_rate;
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2013-03-20 12:00:34 +00:00
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}
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2013-04-11 18:31:36 +00:00
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if (rate_hw && rate_ops) {
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2013-04-11 18:31:37 +00:00
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if (!rate_ops->recalc_rate) {
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2016-02-07 08:20:31 +00:00
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hw = ERR_PTR(-EINVAL);
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2013-03-20 12:00:34 +00:00
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goto err;
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}
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2014-07-02 23:58:14 +00:00
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clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
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2013-03-20 12:00:34 +00:00
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2014-07-02 23:58:14 +00:00
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if (rate_ops->determine_rate)
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clk_composite_ops->determine_rate =
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clk_composite_determine_rate;
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else if (rate_ops->round_rate)
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clk_composite_ops->round_rate =
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|
|
|
clk_composite_round_rate;
|
|
|
|
|
|
|
|
/* .set_rate requires either .round_rate or .determine_rate */
|
|
|
|
if (rate_ops->set_rate) {
|
|
|
|
if (rate_ops->determine_rate || rate_ops->round_rate)
|
|
|
|
clk_composite_ops->set_rate =
|
|
|
|
clk_composite_set_rate;
|
|
|
|
else
|
|
|
|
WARN(1, "%s: missing round_rate op is required\n",
|
|
|
|
__func__);
|
2013-04-11 18:31:37 +00:00
|
|
|
}
|
|
|
|
|
2013-04-11 18:31:36 +00:00
|
|
|
composite->rate_hw = rate_hw;
|
|
|
|
composite->rate_ops = rate_ops;
|
2013-03-20 12:00:34 +00:00
|
|
|
}
|
|
|
|
|
2016-04-12 08:43:39 +00:00
|
|
|
if (mux_hw && mux_ops && rate_hw && rate_ops) {
|
|
|
|
if (mux_ops->set_parent && rate_ops->set_rate)
|
|
|
|
clk_composite_ops->set_rate_and_parent =
|
|
|
|
clk_composite_set_rate_and_parent;
|
|
|
|
}
|
|
|
|
|
2013-03-20 12:00:34 +00:00
|
|
|
if (gate_hw && gate_ops) {
|
|
|
|
if (!gate_ops->is_enabled || !gate_ops->enable ||
|
|
|
|
!gate_ops->disable) {
|
2016-02-07 08:20:31 +00:00
|
|
|
hw = ERR_PTR(-EINVAL);
|
2013-03-20 12:00:34 +00:00
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
composite->gate_hw = gate_hw;
|
|
|
|
composite->gate_ops = gate_ops;
|
|
|
|
clk_composite_ops->is_enabled = clk_composite_is_enabled;
|
|
|
|
clk_composite_ops->enable = clk_composite_enable;
|
|
|
|
clk_composite_ops->disable = clk_composite_disable;
|
|
|
|
}
|
|
|
|
|
|
|
|
init.ops = clk_composite_ops;
|
|
|
|
composite->hw.init = &init;
|
|
|
|
|
2016-02-07 08:20:31 +00:00
|
|
|
ret = clk_hw_register(dev, hw);
|
|
|
|
if (ret) {
|
|
|
|
hw = ERR_PTR(ret);
|
2013-03-20 12:00:34 +00:00
|
|
|
goto err;
|
2016-02-07 08:20:31 +00:00
|
|
|
}
|
2013-03-20 12:00:34 +00:00
|
|
|
|
|
|
|
if (composite->mux_hw)
|
2016-02-07 08:20:31 +00:00
|
|
|
composite->mux_hw->clk = hw->clk;
|
2013-03-20 12:00:34 +00:00
|
|
|
|
2013-04-11 18:31:36 +00:00
|
|
|
if (composite->rate_hw)
|
2016-02-07 08:20:31 +00:00
|
|
|
composite->rate_hw->clk = hw->clk;
|
2013-03-20 12:00:34 +00:00
|
|
|
|
|
|
|
if (composite->gate_hw)
|
2016-02-07 08:20:31 +00:00
|
|
|
composite->gate_hw->clk = hw->clk;
|
2013-03-20 12:00:34 +00:00
|
|
|
|
2016-02-07 08:20:31 +00:00
|
|
|
return hw;
|
2013-03-20 12:00:34 +00:00
|
|
|
|
|
|
|
err:
|
|
|
|
kfree(composite);
|
2016-02-07 08:20:31 +00:00
|
|
|
return hw;
|
|
|
|
}
|
|
|
|
|
2020-01-02 23:10:59 +00:00
|
|
|
struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
|
|
|
|
const char * const *parent_names, int num_parents,
|
|
|
|
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
|
|
|
|
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
|
|
|
|
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
|
|
|
return __clk_hw_register_composite(dev, name, parent_names, NULL,
|
|
|
|
num_parents, mux_hw, mux_ops,
|
|
|
|
rate_hw, rate_ops, gate_hw,
|
|
|
|
gate_ops, flags);
|
|
|
|
}
|
2020-07-30 01:22:50 +00:00
|
|
|
EXPORT_SYMBOL_GPL(clk_hw_register_composite);
|
2020-01-02 23:10:59 +00:00
|
|
|
|
|
|
|
struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
|
|
|
|
const char *name,
|
|
|
|
const struct clk_parent_data *parent_data,
|
|
|
|
int num_parents,
|
|
|
|
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
|
|
|
|
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
|
|
|
|
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
|
|
|
return __clk_hw_register_composite(dev, name, NULL, parent_data,
|
|
|
|
num_parents, mux_hw, mux_ops,
|
|
|
|
rate_hw, rate_ops, gate_hw,
|
|
|
|
gate_ops, flags);
|
|
|
|
}
|
|
|
|
|
2016-02-07 08:20:31 +00:00
|
|
|
struct clk *clk_register_composite(struct device *dev, const char *name,
|
|
|
|
const char * const *parent_names, int num_parents,
|
|
|
|
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
|
|
|
|
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
|
|
|
|
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
|
|
|
struct clk_hw *hw;
|
|
|
|
|
|
|
|
hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
|
|
|
|
mux_hw, mux_ops, rate_hw, rate_ops, gate_hw, gate_ops,
|
|
|
|
flags);
|
|
|
|
if (IS_ERR(hw))
|
|
|
|
return ERR_CAST(hw);
|
|
|
|
return hw->clk;
|
2013-03-20 12:00:34 +00:00
|
|
|
}
|
2021-09-01 22:25:24 +00:00
|
|
|
EXPORT_SYMBOL_GPL(clk_register_composite);
|
2016-03-23 16:38:24 +00:00
|
|
|
|
2020-01-02 23:10:59 +00:00
|
|
|
struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
|
|
|
|
const struct clk_parent_data *parent_data,
|
|
|
|
int num_parents,
|
|
|
|
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
|
|
|
|
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
|
|
|
|
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
|
|
|
struct clk_hw *hw;
|
|
|
|
|
|
|
|
hw = clk_hw_register_composite_pdata(dev, name, parent_data,
|
|
|
|
num_parents, mux_hw, mux_ops, rate_hw, rate_ops,
|
|
|
|
gate_hw, gate_ops, flags);
|
|
|
|
if (IS_ERR(hw))
|
|
|
|
return ERR_CAST(hw);
|
|
|
|
return hw->clk;
|
|
|
|
}
|
|
|
|
|
2016-03-23 16:38:24 +00:00
|
|
|
void clk_unregister_composite(struct clk *clk)
|
|
|
|
{
|
|
|
|
struct clk_composite *composite;
|
|
|
|
struct clk_hw *hw;
|
|
|
|
|
|
|
|
hw = __clk_get_hw(clk);
|
|
|
|
if (!hw)
|
|
|
|
return;
|
|
|
|
|
|
|
|
composite = to_clk_composite(hw);
|
|
|
|
|
|
|
|
clk_unregister(clk);
|
|
|
|
kfree(composite);
|
|
|
|
}
|
2019-11-15 16:28:56 +00:00
|
|
|
|
|
|
|
void clk_hw_unregister_composite(struct clk_hw *hw)
|
|
|
|
{
|
|
|
|
struct clk_composite *composite;
|
|
|
|
|
|
|
|
composite = to_clk_composite(hw);
|
|
|
|
|
|
|
|
clk_hw_unregister(hw);
|
|
|
|
kfree(composite);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(clk_hw_unregister_composite);
|
2020-11-05 19:27:45 +00:00
|
|
|
|
|
|
|
static void devm_clk_hw_release_composite(struct device *dev, void *res)
|
|
|
|
{
|
|
|
|
clk_hw_unregister_composite(*(struct clk_hw **)res);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct clk_hw *__devm_clk_hw_register_composite(struct device *dev,
|
|
|
|
const char *name, const char * const *parent_names,
|
|
|
|
const struct clk_parent_data *pdata, int num_parents,
|
|
|
|
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
|
|
|
|
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
|
|
|
|
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
|
|
|
struct clk_hw **ptr, *hw;
|
|
|
|
|
|
|
|
ptr = devres_alloc(devm_clk_hw_release_composite, sizeof(*ptr),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!ptr)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
hw = __clk_hw_register_composite(dev, name, parent_names, pdata,
|
|
|
|
num_parents, mux_hw, mux_ops, rate_hw,
|
|
|
|
rate_ops, gate_hw, gate_ops, flags);
|
|
|
|
|
|
|
|
if (!IS_ERR(hw)) {
|
|
|
|
*ptr = hw;
|
|
|
|
devres_add(dev, ptr);
|
|
|
|
} else {
|
|
|
|
devres_free(ptr);
|
|
|
|
}
|
|
|
|
|
|
|
|
return hw;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
|
|
|
|
const char *name,
|
|
|
|
const struct clk_parent_data *parent_data,
|
|
|
|
int num_parents,
|
|
|
|
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
|
|
|
|
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
|
|
|
|
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
|
|
|
return __devm_clk_hw_register_composite(dev, name, NULL, parent_data,
|
|
|
|
num_parents, mux_hw, mux_ops,
|
|
|
|
rate_hw, rate_ops, gate_hw,
|
|
|
|
gate_ops, flags);
|
|
|
|
}
|