2005-04-16 22:20:36 +00:00
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#ifndef __ASM_SYSTEM_H
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#define __ASM_SYSTEM_H
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#include <linux/kernel.h>
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#include <asm/segment.h>
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2007-05-08 07:35:02 +00:00
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#include <asm/cmpxchg.h>
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2005-04-16 22:20:36 +00:00
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#ifdef __KERNEL__
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#define __STR(x) #x
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#define STR(x) __STR(x)
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#define __SAVE(reg,offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
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#define __RESTORE(reg,offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
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/* frame pointer must be last for get_wchan */
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2006-09-26 08:52:41 +00:00
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#define SAVE_CONTEXT "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
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#define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
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2005-04-16 22:20:36 +00:00
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#define __EXTRA_CLOBBER \
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,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
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2006-09-26 08:52:41 +00:00
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/* Save restore flags to clear handle leaking NT */
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2005-04-16 22:20:36 +00:00
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#define switch_to(prev,next,last) \
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asm volatile(SAVE_CONTEXT \
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"movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
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"movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
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"call __switch_to\n\t" \
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".globl thread_return\n" \
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"thread_return:\n\t" \
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"movq %%gs:%P[pda_pcurrent],%%rsi\n\t" \
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"movq %P[thread_info](%%rsi),%%r8\n\t" \
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2006-06-26 11:56:16 +00:00
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LOCK_PREFIX "btr %[tif_fork],%P[ti_flags](%%r8)\n\t" \
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2005-04-16 22:20:36 +00:00
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"movq %%rax,%%rdi\n\t" \
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"jc ret_from_fork\n\t" \
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RESTORE_CONTEXT \
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: "=a" (last) \
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: [next] "S" (next), [prev] "D" (prev), \
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[threadrsp] "i" (offsetof(struct task_struct, thread.rsp)), \
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[ti_flags] "i" (offsetof(struct thread_info, flags)),\
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[tif_fork] "i" (TIF_FORK), \
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[thread_info] "i" (offsetof(struct task_struct, thread_info)), \
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[pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
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: "memory", "cc" __EXTRA_CLOBBER)
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extern void load_gs_index(unsigned);
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/*
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* Load a segment. Fall back on loading the zero
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* segment if something goes wrong..
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*/
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#define loadsegment(seg,value) \
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asm volatile("\n" \
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"1:\t" \
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"movl %k0,%%" #seg "\n" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3:\t" \
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"movl %1,%%" #seg "\n\t" \
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"jmp 2b\n" \
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".previous\n" \
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".section __ex_table,\"a\"\n\t" \
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".align 8\n\t" \
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".quad 1b,3b\n" \
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".previous" \
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: :"r" (value), "r" (0))
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/*
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* Clear and set 'TS' bit respectively
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*/
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#define clts() __asm__ __volatile__ ("clts")
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static inline unsigned long read_cr0(void)
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{
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unsigned long cr0;
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asm volatile("movq %%cr0,%0" : "=r" (cr0));
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return cr0;
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}
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static inline void write_cr0(unsigned long val)
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{
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asm volatile("movq %0,%%cr0" :: "r" (val));
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}
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static inline unsigned long read_cr3(void)
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{
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unsigned long cr3;
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asm("movq %%cr3,%0" : "=r" (cr3));
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return cr3;
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}
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[PATCH] x86-64: Remove duplicated code for reading control registers
On Tue, Mar 13, 2007 at 05:33:09AM -0700, Randy.Dunlap wrote:
> On Tue, 13 Mar 2007, Glauber de Oliveira Costa wrote:
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> > Tiny cleanup:
> >
> > In x86_64, the same functions for reading cr3 and writing cr{3,4} are
> > defined in tlbflush.h and system.h, whith just a name change.
> > The only difference is the clobbering of memory, which seems a safe, and
> > even needed change for the write_cr4. This patch removes the duplicate.
> > write_cr3() is moved to system.h for consistency.
>
> missing patch.....
>
thanks. Attached now
--
Glauber de Oliveira Costa
Red Hat Inc.
"Free as in Freedom"
Signed-off-by: Andi Kleen <ak@suse.de>
2007-05-02 17:27:06 +00:00
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static inline void write_cr3(unsigned long val)
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{
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asm volatile("movq %0,%%cr3" :: "r" (val) : "memory");
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}
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2005-04-16 22:20:36 +00:00
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static inline unsigned long read_cr4(void)
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{
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unsigned long cr4;
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asm("movq %%cr4,%0" : "=r" (cr4));
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return cr4;
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}
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static inline void write_cr4(unsigned long val)
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{
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[PATCH] x86-64: Remove duplicated code for reading control registers
On Tue, Mar 13, 2007 at 05:33:09AM -0700, Randy.Dunlap wrote:
> On Tue, 13 Mar 2007, Glauber de Oliveira Costa wrote:
>
> > Tiny cleanup:
> >
> > In x86_64, the same functions for reading cr3 and writing cr{3,4} are
> > defined in tlbflush.h and system.h, whith just a name change.
> > The only difference is the clobbering of memory, which seems a safe, and
> > even needed change for the write_cr4. This patch removes the duplicate.
> > write_cr3() is moved to system.h for consistency.
>
> missing patch.....
>
thanks. Attached now
--
Glauber de Oliveira Costa
Red Hat Inc.
"Free as in Freedom"
Signed-off-by: Andi Kleen <ak@suse.de>
2007-05-02 17:27:06 +00:00
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asm volatile("movq %0,%%cr4" :: "r" (val) : "memory");
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2005-04-16 22:20:36 +00:00
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}
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#define stts() write_cr0(8 | read_cr0())
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#define wbinvd() \
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__asm__ __volatile__ ("wbinvd": : :"memory");
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2006-01-12 09:05:27 +00:00
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/*
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* On SMP systems, when the scheduler does migration-cost autodetection,
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* it needs a way to flush as much of the CPU's caches as possible.
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*/
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static inline void sched_cacheflush(void)
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{
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wbinvd();
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}
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2005-04-16 22:20:36 +00:00
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#endif /* __KERNEL__ */
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#define nop() __asm__ __volatile__ ("nop")
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() do {} while(0)
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do {} while(0)
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#endif
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*/
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#define mb() asm volatile("mfence":::"memory")
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#define rmb() asm volatile("lfence":::"memory")
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#ifdef CONFIG_UNORDERED_IO
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#define wmb() asm volatile("sfence" ::: "memory")
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#else
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#define wmb() asm volatile("" ::: "memory")
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#endif
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#define read_barrier_depends() do {} while(0)
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2006-02-05 07:28:05 +00:00
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#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
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2005-04-16 22:20:36 +00:00
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#define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
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2006-07-03 07:24:45 +00:00
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#include <linux/irqflags.h>
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2006-01-17 06:03:47 +00:00
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2005-04-16 22:20:36 +00:00
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void cpu_idle_wait(void);
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extern unsigned long arch_align_stack(unsigned long sp);
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2006-06-26 11:56:16 +00:00
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extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
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2005-04-16 22:20:36 +00:00
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#endif
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